KS641632K

General Information SDRAM SDRAM Product Guide November 2007 Memory Division November 2007 General Information A. SDRAM Component Ordering Information 1 2 3 4 5 6 7 8 9 10 11 SDRAM K4 SXXXXXXX-XXXX SAMSUNG Memory DRAM Product Density & Refresh Organization Speed Temperature & Power Package Type Revision Interface (VDD, VDDQ) Bank 1. SAMSUNG Memory : K 8. Revision M A B C D E F H : 1st Gen. : 2nd Gen. : 3rd Gen. : 4th Gen. : 5th Gen. : 6th Gen. : 7th Gen : 9th Gen J : 11th Gen. K : 12th Gen N : 14th Gen 2. DRAM : 4 3. Product S : SDRAM 4. Density & Refresh 16 : 16Mb, 4K/64ms 64 : 64Mb, 4K/64ms 28 : 128Mb, 4K/64ms 56 : 256Mb, 8K/64ms 51 : 512Mb, 8K/64ms 5. Organization 04 : 06 : 07 : 08 : 16 : 32 : 6. Bank 2 : 2 Banks 3 : 4 Banks x4 x 4 Stack (Flex frame) x 8 Stack (Flex frame) x8 x16 x32 9. Package Type U : TSOP II (Lead-free)*1 T : TSOP II V : sTSOP II (Lead-free)*1 N : sTSOP II (Lead-free & Halogen-free)*1 L : TSOP II Note 1: All of Lead-free or Halogen-free product are in compliance with RoHS 10. Temperature & Power C : Commercial Temp.( 0°C ~ 70°C) & Normal Power L : Commercial Temp.( 0°C ~ 70°C) & Low Power I : Industrial Temp.( -40°C ~ 85°C) & Normal Power P : Industrial Temp.( -40°C ~ 85°C) & Low Power 11. Speed (Default CL= 3) 75 : 7.5ns, PC133 (133MHz CL=3) 60 : 6.0ns (166MHz CL=3) 50 : 5.0ns (200MHz CL=3) 7. Interface ( VDD, VDDQ) 2 : LVTTL (3.3V, 3.3V) November 2007 General Information B. SDRAM Component Product Guide Density Bank Part Number K4S640832K 64Mb K-die 4Banks K4S641632K K4S640832N 64Mb N-die 4Banks K4S641632N K4S280432I 128Mb I-die 4Banks K4S280832I K4S281632I K4S280432K 128Mb K-die 4Banks K4S280832K K4S281632K K4S560432H 256Mb H-die 4Banks K4S560832H K4S561632H K4S560432J 256Mb J-die 4Banks K4S560832J K4S561632J K4S510432D 512Mb D-die 4Banks K4S510832D K4S511632D Note 1 : U : TSOP(II) (Lead-free) L : TSOP(II) (Lead-free & Halogen-free) Note 2 : Temperature and Power C L Description Temperature, Normal Power Temperature, Low Power Package*1 & Power*2 & Speed*3 UC75 UL75 UC50/C60/C75 UL50/L60/L75 LC75 LL75 LC50/C60/C75 LL50/L60/L75 UC75 UL75 UC75 UL75 UC60/C75 UL60/L75 U*4C75 UL75 UC75 UL75 UC60/C75 UL60/L75 UC75 UL75 UC75 UL75 UC60/C75 UL60/L75 U*4C75 UL75 UC75 UL75 UC60/C75 UL60/L75 UC75 UL75 UC75 UL75 UC75 UL75 Org. 8M x 8 LVTTL 4M x 16 8M x 8 LVTTL 4M x 16 32M x 4 16M x 8 8M x 16 32M x 4 16M x 8 8M x 16 64M x 4 32M x 8 16M x 16 64M x 4 32M x 8 16M x 16 128M x 4 64M x 8 32M x 16 LVTTL 8K/64ms 3.3 ± 0.3V LVTTL 8K/64ms 3.3 ± 0.3V LVTTL 8K/64ms 3.3 ± 0.3V LVTTL 4K/64ms 3.3 ± 0.3V LVTTL 4K/64ms 3.3 ± 0.3V 4K/64ms 3.3 ± 0.3V 4K/64ms 3.3 ± 0.3V Interface Refresh Power (V) Package SDRAM Avail. Lead-free 54pin TSOP(II) EOL DEC. ’08 Lead-free & Halogenfree 54pin TSOP(II) 4Q’07 CS Lead-free 54pin TSOP(II) EOL AUG. ’08 Lead-free & Halogenfree 54pin TSOP(II)*4 Now Lead-free 54pin TSOP(II) EOL SEP. ’08 Lead-free & Halogenfree 54pin TSOP(II)*4 Now Lead-free 54pin TSOP(II) Now Note 3 : Speed 75 60 50 Description 7.5ns, PC133 (133Mhz @ CL=3) 6.0 ns (166Mhz @ CL=3) 5.0 ns (200Mhz @ CL=3) * All products have backward compatibility with PC100. - Commercial Temp (0°C < Ta < 70°C) Note 4 : 128Mb K-die SDR and 256Mb J-die SDR DRAMs support Lead-free & Halogen-free package with Lead-free package code(-U) November 2007 General Information C. Industrial Temperature SDRAM Component Product Guide Density 64Mb K-die 64Mb N-die 128Mb I-die 128Mb K-die 256Mb H-die 256Mb J-die Bank 4Banks 4Banks 4Banks 4Banks 4Banks 4Banks Part Number KS641632K KS641632N K4S281632I K4S281632K K4S561632H K4S561632J Package*1 & Power*2 & Speed*3 UI60/I75 UP60/P75 LI60/I75 LP60/P75 UI60/I75 UP60/P75 U*4I60/I75 UP60/P75 UI60/I75 UP60/P75 U*4I60/I75 UP60/P75 Org. 4M x 16 4M x 16 8M x 16 8M x 16 16M x 16 16M x 16 Interface LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Refresh 4K/64ms 4K/64ms 4K/64ms 4K/64ms 8K/64ms 8K/64ms Power (V) 3.3 ± 0.3V 3.3 ± 0.3V 3.3 ± 0.3V 3.3 ± 0.3V 3.3 ± 0.3V 3.3 ± 0.3V Package SDRAM Avail. EOL DEC.’08 1Q’08 EOL AUG.’08 Now EOL SEP.’08 Now Lead-free 54pin TSOP(II) Lead-free & Halogen-free 54pin TSOP(II) Lead-free 54pin TSOP(II) Lead-free & Halogen-free 54pin TSOP(II)*4 Lead-free 54pin TSOP(II) Lead-free & Halogen-free 54pin TSOP(II)*4 Note 1 : U : TSOP(II) (Lead-free) L : TSOP(II) (Lead-free & Halogen-free) Note 2 : Temperature and Power I P Description Industrial Temperature, Normal Power Industrial Temperature, Low Power Note 3 : Speed 75 60 50 Description 7.5ns, PC133 (133Mhz @ CL=3) 6.0 ns (166Mhz @ CL=3) 5.0 ns (200Mhz @ CL=3) - Industrial Temp (-40°C < Ta < 85°C) Note 4 : 128Mb K-die SDR and 256Mb J-die SDR DRAMs support Lead-free & Halogen-free package with Lead-free package code(-U) November 2007 General Information D. SDRAM Module Ordering Information 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM MXXXSXXXXXXX-XXX Memory Module DIMM Configuration Data bits Feature Depth Refresh, # of Banks in Comp. & Interface Speed Power PCB revision & Type Package Component Revision Composition Component 1. Memory Module : M 7. Composition Component 0 3 4 8 9 : : : : : x4 x8 x16 x 4 Stack (Flexframe) x 8 Stack (Flexframe) 2. DIMM Configuration 3 : DIMM 4 : SODIMM 3. Data Bits 63 : x63 PC100 / PC133 µSODIMM with SPD for 144pin 64 : x64 PC100 / PC133 SODIMM with SPD for 144pin (Intel/JEDEC) 66 : x64 Unbuffered DIMM with SPD for 144pin/168pin (Intel/JEDEC) 74 : x72 /ECC Unbuffered DIMM with SPD for 168pin (Intel/JEDEC) 77 : x72 /ECC PLL + Register DIMM with SPD for 168pin (Intel PC100) 90 : x72 /ECC PLL + Register DIMM with SPD for 168pin (JEDEC PC133) 4. Feature S : SDRAM 5. Depth 16 : 16M 32 : 32M 64 : 64M 28 : 128M 56 : 256M 09 17 33 65 29 59 : 8M (for 128Mb/512Mb) : 16M (for 128Mb/512Mb) : 32M (for 128Mb/512Mb) : 64M (for 128Mb/512Mb) : 128M (for 128Mb/512Mb) : 256M (for 128Mb/512Mb) 8. Component Revision M B D F J : 1st Gen. : 3rd Gen. : 5th Gen. : 7th Gen. : 11h Gen. A C E H : : : : 2nd Gen. 4th Gen. 6th Gen. 9h Gen. 9. Package T N U V : : : : TSOP(II) (400mil) sTSOP(II) (400mil) TSOP(II) Lead-free (400mil) sTSOP(II) Lead-free (400mil) 10. PCB Revision & Type 0 : Mother PCB 2 : 2nd Rev. U : Low Profile DIMM 1 : 1st Rev. 3 : 3rd Rev. S : 4Layer PCB. 11. Power C : Commercial Normal L : Commercial Low ( 0°C ~ 70°C) ( 0°C ~ 70°C) 6. Refresh, # of Banks in comp. & Interface 2: 5: 4K/ 64ms Ref., 4Banks & LVTTL 8K/ 64ms Ref., 4Banks & LVTTL 12. Speed (Default CL= 3 ) 7A : PC133 (133MHz CL=3/PC100 CL2) November 2007 General Information E. SDRAM Module Product Guide Org. Density Part No. Speed Composition Comp. Version 9 pcs 256Mb 256Mb 256Mb H-die H-die H-die 3.3 V 4 Power (V) Internal Banks External Banks 1 1 1 SDRAM Feature Avail. 168pin PC133 Registered DIMM 32Mx72 64Mx72 256MB 512MB M390S3253HU1 M390S6450HU1 M390S6450HUU C7A C7A C7A 32M x 8 * DS, 1500mil DS, 1700mil DS, 1200mil EOL JUN.’08 64M x 4 * 18 pcs 64M x 4 * 18 pcs 168pin PC133 Unbuffered DIMM 8Mx64 64MB M366S0924IUS M366S1723IUS 16Mx64 128MB M366S1654HUS M366S1654JUS 16Mx72 32Mx64 32Mx72 32Mx64 64Mx64 512MB 256MB M374S1723IUS M366S3323IUS M374S3323IUS M366S3253JUS M366S6453HUS M366S6453JUS C7A C7A C7A C7A C7A C7A C7A C7A C7A C7A 8M x 16 * 16M x 8 * 16M x 16 * 16M x 16 * 16M x 8 * 4 pcs 8 pcs 4 pcs 4 pcs 9 pcs 128Mb 128Mb 256Mb 256Mb 128Mb 128Mb 128Mb 256Mb 256Mb 256Mb I-die I-die H-die J-die I-die I-die I-die J-die H-die J-die 3.3V 4 1 1 1 1 1 2 2 1 2 2 SS, 1000mil SS, 1375mil SS, 1000mil SS, 1000mil SS, 1375mil DS, 1375mil DS, 1375mil SS, 1375mil DS, 1375mil DS, 1375mil Now EOL JUN.’08 Now EOL JUN.’08 EOL JUN.’08 EOL JUN.’08 Now 16M x 8 * 16 pcs 16M x 8 * 18 pcs 32M x 8 * 8 pcs 32M x 8 * 16 pcs 32M x 8 * 16 pcs 144pin PC133 SODIMM 16Mx64 128MB M464S1724IUS M464S1724KUS 32Mx64 256MB M464S3254HUS M464S3254JUS 64Mx64 512MB M464S6453HV0 M464S6453JV0 L7A L7A L7A L7A L7A L7A 8M x 16 * 8M x 16 * 16M x 16 * 16M x 16 * 8 pcs 8 pcs 8 pcs 8 pcs 128Mb 128Mb 256Mb 256Mb 256Mb 256Mb I-die K-die H-die J-die H-die J-die 3.3V 4 1 1 1 1 2 2 DS, 1250mil DS, 1250mil DS, 1250mil DS, 1250mil DS, 1250mil DS, 1250mil EOL JUN.’08 Now EOL JUN.’08 Now EOL JUN.’08 Now 32M x 8 * 16 pcs 32M x 8 * 16 pcs November 2007 General Information F. Package Dimension SDRAM Unit : mm #54 #28 (0.80) (0.50) (10°) (10°) 0.125 1.20 MAX +0.075 - 0.035 10.16 ± 0.10 (1.50) (0.80) 0.665 ± 0.05 0.210 ± 0.05 (R 0.1 5) (10°) 1.00 ± 0.10 22.22 ± 0.10 (0.50) #1 (1.50) #27 11.76 ± 0.20 (10.76) 0.05 MIN 0. 15 (0.71) 0.80TYP [0.80 ± 0.08] 0.35 - 0.05 +0.10 (R 0.075 MAX 0. 25 ) (R (R 0. 25 ) NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY 54Pin TSOP(II) Package Dimension [ (10°) [ (4°) 0.10 MAX ) (0° ∼ 8°) November 2007 0.45 ~ 0.75 0.25TYP General Information SDRAM For further information, semiconductor@samsung.com November 2007