KS86C6308

KS86C6308/P6308 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. Many SAM88RCRI microcontrollers have an external interface that provides access to external memory and other peripheral devices. KS86C6308/P6308 MICROCONTROLLER The KS86C6308/P6308 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM88RCRI CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The KS86C6308 has 8 K bytes of program memory on-chip. Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core: — Five configurable I/O ports (32 pins) — 20 bit-programmable pins for external interrupts — 8-bit timer/counter and 16-bit timwe/counter with three operating modes — Full speed low speed USB function The KS86C6308/P6308 is a versatile microcontroller that can be used in a wide range of full/low speed USB support general purpose applications. It is especially suitable for use as a keyboard with hub controller and is available in a 64-pin SDIP and a 64-pin QFP package. OTP The KS86C6308 microcontroller is also available in OTP (One Time Programmable) version, KS86P6308. KS86P6308 microcontroller has an on-chip 8-Kbyte one-time-programmable EPROM instead of masked ROM. The KS86P6308 is comparable to KS86C6308, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW KS86C6308/P6308 (Preliminary Spec) FEATURES CPU • SAM88RCRI CPU core Timer A • One 8-bit basic timer for watchdog function and programmable oscillation stabilization programmable 8-bit timer internal generation function interval, capture, PWM mode match/capture overflow interrupt Memory • • 8-KB Internal program memory(ROM) 256-byte internal register file (160-byte:General Purpose) Instruction Set • • 41 instructions IDLE and STOP instructions added for powerdown modes Timer B • Programmable 16-bit timer interval generation function interval, capture, PWM mode match/capture overflow interrupt Universal Serial Bus with HUB • • 1 upstream port 4 downstream port and one embedded function each port supports separated enable LED builtin 3.3 V voltage regulator Instruction Execution Time • 332ns at 12 MHz fOSC Interrupts • • 32 interrupt sources with one vector, each source has its pending bits One level, one vector interrupt structure USB/GPIO Function • Upstream port Operation Temperature Range • - 40 °C to + 85 °C Oscillation Frequency • • 12 MHz crystal/ceramic oscillator External clock source Operation Voltage Range • 4.0 V to 5.5 V General I/O • Bit programmable five I/O ports (30 pins total) Package Types • • 64-pin SDIP 64-pin QFP 1-2 KS86C6308/P6308 (Preliminary Spec) PRODUCT OVERVIEW BLOCK DIAGRAM USB Transceiver & Voltage Regulator LPF 12 MHz XI OSC XO PLL 48 MHz USB Module DP0/GPIO, DM0/GPIO DP1, DM1 DP2, DM2 DP3, DM3 DP4, DM4 3.3 VOUT PWREN1 PWREN2 PWREN3 PWREN4 OCDET1 OCDET2 OCDET3 OCDET4 12 MHz SAM88RCRI CORE USB Device Control LVD VDD VSS VSS1 TEST RESET 8K ROM LEDON0 LEDON1 LEDON2 LEDON3 LEDON4 GANGED 8 B i t B U S Port P0.0/INT2 - P0.7/INT2 160 Byte RAM Port P1.0 - P1.7 TMOD Timer A (8 Bit) Port Timer B (16 Bit) Port Basic Timer P2.0/INT0 - P2.7/INT0 P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.1/TACAP/TBOUT P4.0/INT1 P4.1/INT1 Port Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW KS86C6308/P6308 (Preliminary Spec) PIN ASSIGNMENTS LEDON4 P1.4 P1.5 P1.6 P1.7 P4.0/INT1 P4.1/INT1 P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 SDAT /P2.6/INT0 SCLK /P2.7/INT0 VDD /VDD VSS /VSS XO /XO XI /XI TEST /TEST LPF VSS/VSSA RESET/RESET TMODE DP0/GPIO DM0/GPIO DP1 DM1 DP2 DM2 DP3 DM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LEDON3 LEDPN2 LEDON1 LEDON0 OCDET4 PWREN4 P1.3 P1.2 P1.1 P1.0 P0.7/INT2 P0.6/INT2 P0.5/INT2 P0.4/INT2 P0.3/INT2 P0.2/INT2 P0.1/INT2 P0.0/INT2 OCDET3 PWREN 3 Figure 1-2. Pin Assignment Diagram (64-Pin SDIP Package) KS86C6308/P6308 P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT VSS1/VSS OCDET2 PWREN2 ECDET1 PWREN1 3.3VOUT DM4 DP4 1-4 KS86C6308/P6308 (Preliminary Spec) PRODUCT OVERVIEW P41/INT1 P40/INT1 P17 P16 P15 P14 LEDON4 LEDON3 LEDON2 LEDON1 LEDON0 64 63 62 61 60 59 58 57 56 55 54 53 52 P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 SDAT /P2.6/INT0 SCLK /P2.7/INT0 VDD/VDD VSS/VSS XO /XO XI /XI TEST /TEST LPF VSS/VSSA RESET/RESET OCDET4 PWREN4 TMODE DP0/GPIO DM0/GPIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 KS86C6308 (KS86P6308) 51 50 43 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.3 P1.2 P1.1 P1.0 P0.7/INT2 P0.6/INT2 P0.5/INT2 P0.4/INT2 P0.3/INT2 P0.2/INT2 P0.1/INT2 P0.0/INT2 OCDET3 PWREN3 P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT GANGED DP1 DM1 DP2 DM2 DP3 DM3 DP4 DM4 3.3VOUT Figure 1-3. Pin Assignment Diagram (64-Pin QFP Package) PWREN1 OCDET1 PWREN2 OCDET2 20 21 22 23 24 25 26 27 28 29 30 31 32 1-5 PRODUCT OVERVIEW KS86C6308/P6308 (Preliminary Spec) PIN DESCRIPTIONS Table 1-1. KS86C6308/P6308 Pin Descriptions Pin Names P0.0-P0.7 I/O I/O Pin Description Bit-programmable I/O port for Schmitt trigger input or open-drain output. Port 0 can be individually configured as external interrupt inputs. Pull-up resistors are assignable by software. Bit-programmable I/O port for Schmitt trigger input or open-drain output. Pull-up resistors are assignable by software. Bit-programmable I/O port for Schmitt trigger input or open-drain output. Port 2 can also be individually configured as external interrupt inputs. Pull-up resistors are assignable by software. Bit-programmable I/O port for Schmitt trigger input, opendrain output or push-pull output. Port 3 are designed for to drive LED directly. P3.3 can be used to system clock output(CLO) pin. P3.2 PLL clock out for PLL Block. Bit-programmable I/O port for Schmitt trigger input or open-drain output or push-pull output. Port4 can also be individually configured as external interrupt inputs. In output mode, pull-up resistors are assignable by software. But in input mode, pull-up resistors are fixed. 3.3 V output from internal voltage regulator System clock input and output pin (crystal/ceramic oscillator, or external clock source) External interrupt for bit-programmable port0, port2 and port4 pins when set to input mode. RESET signal input pin with LVD Low Pass Filter Pin for PLL Test signal input pin (for factory use only; must be connected to VSS) Test signal input pin (for factory use only, must be connected to VSS) Power input pin VSS1 is a ground power for CPU core. VSS2 is a ground power for I/O and OSC block. Pin Type B Share Pins INT2 P1.0-P1.7 I/O B – P2.0-P2.7 I/O B INT0 P3.0-P3.3 I/O C P3.3/TACLK/CLO P3.2/TBCLK/ USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT INT1 P4.0-P4.1 I/O D 3.3 VOUT XIN XOUT INT0 INT1 INT2 RESET LPF TEST TMODE VDD VSS VSS1 – – I – – – – – P2.0-P2.7 P4.0/P4.1 P0.0/P0.7 – – – – – – I I I I – – A – – – – – 1-6 KS86C6308/P6308 (Preliminary Spec) PRODUCT OVERVIEW Table 1-1. KS86C6308/P6308 Pin Descriptions (Continued) Pin Names DP1, DM1 DP2, DM2 DP3, DM3 DP4, DM4 DP0/GPIO DM0/GPIO LEDON0 I/O I/O Pin Description These pins are an USB Downstream pins. Pin Type K Share Pins – I/O O LEDON1-4 O OCDET1-4 I PWREN1-4 O GANGED I These pins are an USB Upstream pin, programmable port for USB interface or General purpose I/O interface. Root port LED enable. N-channel open-drain output. = 0 Turn LED ON. HUB not Suspend = 1 Turn LED OFF. Reset, Suspend, Transfer in progress Four downstream port LED enable. N-channel opendrain output. = 0 Turn LED ON. Port Enable and HUB not Suspend = 1 Turn LED OFF. Reset, Suspend, Transfer in progress Four downstream power sense = 0 Over Current Detected = 1 Power Okay Power on/off control signals. PWREN1 - PWREN4 are active low, N-CH open-drain outputs. In GANGED mode, all output are swithed together. Gang or Individual Power Control of downstream ports = 0 Individual = 1 Gang – G – – G – F – G – F – 1-7 PRODUCT OVERVIEW KS86C6308/P6308 (Preliminary Spec) PIN CIRCUIT DIAGRAMS VDD VDD Pull-up Resistor Noise Filter Output Data Open Drain Output DIsable VSS Input Data D0 MUX D1 Figure 1-4. Pin Circuit Type A (RESET) Figure 1-6. Pin Circuit Type C (Port 3) VDD VDD Pull-up Resistor Pull-up Enable Output Data Output Disable Open Data Open Drain Output DIsable VSS Pull-up Enable VDD Pull-up Resistor Input Data D0 MUX D1 VSS Input Data D0 MUX D1 Figure 1-5. Pin Circuit Type B (Port 0, 1, 2) Figure 1-7. Pin Circuit Type D (Port 4) 1-8 KS86C6308/P6308 (Preliminary Spec) PRODUCT OVERVIEW VDD Pull-up Resistor Figure 1-8. Pin Circuit Type F 3.0 V < V