KS88P8324

KS88C8316/C8324/P8324 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM87 PRODUCT FAMILY Samsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Release by interrupt of Idle and Stop power-down modes — Built-in basic timer circuit with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. KS88C8316/C8324/P8324 The KS88C8316 microcontroller has 16 K bytes of on-chip program memory and the KS88C8324 has 24 K bytes. Both chips have a 272-byte general-purpose internal register file. The interrupt structure has seven interrupt sources with six interrupt vectors. The CPU recognizes six interrupt priority levels. Using a modular design approach, the following peripherals were integrated with the SAM87 core to make the KS88C8316/C8324/P8324 suitable for use in color television and other types of screen display applications: — Four programmable I/O ports (26 pins total: 16 general-purpose I/O pins; 8 n-channel, open-drain output pins) — 2 channel A/D converter (4-bit resolution) — 14-bit PWM output (one channels: push-pull type) — Basic timer (BT) with watchdog timer function — One 8-bit timer/counter (T0) with interval timer — One 8-bit general-purpose timer/counter (TA) with prescalers — On-screen display (OSD) with a wide range of programmable features including halftone control signal output The KS88C8316/C8324 are available in a versatile 42-pin SDIP package. OTP The KS88C8316/C8324 microcontroller is also available in OTP (One Time Programmable) version, KS88P8324. KS88P8324 microcontroller has an on-chip 24K-byte one-time-programmable EPROM instead of masked ROM. The KS88P8324 is comparable to KS88C8316/C8324, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW KS88C8316/C8324/P8324 FEATURES CPU • SAM87 CPU core Pulse Width Modulation Module • • • 14-bit PWM with one-channel output (push-pull type) PWM counter and data capture input pin Frequency: 5.859 kHz to 23.437 kHz with a 6-MHz CPU clock Memory • • 16-K byte (KS88C8316) or 24-K byte (KS88C8324) internal program memory 272-byte general-purpose register area On-Screen Display (OSD) Instruction Set • • 78 instructions IDLE and STOP instructions added for powerdown modes • • • • • • Interrupts • • • 7 interrupt sources with 6 vectors 6 interrupt levels Fast interrupt processing for select levels • General I/O • • • Four I/O ports (26 pins total) Six open-drain pins for up to 6-volt loads Two open-drain pins for up to 5-volt loads • • • Video RAM: 252 × 12 bits Character generator ROM: 256 × 18 × 16 bits (256 display characters: fixed: 2, variable: 254) 252 display positions (12 rows × 21 columns) 16-dot × 18-dot character resolution 16 different character sizes Eight character colors Vertical direction fade-in/fade-out control Eight colors for character and frame background Halftone control signal output; selectable for individual characters Synchronous polarity selector for H-sync and V-sync input Instruction Execution Time • 750 ns (minimum) with an 8-MHz CPU clock Oscillator Frequency • • 5-MHz to 8-MHz external crystal oscillator Maximum 8-MHz CPU clock 8-Bit Basic Timer • • Three selectable internal clock frequencies Watchdog or oscillation stabilization function Operating Temperature Range • – 20°C to + 85°C Timer/Counters • • One 8-bit timer/counter (T0) with three internal clocks and interval timer mode. One general-purpose 8-bit timer/counters with interval timer mode (timer A) Operating Voltage Range • 4.5 V to 5.5 V Package Type • 42-pin SDIP A/D Converter • • Two analog input pins; 4-bit resolution 3.125 µs conversion time (8-MHz CPU clock) 1-2 KS88C8316/C8324/P8324 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0 - P0.7 P1.0 - P1.7 RESET PORT 0 INT0 - INT1 PORT 1 TEST XIN XOUT MAIN OSC SAM87 BUS TIMER A PORT I/O and INTERRUPT CONTROL OSC IN OSC OUT H-sync V-sync Vred Vgreen Vblue Vblank OSDHT L-C OSC TIMER 0 ONSCREEN DISPLAY SAM87 CPU PWM BLOCK PWM COUNTER and DATA CAPTURE CAPA ADC0 ADC1 16-KB ROM (8316) 4-BIT ADC 24-KB ROM (8324) 272-BYTE REGISTER FILE 14-BIT PWM SAM87 BUS PWM0 PORT 2 PORT 3 P2.0 - P2.7 P3.0 - P3.1 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW KS88C8316/C8324/P8324 PIN ASSIGNMENTS P2.5/PWM0 P2.1 P2.2(SCL ) P2.3(SDA) P2.4 P2.0 P2.6 P1.7 P3.0/ADC0 P3.1/ADC1 P0.6 P0.7 TEST P1.0/INT0 P1.1/INT1 P1.2 P1.3 P1.4 P1.5 P1.6 P2.7/OSDHT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 KS88C8316/ 33 C8324/P8324 32 42-PIN SDIP 31 (Top View) 30 29 28 27 26 25 24 23 22 P0.0 P0.1 P0.2 P0.3 P0.4 VSS2 CAPA P0.5 VDD RESET XOUT XIN VSS1 OSCOUT OSCIN V-sync H-sync Vblank Vred Vgreen Vblue Figure 1-2. KS88C8316/C8324/P8324 Pin Assignment Diagram 1-4 KS88C8316/C8324/P8324 PRODUCT OVERVIEW Table 1-1. KS88C8316/C8324 Pin Descriptions Pin Name P0.0–P0.7 P1.0–P1.1 Pin Type I/O I/O Pin Description General I/O port (8-bit), configurable for digital input or push-pull output. General I/O port (2-bit), configurable for digital input or n-channel open-drain output. P1.0–P1.1 can withstand up to 6-volt loads. Multiplexed for alternative use as external interrupt inputs INT0–INT1. General I/O port (4-bit), configurable for digital input or n-channel open-drain output. P1.2–P1.5 can withstand up to 6-volt loads. High current port (10mA). General I/O port (2-bit), configurable for digital input or push-pull output. I/O General I/O port (6-bit). I/O mode or n-channel open-drain, push-pull output mode is software configurable. Pins can withstand up to 5-volt loads. P2.2: OTP serial clock pin P2.3: OTP serial data pin General I/O port (2-bit). I/O mode or n-channel open-drain, push-pull output mode is software configurable. Pins can withstand up to 5-volt loads. Each pin has an alternative function. P2.5: PWM0 (14-bit PWM output) P2.7: OSDHT (Halftone signal output) Circuit Type 3 7 Pin Numbers 11–12, 35, 38–42 14–15 INT0–INT1 Share Pins P1.2–P1.5 5 16–19 P1.6–P1.7 P2.0–P2.4, P2.6 3 2 20, 8 2–7 P2.5, P2.7 2 1, 21 PWM0 OSDHT 1-5 PRODUCT OVERVIEW KS88C8316/C8324/P8324 Table 1-1. KS88C8316/C8324 Pin Descriptions (Continued) Pin Name P3.0–P3.1 Pin Type I/O Pin Description General I/O port (2 bits), configurable for digital input or n-channel open-drain output. P3.0–P3.1 can withstand up to 5-volt loads. Multiplexed for alternative use as external interrupt inputs ADC0–ADC1. Output pin for 14-bit PWM0 circuit Analog inputs for 4-bit A/D converter External interrupt input pins Halftone control signal output for OSD Digital blue, green, red, and video blank signal outputs for OSD H-sync input for OSD V-sync input for OSD I, O I L-C oscillator pins for OSD clock frequency generation 0 V: Normal operation mode 5 V: Factory test mode 12.5 V: OTP write mode System clock pins System reset input pin Power supply pins Input for capture A module – – Circuit Type 6 Pin Numbers 9–10 Share Pins ADC0 ADC1 PWM0 ADC0–ADC1 INT0–INT1 OSDHT Vblue, Vgreen Vred, Vblank H-sync V-sync OSCIN, OSCOUT TEST O I I O O I 2 6 7 2 4 8 1 9,10 14,15 21 22–25 26 27 28,29 13 P2.5 P3.0– P3.1 P1.0– P1.1 P2.7 – – – – XIN, XOUT RESET I, O I – I – 1 – 8 31, 32 33 13 26 – – – – VDD, VSS1, VSS2 CAPA 1-6 KS88C8316/C8324/P8324 PRODUCT OVERVIEW PIN CIRCUITS VDD V DD DATA I/O 200 KΩ IN NOISE FILTER INPUT VSS INPUT Figure 1-3. Pin Circuit Type 1 (RESET) Figure 1-5. Pin Circuit Type 3 (P0.0–P0.7, P1.6–P1.7) VDD DATA I/O OPENDRAIN OUTPUT DISABLE DATA I/O VDD VSS VSS INPUT Figure 1-4. Pin Circuit Type 2 (P2.0–P2.7, PWM0, OSDHT) Figure 1-6. Pin Circuit Type 4 (Vblue, Vgreen, Vred, Vblank) 1-7 PRODUCT OVERVIEW KS88C8316/C8324/P8324 I/O I/O DATA DATA VSS VSS INPUT INPUT INT NOISE FILTER NOTE: Circuit type 5 can withstand up to 6-volt loads. NOTE: Circuit type 7 can withstand up to 6-volt loads. Figure 1-7. Pin Circuit Type 5 (P1.2–P1.5) Figure 1-9. Pin Circuit Type 7 (P1.0–P1.1, INT0–INT1) I/O DATA VSS INPUT A/D IN INPUT NOISE FILTER IN NOTE: Circuit type 6 can withstand up to 5-volt loads. Figure 1-8. Pin Circuit Type 6 (P3.0–P3.1, ADC0–ADC1) Figure 1-10. Pin Circuit Type 8 (V-Sync H-Sync, CAPA) 1-8 KS88C8316/C8324/P8324 ELECTRICAL DATA 15 OVERVIEW — I/O capacitance ELECTRICAL DATA In this section, KS88C8316/C8324 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Input timing measurement points for tNF1 and tNF2 — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by RESET — Main oscillator and L-C oscillator frequency — Clock timing measurement points for XIN — Main oscillator clock stabilization time (tST) — A/D converter electrical characteristics — Characteristic curves 15-1 ELECTRICAL DATA KS88C8316/C8324/P8324 Table 15-1. Absolute Maximum Ratings (TA = 25°C) Parameter Supply Voltage Input Voltage Symbol VDD VI1 VI2 Output Voltage Output Current High Output Current Low VO I OH Conditions – P1.0–P1.5 (open-drain) All port pins except VI1 All output pins One I/O pin active All I/O pins active I OL One I/O pin active Total pin current for port 1 Total pin current for ports 0, 2, and 3 Operating Temperature Storage Temperature TA TSTG – – Rating – 0.3 to + 6.0 – 0.3 to + 7 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 18 – 60 + 30 + 100 + 100 – 20 to + 85 – 65 to + 150 °C °C Unit V V V mA mA Table 15-2. D.C. Electrical Characteristics (TA = – 20°C to + 85°C, VDD = 4.5 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 Input Low Voltage VIL1 VIL2 Output High Voltage Output Low Voltage VOH Conditions All input pins except VIH2 XIN, XOUT Min 0.8 VDD 2.7 V – Typ – Max VDD Unit V All input pins except VIL2 XIN, XOUT IOH = – 500 µA P0, P1.6–P1.7, P2 R, G, B, Vblank IOL = 4 mA P0, P1.6–P1.7 IOL = 10 mA P1.2–P1.5 IOL = 2 mA P1.0–P1.1, P3.0–P3.1 IOL = 1 mA R, G, B, Vblank, P2 – 0.2 VDD 1.0 V V VDD – 0.8 – – V VOL1 VOL2 VOL3 VOL4 – – – – – – – – 0.4 0.8 0.4 0.4 V V 15-2 KS88C8316/C8324/P8324 ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (Continued) (TA = – 20°C to + 85°C, VDD = 4.5 V to 5.5 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VIN = VDD All input pins except ILIH2 and ILIH3 VIN = VDD, OSCIN, OSCOUT VIN = VDD, XIN, XOUT VIN = 0 V All input pins except ILIL2, ILIL3, and RESET VIN = 0 V, OSCIN, OSCOUT VIN = 0 V, XIN, XOUT VOUT = VDD All output pins except ILOH2 VOUT = 6 V P1.0–P1.5 VOUT = 0 V All output pins Normal mode; VDD = 4.5 V to 5.5 V 8-MHz CPU clock Idle mode; VDD = 4.5 V to 5.5 V 8-MHz CPU clock Stop mode; VDD = 4.5 V to 5.5 V – – – 7 – 2.5 – – 10 – 2.5 – 10 – Min – Typ – Max 3 Unit µA ILIH2 ILIH3 Input Low Leakage Current ILIL1 10 20 –3 µA ILIL2 ILIL3 Output High Leakage Current ILOH1 ILOH2 Output Low Leakage Current Supply Current (note) – 10 – 20 3 10 –3 20 µA mA µA ILOL IDD1 IDD2 2 10 IDD3 1 10 µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. 15-3 ELECTRICAL DATA KS88C8316/C8324/P8324 Table 15-3. Input/Output Capacitance (TA = – 20°C to + 85°C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min – Typ – Max 10 Unit pF Table 15-4. A.C. Electrical Characteristics (TA = – 20°C to + 85°C, VDD = 4.5 V to 5.5 V) Parameter V-sync Pulse Width H-sync Pulse Width Noise Filter Symbol tVW tHW tNF1 tNF2 tNF3 tNF4 tNF5 NOTE: tCAPA = fOSC/128. Conditions – – P1.0–P1.1, V-sync RESET Min 4 3 – – – – – Typ – – 350 1000 15 5 650 Max – – – Unit µs µs ns Glitch filter (oscillator block) CAPA H-sync – – tCAPA ns 1tCPU tNF1L t NF2 tNF1H 0.8 VDD 0.2 VDD Figure 15-1. Input Timing Measurement Points for tNF1 and tNF2 15-4 KS88C8316/C8324/P8324 ELECTRICAL DATA Table 15-5. Data Retention Supply Voltage in Stop Mode (TA = – 20 °C to + 85 °C) Parameter Data Retention Supply Voltage Data Retention Supply Current Symbol VDDDR IDDDR Conditions Stop mode Stop mode, VDDDR = 2.0 V Min 2 – Typ – – Max 6 5 Unit V µA NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped. t SREL OSCILLATION STABILIZATION TIME NORMAL OPERATING MODE ~ ~ ~ ~ STOP MODE DATA RETENTION MODE VDD VDDDR EXECUTION OF STOP INSTRUCTION RESET NOTE: t WAIT is the same as 4096 x 16 x 1 / fOSC t WAIT Figure 15-2. Stop Mode Release Timing When Initiated by a Reset 15-5 ELECTRICAL DATA KS88C8316/C8324/P8324 Table 15-6. Main Oscillator and L-C Oscillator Frequency (TA = – 20°C to + 85°C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Clock Circuit C1 Conditions OSD block active Min 5 Typ 6 Max 8 Unit MHz XIN XOUT C2 OSD block inactive Ceramic C1 0.5 5 6 6 8 8 MHz XIN XOUT C2 OSD block active OSD block inactive External Clock XIN XOUT 0.5 5 6 6 8 8 MHz OSD block active OSD block inactive L-C Oscillator C1 0.5 5 6 6.5 8 8 MHz OSCIN OSCOUT C2 Recommend value: C1 = C2 = 20 pF CPU Clock Frequency – 0.032 6.0 8 MHz 1 / fOSC tXL tXH XIN 2.7 V 1.0 V Figure 15-3. Clock Timing Measurement Points for XIN 15-6 KS88C8316/C8324/P8324 ELECTRICAL DATA Table 15-7. Main Oscillator Clock Stabilization Time (TA = – 20°C to + 85°C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Ceramic Symbol – Test Condition VDD = 4.5 V to 6.0 V (Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range.) XIN input High and Low level width (tXH, tXL) tSREL tWAIT Normal operation CPU clock = 8 MHz; Stop mode released by RESET CPU clock = 8 MHz; Stop mode released by an interrupt 65 – – – 1000 8.3 Min – Typ – Max 20 10 Unit ms External Clock Release Signal Setup Time Oscillation Stabilization Wait Time (1) 100 – – ns ns ms (2) NOTES: 1. Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is released. 2. The oscillation stabilization interval is determined by the basic timer (BT) input clock setting. Table 15-8. A/D Converter Electrical Characteristics (TA = – 20°C to + 85°C, VDD = 4.5 V to 5.5 V, VSS = 0 V) Parameter Absolute Accuracy (1) Conversion Time (2) Analog Input Voltage Analog Input Impedance Symbol – tCON VIAN RAN – – Conditions CPU clock = 8 MHz Min – tCPU × 25 (3) Typ – – – Max ± 0.5 Unit LSB µs VSS 2 VDD – V MΩ NOTES: 1. Excluding quantization error, absolute accuracy values are within ± 1/2 LSB. 2. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 3. The unit tCPU means one CPU clock period. 15-7 KS88C8316/C8324/P8324 MECHANICAL DATA 16 OVERVIEW 42 14.00 ± 0.2 MECHANICAL DATA The KS88C8316/C8324 microcontrollers are available in a 42-pin SIP package (42-SDIP-600). 22 0 ~ 15 ° 42-SDIP-600 #1 21 0.25 +0.1 – 0.0 5 3.50 ± 0.2 (1.77) 0.50 ± 0.1 1.00 ± 0.1 1.778 NOTE: Package dimensions are in millimeters. Figure 16-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600) 3.30 ± 0.3 0.51MIN 5.08MAX 39.10 ± 0.2 15.24 16-1 KS88C8316/C8324/P8324 KS88P8324 OTP 17 OVERVIEW KS88P8324 OTP The KS88P8324 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS88C8316/C8324 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS88P8324 is fully compatible with the KS88C8316/C8324, both in function and in pin configuration. Because of its simple programming requirements, the KS88P8324 is ideal for use as an evaluation chip for the KS88C8316/C8324. 17-1 KS88P8324 OTP KS88C8316/C8324/P8324 P2.5/PWM0 P2.1 SCLK/ P2.2 SDAT/ P2.3 P2.4 P2.0 P2.6 P1.7 P3.0/ADC0 P3.1/ADC1 P0.6 P0.7 TEST/TEST P1.0/INT0 P1.1/INT1 P1.2 P1.3 P1.4 P1.5 P1.6 P2.7/OSDHT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 KS88P8324 42-PIN SDIP (Top View) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P0.0 P0.1 P0.2 P0.3 P0.4 VSS2/ VSS CAPA P0.5 VDD / VDD RESET/ RESET XOUT XIN VSS1/ VSS OSC OUT OSC IN V-sync H-sync Vblank Vred Vgreen Vblue NOTE: The bolds indicate an OTP pin name. Figure 17-1. KS88P8324 Pin Assignments (42-SDIP) 17-2 KS88C8316/C8324/P8324 KS88P8324 OTP Table 17-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P2.3 (Pin 4) Pin Name SDAT Pin No. 4 During Programming I/O I/O Function Serial data Pin (Output when reading, Input when writing) Input and Push-pull Output Port can be assigned Serial clock Pin (Input Only Pin) 0 V: Operating mode 5 V: Test mode 12.5 V: OTP mode 0 V: Chip initialization, OTP mode 5 V: Operating mode Logic Power Supply Pin. P2.2 (Pin 3) TEST SCLK VPP (TEST) 3 13 I/O I RESET RESET 33 34/30, 37 I I VDD/VSS VDD/VSS Table 17-2. Comparison of KS88P8324 and KS88C8316/C8324 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS88P8324 24 K byte EPROM 4.5 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 42 SDIP User Program 1 time 42 SDIP Programmed at the factory KS88C8316/C8324 24 K byte mask ROM 4.5 V to 5.5 V – 17-3