KS9286

KS9286B/KS9286B-L DIGITAL SIGNAL PROCESSOR DIGITAL SIGNAL PROCESSOR for CDP 80-QFP-1420C The KS9286B is a CMOS integrated circuit designed for the Digital Audio Signal Processor for Compact Disc Player. It is a monolithic IC that builts-in 16-bit Digital Analog Convertor, ESP Interface and Digital De-emphasis additional conventional DSP function. FEATURES • • • • • • • • • • • • • • • • EFM data demodulation Frame sync detection/protection/insertion Powerful error correction (C1: 2error, C2: 4erasure) Interpolation 8fs digital filter (51th+13th+9th) Subcode data serial output CLV servo controller Micom interface Digital audio output Digital de-emphasis ESP interface Built-in 16K SRAM Built-in Digital PLL Double speed play available Built-in 16-bit D/A converter Operating Voltage range KS9286B : 5V KS9286B-L : 3.4V ORDERING INFORMATION Device KS9286B KS9286B-L Package 80-QFP-1420C Tempe. Range -20oC ~ +75oC 1 KS9286B/KS9286B-L BLOCK DIAGRAM S 0 S1 SUBCODE SYNC DETECTOR 26 DIGITAL SIGNAL PROCESSOR for CDP SUBCODE OUTPUT S B CK 32 S DA T 33 SUBCODE-Q REG ISTER 30 29 SQDT SQCK EFMI 66 EFM PHASE DETECTOR 23BI T SHIFT REG ISTER EFM DEMODULATOR CNTVOL DPFIN DPFOUT DPDO SMEF SMON SMDP SMDS LOCK XOUT XIN 5 3 4 2 72 73 75 76 70 9 8 8 BIT D ATA BUS DIG I TAL PLL FRAME SYNC DETECTOR PROTECTOR INSERTOR ADDRESS GENERATOR 16K SRAM CLV SERVO ECC X-TAL TIMING GENERATOR INTERPO LATOR MDAT MCK MLT TRCNT /ISTAT 37 38 36 69 68 CPU INTERFACE TRACK COUNTER DIG I TAL FILTER & DE-EMPH LRCHO ADATAO BCKO BCKI 77 67 ADATAI LRCHI 80 24 EMPH 11 12 14 17 22 MODE SELECTOR DIG I TAL OUTPUT D/A CONVERTER VREFL1 VREFH1 20 19 61 62 63 65 7 CDROM TE S T0 X TA L S E L TE S T1 DA TX RCHOUT L CHOUT 2 KS9286B/KS9286B-L PIN CONFIGURATION DIGITAL SIGNAL PROCESSOR for CDP B CK I 77 TE S TV 78 DS P EE D 79 LRCHI 80 A DA TA I 67 / I S TA T 6 8 TRCNT 69 L OCK 70 P B FR 71 DV DD2 TE S T1 SMON 73 74 S MDP S MDS 75 76 S MEF 72 E FMI 66 65 64 SRAM 63 CDROM 62 FOK 61 XTALSEL 60 /CS 59 /WE 58 C16M 57 C4M 56 /JIT AVDDI DPDO DPFIN DPFOUT CNTVOL AVSS1 DATX XIN XOUT WDCHO LRCHO ADATAO DVSS1 BCKO C2PO VREFL2 VREFL1 AVDD2 RCHOUT LCHOUT AVSS2 VREFH1 VREFH2 EMPH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 KS9286B 55 ULKFS 54 FSDW 53 DVSS2 52 /PBCK 51 FLAG5 50 FLAG4 49 FLAG3 48 FLAG2 47 FLAG1 46 RD0 45 RD1 44 RD2 43 RD3 42 RD4 41 RD5 27 26 25 L K FS RE S E T S0 S1 29 28 / E SP S QCK 32 31 30 S QOK S QDT S B CK 33 S DA T 35 34 MUTE DV DD1 38 37 36 ML T MDA T 39 40 RD6 RD7 MCK 3 KS9286B/KS9286B-L PIN DESCRIPTION DIGITAL SIGNAL PROCESSOR for CDP PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SYMBOL AVDD1 DPDO DPFIN DPFOUT CNTVOL AVSS1 DATX XIN XOUT WDCHO LRCHO ADATAO DVSS1 BCKO C2PO VREFL2 VREFL1 AVDD2 RCHOUT LCHOUT AVSS2 VREFH1 VREFH2 EMPH LKFS S0S1 RESET /ESP SQCK IO O I O I O I O O O O O O I I O O I I O O O I I I Analog VCC1 DESCRIPTION Charge pump output for Digital PLL Filter input for Digital PLL Filter output for Digital PLL VCO control voltage for Digital PLL Analog Ground1 Digital Audio output data X'tal oscillator input X'tal oscillator output Word clock output of 48bit/Slot (88.2KHz) Channel clock output of 48 bit/Slot (44.1KHz) Serial audio data output of 48 bit/Slot (MSB first) Digital Ground1 Audio data bit clock output of 48 bit/Slot (2.1168MHz) C2 Pointer for output audio data Input terminal2 of reference voltage "L" (Floating) Input terminal1 of reference voltage "L" (GND connection) Analog VCC2 Right-Channel audio output through D/A converter Left-Channel audio output through D/A converter Analog ground2 Input terminal1 of reference voltage "H" (VDD connection) Input terminal2 of reference voltage "H" (Floating) H: Emphasis ON, L: Emphasis OFF The Lock Status output of frame sync Output of subcode sync signal(S0+S1) System reset at "L" ESP function ON/OFF control ("L": ESP function ON, "H": ESP function OFF) Clock for output Subcode-Q data 4 KS9286B/KS9286B-L PIN DESCRIPTION (continued) DIGITAL SIGNAL PROCESSOR for CDP PIN NO 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 SYMBOL SQDT SQOK SBCK SDAT DVDD1 MUTE MLT MDAT MCK RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 /PBCK DVSS2 FSDW ULKFS /JIT C4M C16M /WE /CS IO O O I O I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Serial output of Subcode-Q data DESCRIPTION The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q Clock for output subcode data Subcode serial data output Digital VDD1 Mute control input ("H": Mute ON) Latch Signal Input from Micom (Schmit Trigger) Serial data input from Micom (Schmit Trigger) Serial clock input from Micom (Schmit Trigger) SRAM data I/O port 8 (MSB) SRAM data I/O port 7 SRAM data I/O port 6 SRAM data I/O port 5 SRAM data I/O port 4 SRAM data I/O port 3 SRAM data I/O port 2 SRAM data I/O port 1 (LSB) Monitoring output for error correction (RA0) Monitoring output for error correction (RA1) Monitoring output for error correction (RA2) Monitoring output for error correction (RA3) Monitoring output for error correction (RA4) Output of VCO/2 (4.3218MHz) (RA5) Digital ground 2 Window or unprotected frame sync (RA6) Frame sync protection state (RA7) Display of either RAM overflow or underflow for + 4 frame jitter margin (RA8) Only monitoring signal (4.2336MHz) (RA9) 16.9344MHz signal output(RA10) Terminal for test Terminal for test 5 KS9286B/KS9286B-L PIN DESCRIPTION (continued) PIN NO 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DIGITAL SIGNAL PROCESSOR for CDP SYMBOL XTALSEL FOK CDROM SRAM TEST1 EFMI ADATAI /ISTAT TRCNT LOCK PBFR SMEF SMON DVDD2 SMDP SMDS BCKI TESTV DSPEED LRCHI IO I I I I I I I O I O O O O O O I I I I DESCRIPTION Mode Selection1 (H: 33.8688MHz, L: 16.9344MHz) SERVO FOK Signal input terminal Mode Selection2 (H: CD-ROM, L: CDP) TEST input terminal (GND connection) TEST input terminal (GND connection) EFM signal input Serial audio data input of 48 bit/Slot (MSB first) The internal status output Tracking counter input signal Output signal of LKFS condition sampled PBFR/16 (if LKFS is "H", LOCK is "H", if LKFS is sampled "L" at least 8 times by PBFR/16, LOCK is "L".) Write frame clock (Lock: 7.35KHz) LPF time constant control of the spindle servo error signal ON/OFF control signal for spindle servo Digital VDD2 Spindle Motor drive (Rough control in the SPEED mode, Phase control in the PHASE mode) Spindle Motor drive (Velocity control in the PHASE mode) Audio data bit clock input of 48 bit/Slot (2.1168MHz) TEST input terminal (GND connection) TEST input terminal (VDD connection) Channel clock input of 48 bit/Slot (44.1KHz) 6 KS9286B/KS9286B-L ABSOLUTE MAXIMUM RATINGS Characteristic Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Symbol VDD VI VO TOPR TSTG DIGITAL SIGNAL PROCESSOR for CDP Value -0.3 ~ 7.0 -0.3 ~ 7.0 -0.3 ~ 7.0 -20 ~ 75 -40 ~ 125 Unit V V V o o C C ELECTRICAL CHARACTERISTIC 1. DC Characteristic (Vcc=5V, Vss=0V, Ta=25oC, unless otherwise specified) Characteristic 'H' INPUT VOLTAGE1 'L' INPUT VOLTAGE1 'H' INPUT VOLTAGE2 'L' INPUT VOLTAGE2 'H' OUTPUT VOLTAGE1 'L' OUTPUT VOLTAGE1 'H' OUTPUT VOLTAGE2 'L' OUTPUT VOLTAGE2 INPUT LEAK CURRENT THREE STATE OUTPUT LEAK CURRENT Symbol VIH(1) VIL(1) VIH(2) VIL(2) VOH(1) VOL(1) VOH(2) VOL(2) ILKG IO(LKG) Test Conditions (Note1) (Note1) (Note2) (Note2) IOH=-1mA (Note3) IOL=1mA (Note3) IOH=-1mA (Note4) IOL=2mA (Note4) VI=0~VDD (Note5) VO=0~VDD (Note6) Min 0.7VDD 0.8VDD VDD-0.5 0 VDD-0.5 0 -5 -5 Typ - Max 0.3VDD 0.2VDD VDD 0.4 VDD 0.4 5 5 Unit V V V V V V V V uA uA (Note1) Related pins : XTALSEL, TEST0, CDROM, SRAM, TEST1, EFMI, ADATAI, BCKI, DSPEED & LRCHI (Note2) Related pins : All bi-direction pins & RESET, MLT, MCK, MDAT, MUTE, TRCNT (Note3) Related pins : All output pins except (Note4) and OSCILATOR, DPFOUT (Note4) Related pins : /ISTAT (Note5) Related pins : XIN (Note6) Related pins : SMEF, SMDP, SMDS & DPDO 7 KS9286B/KS9286B-L 2. AC CHARACTERISTIC A. XIN (When the pulse is input) (Vcc=5V, Vss=0V, Ta=25oC, unless otherwise specified) DIGITAL SIGNAL PROCESSOR for CDP Characteristic 'H' LEVEL PULSE WIDTH 'L' LEVEL PULSE WIDTH PULSE FREQUENCY INPUT 'H' LEVEL INPUT 'L' LEVEL RISING & FALLING TIME Symbol TWH TWL TCK VIH VIL TR,TF Min 13 13 26 VDD-1.0 - Typ - Max 0.8 8 UNIT ns ns ns V V ns TCK TWH TWL VIH VIHx0.9 VDD/2 VIL*0.1 VIL TF TR 8 KS9286B/KS9286B-L B. MCK, MDAT, MLT & TRCNT (Vcc=5V, Vss=0V, Ta=25oC, unless otherwise specified) DIGITAL SIGNAL PROCESSOR for CDP Characteristic CLOCK FREQUENCY CLOCK PULE WIDTH SETUP TIME HOLD TIME DELAY TIME LATCH PULSE WIDTH TRCNT, SQCK FREQUENCY TRCNT, SQCK PULSE WIDTH Symbol FCK1 TW TSU TH TD TWCK1 FCK2 TWCK2 Min 300 300 300 300 300 300 Typ - Max 1 1 - Unit MHz ns ns ns ns ns MHz ns 1/FCK1 TWCK1 TWCK1 MCK MDAT MLT TSU TH TD TW TRCNT SQCK TWCK2 1/FCK2 TWCK2 SQDAT TSU TH 9 KS9286B/KS9286B-L FUNCTION DESCRIPTION 1. Micom Interface DIGITAL SIGNAL PROCESSOR for CDP The data inputted from Micom is inputted to MDAT and transfered by MCK, and the inputted signal is loaded to control register by means of MLT. The timing chart is as follows. MDAT D0 D1 D2 D3 D4 D5 D6 D7 MCK MLT Register (9X ~ FX) Valid MDAT D0 D1 D2 D3 D4 ¡ó ¡ó D11 D12 D13 D14 D15 MCK MLT Register (88XX, 8DXX) Valid Fig.1. Micom data input timing chart CONTROL REGSTER CNTL-Z CNTL-S CNTL-L CNTL-U CNTL-W CNTL-C CNTL-D DATA CONTROL FRAME SYNC PROTECTION ATTENUATION CONTROL TRACKING COUNTER LOWER 4 BITS TRACKING COUNTER UPPER 4 BITS CLV CONTROL CLV-MODE DOUBLE-SPEED ADDRESS D7~D4 9X AX BX CX DX EX FX D3 ZCMT FSEM TRC3 TRC7 CM3 0 D2 FSEL TRC2 TRC6 WB CM2 0 DATA D1 NCLV WSEL TRC1 TRC5 WP CM1 DS1 D0 CRCQ ATTM TRC0 TRC4 GAIN CM0 DS2 /ISTAT PIN S0S1 LKFS /COMPLETE /COUNT FOK /(Pw > 64) TRCNT COMMENT CONTROL REGSTER CNTL-F CNTL-H COMMENT FUNCTION CONTROL ESP,MONITOR PIN CONTROL ADDRESS D15~D8 88XX 8DXX D7 D6 D5 DEEM DATA D4 ERA_ OFF /ISTAT D3 D2 D1 ESP_ ON D0 - PIN Hi-Z Hi-Z - - DUMB Table 1. Control register & data * Send the 9X, AX, DX, FX command when output the S0S1, LKFS, FOK, TRCNT signal to /ISTAT pin also just send MDAT, MCK except MLT 10 KS9286B/KS9286B-L 1) CNTL-Z REGISTER DIGITAL SIGNAL PROCESSOR for CDP It is a register to control zero cross mute of audio data, phase terminal control, phase servo control and having or not of CRCF in data SQDT. DATA = 0 ZCMT NCLV CRCQ D3 D2 D1 D0 Zero cross mute is OFF The phase servo is acted by frame sync SQDT outputs except for SQOK DATA = 1 Zero cross mute is ON The phase servo is controlled by base counter SQDT=CRCF when S0S1='H' Table 2. CNTL-Z register & data 2) CNTL-S REGISTER It is a register to control frame sync protection and attenuation. FSEM 0 0 1 1 FSEL 0 1 0 1 FRAME 2 4 8 13 WSEL 0 1 CLOCK +3 +7 ATTM 0 0 1 1 MUTE 0 1 0 1 dB 0 - -12 -12 Table 3. CNTL-S register & data 3) CNTL-L, U REGISTER After the counter of track that must be counted is inputted from Micom, the data is loaded to tracking counter by CNTL-L, U register. 8 11 KS9286B/KS9286B-L 4) CNTL-W REGISTER It is a register to control CLV-Servo. DATA=0 WB WP GAIN D3 D2 D1 D0 XTFR/32 XTFR/4 -12dB DATA=1 XTFR/16 XTFR/2 0dB - DIGITAL SIGNAL PROCESSOR for CDP COMMENT Bottom hold period control during speed or Hspeed-mode Peak hold period control during speed-mode SMDP gain control during speed or Hspeed-mode Table 4. CNTL-W register & data 5) CNTL-C REGISTER It is a register to control CLV-Mode. MODE FORWARD REVERSE SPEED HSPEED PHASE XPHSP VPHSP STOP 1110 D7~D4 D3~D0 1000 1010 1110 1100 1111 0110 0101 0000 SMDP H L SPEED-MODE HSPEED-MODE PHASE-MODE SPEED or PHASEMODE SPEED or PHASEMODE L SMSD Hi-Z Hi-Z Hi-Z Hi-Z PHASE-MODE Hi-Z or PHASE-MODE Hi-Z or PHASE-MODE Hi-Z SMEF L L L L Hi-Z L, Hi-Z L, Hi-Z L SMON H H H H H H H lL Table 5. CNTL-C register & data 6) CNTL-D REGISTER It is a register to control normal speed mode and double speed mode. MODE NORMAL 1111 DOUBLE 0011 Double Speed D7~D4 D3~D0 0000 COMMENT Normal Speed Table 6. CNTL-D register & data 12 KS9286B/KS9286B-L DIGITAL SIGNAL PROCESSOR for CDP 7) CNTL-F REGISTER It is a register to control De-emphasis and ECC Erasure correction. DATA = 0 DEEM ERA_OFF D5 D4 Internal De-emphasis Filter operation OFF ECC Erasure correction ON DATA = 1 Internal De-emphasis Filter operation ON ECC Erasure correction OFF Table 6. CNTL-F register & data 8) CNTL-H RESISTER It isa resister to control ESP interface and Monitor pin DATA = 0 ESP_ON DUMB D1 D0 ESP Interface Disable Monitor Pin Output Enable DATA = 1 ESP Interface Enable Monitor Pin Output Disable Note) Monitor pin : FLAG1 ~ FLAG5, /PBCK, FSDW, ULKFS, C16M, PBFR Table 7. CNTL-H register & data 2. Tracking Counter Block This block is used to improve the Track-jump characteristics. The numbers of tracks that are to be jumped (inputted from Micom) are loaded into either register CNTL-L or CNTL-U at the rising edge of MLT. When the address is set in CNTL-L, the signal /COMPLETE is output in /ISTAT Pin, and when the address is set in CNTL-U, the signal /COUNT is output. The following is timing chart of tracking counter block. MLT CNTL-L,U TRCNT /ISTAT =(/count) /ISTAT =(/complete) N N N N N N Fig.2. Tracking counter timing chart MDAT ML T CNTL State /co mple te / I ST A T /coun t /(PW >64) HI-Z CNTL -L CNTL -U CNTL -C Othe r Mo de Fig.3. /ISTAT output signal according to CNTL Register 13 KS9286B/KS9286B-L 3. EFM DEMODULATION BLOCK DIGITAL SIGNAL PROCESSOR for CDP The EFM block consists of EFM demodulator circuit which demodulates EFM data obtained from a disc, EFM phase detector circuit and control signal generator circuit etc. 1) EFM Demodulator The modulated 14-bit data is demodulated to 8-bit data through the demodulator circuit. There are two kinds of demodulated data, one is subcode data and the other is audio data, and the subcode data is inputted into subcode block and the audio data is written into built-in 16K SRAM and performed error correction. 2) Frame SYNC Detector, Protector and Inserter A. Frame SYNC Detector The data consists of frame unit, that is, it consists of frame SYNC, subcode data, audio data and redundancy data etc. The frame SYNC is detected in order to maintain the synchronization. B. Frame SYNC Protector and Inserter Occasionally, the frame sync is omitted or detected in the place where it does not exist by the effect of error or jitter on a disc. In these case, it is need to protect or insert frame SYNC signal. The window is made by using the WSEL of CNTL-S register to protect the frame SYNC, and it's width is determined by WSEL. If the frame SYNC is inputted to the window, it is true data and if it isn't inputted, it is ignored. If the frame SYNC is not detected in the frame SYNC protection window, one is inserted from the internal counter block. When continuous inserting of frame SYNC, the appointed number of frame according to the FSEM and FSEL of CNTL-S register is achieved, the ULKFS becomes "H" and the frame SYNC protection window is ignored. At that time, the frame SYNC is received absolutely, the ULKFS signal becomes "L" and the frame SYNC in window is received. LKFS 1 0 ULKFS 0 0 COMMENT Corresponding with play back frame SYNC and generated frame SYNC 1) Out of corresponding with play back frame SYNC and generated frame SYNC, but PBFR SYNC is detected in the window selected by WSEL. 2) Out of corresponding with PBFR SYNC and XTFR SYNC, the SYNC is inserted because it is'nt detected in the window selected by WSEL. 1) After insertion as many as the frame decided by FSEM and FSEL of CNTL-S register as frame isn't detected in the window. 2) In the case that the PBFR SYNC is not detected continually after 1) 0 1 Table 8 14 KS9286B/KS9286B-L 4. SUBCODE BLOCK DIGITAL SIGNAL PROCESSOR for CDP The 14-bit subcode SYNC signal(that is S0,S1) is detected in the subcode SYNC block. After detection of S0 and passing through a frame, the S1 is detected. The S0+S1 signal is outputted to S0S1 terminal, and the subcode data is outputted to SDAT terminal when the S0S1 signal is "H". The subcode data among the data inputted to EFMI terminal is demodulated to 8-bit subcode data (P,Q,R,S,T,U,V,W). It is synchronized with PBFR signal and outputted to SDAT terminal by SBCK clock. Among the eight subcode data, only Q data is selected and loaded to the eighty shift register by FBFR signal. The result of checking the CRC (Cycle Redundancy Check) of loading data is synchronized with S0S1 rising edge and outputted to SQOK terminal. If the result of CRC checking is error, "L" is outputted to SQOK terminal, and if it is true, "H" is outputted to SQOK terminal. In case of CRCQ of CNTL-Z register being "H", the result of CRC checking is outputted to SQDT terminal during from S0S1 "H" to SQCK negative edge. The following is the timing chart of subcode block . 1) SQCK Using External Clock: S0S1, SQOK, SQCK, SQDT Timing Chart SOS1 SQOK SQCK SQDT CRCQ=0 SQDT CRCQ=1 0 Q4 Q3 Q2 Q1 Q8 Q7 Q6 Q5 Q12 Q80 Q79 Q78 Q77 0 Q4 Q3 Q4 Q3 Q2 Q1 Q8 Q7 Q6 Q5 Q12 Q80 Q79 Q78 Q77 SQOK(n +1) Q4 Q3 Fig.4. Subcode-Q timing chart When the CRCQ of CNTL-Z register is "H", SQOK signal is outputted to SQDT terminal according SQCK signal, and when the CRCQ is "L", SQOK signal is not outputted to SQDT terminal. 15 KS9286B/KS9286B-L 2) SDAT, SBCK TIMING CHART DIGITAL SIGNAL PROCESSOR for CDP PBFR A SBCK SDAT B Q R S T U V W C 1 2 3 4 5 6 7 8 a. After PBFR becomes falling edge, SBCK becomes "L" during about 10µS. b. If S0S1 is "L", subcode P is outputted, and if S0S1 is "H", S0S1 is outputted. c. If the pulse inputted to the SBCK terminal is over seven, subcode data P, Q, R, S, T, U, V, W is repeated. Fig.5. Timing chart of Subcode-Q data output 16 KS9286B/KS9286B-L 5. ECC (Error Correction Code) Block DIGITAL SIGNAL PROCESSOR for CDP The function of ECC block is to recover damaged data to some extent when data on a disk is damaged. By using CIRC (Cross-interleave Reed-Solomon Code), C1(32,28: 2 Error) and C2 (28,24: 4 Erasure) error are corrected, and ECC is performed by the unit of one symbol of 8-bit. In C1 correcting, a C1 pointer is generated, and in C2 correcting , a C2 pointer send error information or the data which ECC gives. The information signal is used to deal with the error data, and the process of FLAG1, FLAG2, FLAG3, FLAG4, FLAG5 terminal. error correction can monitored by is generated. C1 & C2 pointer MODE C1 No error C1 1 error C1 2 error C1 Irretrirvable error C2 No error C2 1 error C2 2 error C2 3 error C2 4 error C2 Irretrievable error 1 C2 Irretrievable error 2 FLAG5 0 0 0 0 1 1 1 1 1 1 1 FLAG4 0 0 0 1 0 0 0 0 0 1 1 FLAG3 0 0 0 1 0 0 0 0 1 1 1 FLAG2 0 0 1 1 0 0 1 1 0 1 1 FLAG1 0 1 0 1 0 1 0 1 0 0 1 REMARK C1 correction start C1 pointer set C2 correction start C1 pointer copy C2 pointer set Table 9. Error Correction monitoring flag 17 KS9286B/KS9286B-L 6. INTERPOLATOR / MUTE BLOCK 1) Interpolator DIGITAL SIGNAL PROCESSOR for CDP When a burst error occurs on a disc, sometimes the data can't be corrected even if the ECC process is performed. The interpolator block revises the data by using a C2 pointer outputted through the ECC block. The data inputted to a data bus is inputted to the left and right channel respectively, in the order of C2 pointer, lower 8-bit and upper 8-bit. In case of C2PO being "H" and the occurrence of a single error, an average interpolation method is carried out with the range of the data before and after an error happens. A pre-hold method is taken when the C2 pointer is "H" and 3 errors occur continuously. When a check against a checked cycle LRCH is "L", R-ch data is outputted, and L-ch data is outputted when the check is "H". The following is timing chart of interpolator block. A B C G D E F H I J C2 p ointer B = ( A + C ) / 2: Average Interpolation F = E = D: Previous Data Hold G = (F + H ) / 2: Average Interpolation Fig.6. Interpolation 18 KS9286B/KS9286B-L 2) MUTE AND ATTENUATION DIGITAL SIGNAL PROCESSOR for CDP By using a mute terminal and the ATTM signal of the CNTL-S register, the audio data is muted or attenuated. A. Zero Cross Muting The audio data is muted, after ZCMT of CNTL-S register goes to "H", and in case that mute is "H" and the upper 6 bits of audio data become all "L" or "H". B. Muting The audio data is muted when the ZCMT of CNTL-S rgister is "L" and MUTE terminal is "H". C. Attenuation The signal attenuation is occured by ATTM of CNTL-S register and MUTE signal as following. ATTM 0 0 1 1 MUTE 0 1 0 1 Degree of Attenuation 0dB dB -12dB -12dB Table 10. 8 19 KS9286B/KS9286B-L 7. Digital Filter DIGITAL SIGNAL PROCESSOR for CDP The KS9286B has a built-in FIR ( Finite Impulse Response) digital filter. This digital filter consists of 8fs over sampling filter. 1) Block Diagram fS 51th FIR 2fS 13th FIR 4f S 9th FIR 8f S 16-bit A) Normal speed play mode f S* 51th FIR 2fS* 9th FIR 4fS* 16-bit B) Double speed play mode Fig.7. Digital filter block diagram 20 KS9286B/KS9286B-L 2) FILTER CHARACTERISTIC Ripple in passband : within + 0.5dB Attenuation in stopband: below -42dB DIGITAL SIGNAL PROCESSOR for CDP (a) NORMAL SPEED log magntude(dB) frequency (Fs) (b) DOUBLE SPEED log magntude(dB) frequency (Fs) Fig.8. Filter characteristic curve 21 KS9286B/KS9286B-L 8. DIGITAL AUDIO OUTPUT BLOCK DIGITAL SIGNAL PROCESSOR for CDP The 2-channel, 16-bit data is connected and outputted serially to other digital system by the digital audio interface format. 1) Digital Audio Interface Format for CD 191R 0L T 0R 1L 1R ........ 192T 190L 190R 191L 191R 0L 0R 0L : L-ch format including block sync preamble 1L ~ 191L : L-ch format including L-ch sync preamble 0R ~ 191R : R-ch format including R-ch sync preamble 1LRCH L-ch R-ch Preamble Modulated '0' 8-bit Modulated 16-bit audio data V U C P Co ntro l sig na l Fig.9. Digital audio output format A. Preamble It is used to discriminated against the block sync of data and L/R-channel of data. Fig.10. Preamble Signal 8.4672MHz L-ch sync (Except for Block Sync) R-ch sync Block sync(L-ch) Fig.10. Preamble Signal 22 KS9286B/KS9286B-L B. CONTROL SIGNAL DIGITAL SIGNAL PROCESSOR for CDP 1) Validity Bit: It is indicated that the error of 16-bit audio data exists, or doesn't. ("H": Error, "L": Valid data) 2) User Definable Bit: Subcode data output. S0S1 PBFR SBCK SBDT sync pattern P QRSTUVW Fig.11. Timing chart of digital audio output 3) Channel Status Bit: Output a high position information of 4-bit of Subcode-Q indicating the number of channel, pre-emphasis and copy etc. Indicates the CDP category. S0S1 SQDT ID0 ID1 COPY EMPH PBFR Fig.12. Timing chart of channel status data output 4) Parity Bit: Making even parity. 2) Timing Chart of Digital Audio Data Output 48 bits/slot LRCH (44.1KHz) BCK (2.12MHz) WDCH (88.2KHz) ADATA R-ch (MSB ) 16 15 14 13 12 11 10 9 876 54 32 1 L-ch (MSB ) 16 15 14 13 12 11 10 9 876 543 21 1 5 10 15 20 25 30 35 40 45 50 T Fig.13. Timing chart of audio data output 23 KS9286B/KS9286B-L 9. CLV SERVO BLOCK DIGITAL SIGNAL PROCESSOR for CDP The CNTL-C register is selected to control CLV (Constant Linear Velocity) servo by the data inputted from Micom. In the CNTL-C register, the CLV servo action mode is appointed by the data inputted from Micom to control the spindle motor. 1) Forward It is a mode of spindle motor rotates in forward direction. Output condition in forward mode is as following. SMDP H SMSD Hi-Z Table 11. SMEF L SMON H 2) Reverse It is a mode of spindle motor rotates in reverse direction. Output condition in reverse mode is as following. SMDP L SMSD Hi-Z SMEF L SMON H Table 12. 3) Speed-Mode The spindle motor is controlled roughly by speed mode when track jumping or EFM phase is unlocked. If a period of VCO is "T", the pulse width of frame sync is 22T. In case that the signal detected from EFM signal exceeds 22T by noise on the disc and etc., it must be removed, if not, the right frame sync can't be detected. In this case, the pulse width of EFM signal is detected by peak hold clock and bottom hold clock. ( Peak hold clock is XTFR/2 or XTFR/4, and bottom hold clock is XTFR/16 or XTFR/32.) The detected value is used for synchronized frame signal. If the frame signal is less than 21T, the SMDP terminal outputs "L", eaqul to 22T, outputs "Hi-Z", and more than 23T, ouputs "H". If the gain signal of CNTL-W register is "L", the output of SMDP terminal is reduced up to -12dB, if it is "H", there is no reduction. Output condition: SMSD="Hi-Z", SMEF="L", SMON="H". 24 KS9286B/KS9286B-L 4) Hspeed-Mode DIGITAL SIGNAL PROCESSOR for CDP The rough servo mode, which moves 20,000 tracks in high speed acts between the inside and outside of the CD. The mirror domain of track which hasn't pit is duplicated with 20KHz signal to EFM. In this case, servo action is unstable because the peak value of mirror signal which is longer than orignal frame sync signal which is detected. In Hspeed mode, by using the 8.4672/256MHz signal against peak hold and XTFR/16 or XTFR/32 signal against bottom hold, the mirror component is removed, and Hspeed servo action to be stable. The output condition is as following. SMDP - SMSD Hi-Z Table 13. SMEF L SMON H 5) Phase-Mode The phase mode is the mode to control the EFM phase. Phase difference between PBFR/4 and XTFR/4 is detected when NCLV of CNTL-Z register is "L",and phase difference between Read Base Counter/4 and Write Base Counter/4 detected when NCLV is "H", and the difference is outputted to SMDP(Fig.14). If the cycle of VCO/2 signal is put as "T" and it is put as "/WP" during a "H" period of PBFR, it outputs "H" to SMSD terminal from the falling edge of PBFR to the (/WP-278T) x 32, and then, outputs "L" to the falling edge of the next PBFR (Fig.15). 6) XPHSP-Mode The XPHSP mode is the mode used in normal operation. The LKFS signal made from frame sync block is to sampling which period is PBFR/ 16. If the sampling is "H", the Phase mode is performed, and if the sampling is eight of "L" continously, Speed-mode is performed automatically. The selection of peak hold period in Speed-mode and selection of bottom hold period and gain in Speed/ Hspeedmode is determined by CNTL-W register. 7) VPHSP-Mode The VPHSP mode is the mode used for rough servo control. It uses VCO instead of X-tal in the EFM pattern test. When the range of VCO center changes, VCO is easily locked because the rotation of a spindle motor changes in the same direction. 25 KS9286B/KS9286B-L 8) Stop-Mode The stop mode is used to stop the spindle motor. The output condition is as following. DIGITAL SIGNAL PROCESSOR for CDP SMDP L SMSD Hi-Z Table 14 SMEF L SMON L XTFR/4; (XTFR/8) PBFR/4; (PBFR/8) SMDP Hi-Z Hi-Z Hi-Z Fig.14. Timing chart of SMDP output 287T PBFR 288T SMSD (A) Timing chart of SMSD when PBFR is 278T 294T PBFR 512T SMSD (B) Timing chart of SMSD when PBFR is 294T Fig.15. Timing chart of SMSD output in phase mode 26 KS9286B/KS9286B-L DIGITAL SIGNAL PROCESSOR for CDP TB PHC BHC 1. 22T 2. 21T> TP 3. >23T EFM width( >22T) EFM width( >23T) PH F/F(>22T) PH F/F(>23T) BH F/F(>22T) BH F/F(>23T) Latch(22T) Latch(23T) SMDP 0 1 Z : 22T(output for 1) >23T noise 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 L : 21T(output for 2) H:(output for3) Fig.16. Timing chart of SMDP output when the gain is "H" in speed mode 27 KS9286B/KS9286B-L 10. DIGITAL PLL DIGITAL SIGNAL PROCESSOR for CDP This device contains Digital PLL in order to obtain the stable channel clock for demodulating EFM signal. The block diagram of Digital PLL is as follows. Frequency Synthesizer X'tal PHASE COMPARATO R 1/N DIVIDER LOW PASS FILTER VOLTAGE CONTROLED OSCILATOR EFMI DIGITAL MAIN PLL /PBCK Fig.17. Digital PLL circuit diagram 11. D/A Converter (Digital to Analog Converter) The KS9286B has a built-in 16-bit D/A converter. Digital audio data is a 2's complement serial format (MSB sirst), 28 KS9286B/KS9286B-L 1) Vref Terminal DIGITAL SIGNAL PROCESSOR for CDP Vref, the reference voltage across a resister-ladder, is usually recommended with VrefH1=5V, VrefL1=0V. One way of avoiding an amplitude mismatching between the Vref and OP AMP input connected to the output of D/ A converter is to reduce the analog output amplitude with VrefH2=5V and VrefL2=0V (At this time about 100uF capacitor should be connected from VreH1 and VrefL1 to GND). By the effect of built-in RH and RL with this choice, the maximum analog output amplitude result in a narrow range of about 1.5 ~ 3.5V for 0dB playback. VREFH1 VREFH2 D3 ~ D0, D15 ~ D7 V oltage Dividing D/A converter Analog MUX RCHOUT LCHOUT VREFL1 VREFL2 Control Circuit D6 ~ D4 Fig.18. Vref relation circuit 2) D/A Converter Electrical Characteristic The D/A Converter electrical characteristic built in KS9286B is as follows. (VDD=5V, VSS=0V, Ta=25oC) Characteristics Total Harmonic Distortion Signal to Noise Ratio Cross-Talk Symbol THD S/N CT Test Conditon Data=1kHz, 0dB VDD=4.5V Data=1kHz, 0dB Data=1kHz, 0dB MIN TYP MAX 0.08 Unit % dB dB 92 -85 Table 15 29 KS9286B/KS9286B-L 12. Digital De-Emphasis DIGITAL SIGNAL PROCESSOR for CDP The Emphasis/De-Emphasis circuit is used for improving S/N ration by decreasing high frequency noise in case of the frequency characteristic of signal not being changed. The digital de-emphasis circuit, which can de-emphasise the signal emphasised on disc, is built-in KS9286B, and the frequency characteristic is as follows. Frequency 1KHz 5KHz 10KHz 20KHz Characteristic -0.51dB -4.5dB -7.59dB -9.5dB Table 16. Frequency characteristic of de-emphasis circuit 30 KS9286B/KS9286B-L 13. ESP INTERFACE BLOCK 1) Introduction DIGITAL SIGNAL PROCESSOR for CDP Because the location of normal table CD Player used in family is fixed, it is possible to play music stabilitable when the degree of damage on disc is in limit range. But in now, it is general that user can hear music when moving by Walkman-CD Player. In this case, if user has been shocked suddenly, it often happens that music playing is unstable. On this, the ESP interface block is added to KS9286B for realizing the function of Anti-shock. The application circuit of using NPC anti-shock memory controller IC SM5859AF and KS9286B is as follows. YMDATA SM5859 M ic r o c on t r o l l e r YMCLK YMLD ZSENSE P ar t A 1 6K S RA M E FM º¹Á¶ E CC S UB - Q º¹Á¶ /ESP S0S1 /JIT VSS LRCKO BCKO ADATAO YBLKCK YFLSG YFCLK YLRCK YSCK YSRDATA /RAS /WE A0 to A10 D0 to D3 NCAS DRAM /RAS /WE A0 to A10 D0 to D3 /CAS /OE VSS C LV - S e r v o I NT E R P O L A T I O N P ar t B D ig i t a l F il t e r D ig i t a l d ee mp h a s i s D /A C on v e r t e r LRCKI BCKI ADATAI ZLRCK ZSCK ZSRDATA KS9286B Fig.19. ESP interface application 31 KS9286B/KS9286B-L DIGITAL SIGNAL PROCESSOR for CDP The operation of KS9286B is different when normal operation and forming anti- shock function with external ESP IC. From Fig.19, the operation of part B composed by Digital Filter, Digital de-emphasis and 16-bit D/A Converter in KS9286B and part A except part B is separated. When anti-shock function is used in case of /ESP Pin being "L", part A block operates in double speed and part B block operates in normal speed. That is, after EFM Demodula- tion, Error Correction and Interpolation block operation in double speed, audio data is inputted to ESP IC which is the anti-shock memory controller. Audio data received by ESP IC is saved in external memory and then inputted to KS9286B. In part B of KS9286B, the data is dealed with in normal speed and then outputted . The anti-shock function is not used in case of /ESP terminal being "H". 2) Timing Chart The interface timing diagram of ESP IC is as follows. 32 KS9286B/KS9286B-L DIGITAL SIGNAL PROCESSOR for CDP 88.2Khz LRCHO BCKO ADATAO D1 D0 D15 D14 D13 D1 D11 D10 D9 D8 2 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D1 D9 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 Fig.20. Timing chart of signal outputting to ESP IC 44.1Khz LRCHI BCKI ADATAI D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D 11 Fig.21. Timing chart of signal ESP IC outputting to DSP 33 KS9286B/KS9286B-L APPLICATION INFORMATION DIGITAL SIGNAL PROCESSOR for CDP 1. ESP Part If ESP IC is not used, you must connect follow pins to GND. - LRCHI - ADATAI - BCKI 2. Pin setting condition - TEST1 : Ground - FOK : Connect the servo IC # 40 Pin (KB9223) when use the FOK signal through /ISTAT pin otherwise, connect VDD or GND except upper application 34 KS9286B/KS9286B-L DIGITAL SIGNAL PROCESSOR for CDP SAMSUNG SEMICONDUCTOR SALES OFFICES HEAD OFFICE 8/11FL., SAMSUNG MAIN BLDG. 250, 2-KA, TAEPYUNG-RO, CHUNG-KU,SEOUL,KOREA C.P.O.BOX8780 TEL.....82(2) 776-0114 FAX.....82(2) 753-0967 SAMSUNG SEMICONDUCTOR EUROPE GMBH AM UNISYSPARK 1, 65843 SULZBACH/TS, GERMANY TEL.....49(6196) 58206 FAX.....49(6196) 750345 SAMSUNG ELECTRONICS TAIPEI OFFCE TWTC INTL TRADE BLDG., RM2508, 25F, NO.333, KEELYNG RD., SEC1, TAIPEI, TAIWAN, R.O.C TEL.....886(2) 757-7040 FAX.....886(2) 757-7286 SEMICONDUCTOR BUSINESS SALES & MARKETING DIVISION 16TH FL., SEVERANCE BLDG., 84-11, 5-KA, NAMDAEMOON-RO, CHUNG-KU, SEOUL, KOREA TEL.....82(2) 776-0114 FAX.....82(2) 751-6161 SAMSUNG ELECTRONICS JAPAN CO., LTD. HAMACHO CENTER BLDG., 31-1, NIHONBASHIHAMACHO 2-CHOME, CHUO-KU, TOKYO 103, JAPAN TEL.....81(3) 5641-9850 FAX.....81(3) 5641-9851 SAMSUNG ELECTRONICS SINGAPORE PTE LTD. 80, ROBINSON ROAD, #20-00 SINGAPORE 0106 TEL.....65-535-2808 FAX.....65-227-2792 GUMI BRANCH 5TH FL., SAMSUNG INSURANCE BLDG. 71, SONGJEONG, GUMI, KYUNGSANGBUK-DO, KOREA TEL.....82(546) 457-2525 FAX.....82(546) 457-2460 SAMSUNG ELECTRONICS HONGKONG CO., LTD. 65TH FL., CENTRAL PLAZA, 18 HARBOUR ROAD, WANCHAI, HONG KONG TEL.....852-2862-6900 FAX.....852-2866-1343 SAMSUNG ELECTRONICS SHANGHAI OFFICE SUITE 4034, SHEATON HUATING HOTEL, 1200 CAOXIBEILU, SHANGHAI 200030, CHINA TEL.....86(21)439-0707 FAX.....86(21)439-3798 SAMSUNG SEMICONDUCTOR INC. 3655 NORTH FIRST STREET SANJOSE, CA95134, USA TEL.....1(408) 954-7000 FAX.....1(408) 954-7286 TECHNICAL SUPPORT HOT LINE Phone: 82(331) 209-2878 Fax: 82(331) 209-2899 E-mail: sjcho@sec.samsung.com Circuit diagrams utilizing SAMSUNG products are included as a means of illustrating typical semiconductor applications; consequently, complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described herein any license under the patent rights of SAMSUNG or others. SAMSUNG reserves the right to change device specifications. 35