M372F3280DJ3-C

DRAM MODULE M372F320(8)0DJ3-C M372F320(8)0DJ3-C EDO Mode 32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V GENERAL DESCRIPTION The Samsung M372F320(8)0DJ3-C is a 32Mx72bits Dynamic RAM high density memory module. The Samsung M372F320(8)0DJ3-C consists of thirty-six CMOS 16Mx4bits DRAMs in SOJ 400mil packages and two 16 bits driver IC in TSSOP package mounted on a 168-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M372F320(8)0DJ3-C is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets. FEATURES • Part Identification Part number M372F3200DJ3-C M372F3280DJ3-C PKG SOJ SOJ Ref. 4K 8K CBR Ref. 4K/64ms ROR Ref. 8K/64ms 4K/64ms • Extended Data Out Mode Operation • CAS-before-RAS Refresh capability • RAS-only and Hidden refresh capability • LVTTL compatible inputs and outputs • Single 3.3V±0.3V power supply PERFORMANCE RANGE Speed -C50 -C60 tRAC 50ns 60ns tCAC 18ns 20ns tRC 84ns 104ns tHPC 20ns 25ns • JEDEC standard pinout & Buffered PDpin • Buffered input except RAS and DQ • PCB : Height(1650mil), double sided component PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front Pin Front Pin Front Pin VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS RSVD RSVD VCC W0 CAS0 29 *CAS2 57 30 RAS0 58 31 OE0 59 32 VSS 60 33 A0 61 34 A2 62 35 A4 63 36 A6 64 37 A8 65 38 A10 66 39 A12 67 40 VCC 68 41 RFU 69 42 RFU 70 43 VSS 71 44 OE2 72 45 RAS2 73 46 CAS4 74 47 *CAS6 75 48 W2 76 49 VCC 77 50 RSVD 78 51 RSVD 79 52 DQ18 80 53 DQ19 81 54 82 VSS 55 DQ20 83 56 DQ21 84 DQ22 DQ23 VCC DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS RSVD RSVD VCC RFU CAS1 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back *CAS3 RAS1 RFU VSS A1 A3 A5 A7 A9 A11 *A13 VCC RFU B0 VSS RFU RAS3 CAS5 *CAS7 PDE VCC RSVD RSVD DQ54 DQ55 VSS DQ56 DQ57 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ58 DQ59 VCC DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC PIN NAMES Pin Names A0, B0, A1 - A11 A0, B0, A1 - A12 DQ0 - DQ71 W0, W2 OE0, OE2 RAS0 - RAS3 CAS0, 1,4,5 VCC VSS NC PDE PD1 - 8 ID0 - 1 RSVD RFU Function Address Input(4K ref.) Address Input(8K ref.) Data In/Out Read/Write Enable Output Enable Row Address Strobe Column Address Strobe Power(+3.3V) Ground No Connection Presence Detect Enable Presence Detect ID bit Reserved Use Reserved for Future Use Pins marked ′* ′ are not used in this module. PD & ID Table Pin PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 50NS 1 0 0 0 1 0 0 0 0 0 60NS 1 0 0 0 1 1 1 0 0 0 NOTE : A12 is used for only M372F3280DJ3-C (8K Ref.) PD Note :PD & ID Terminals must each be pulled up through a register to VCC at the next higher level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C ID : 0 for Vss & 1 for N.C ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer. REV. 0.1 Oct. 2000 DRAM MODULE FUNCTIONAL BLOCK DIAGRAM RAS0 CAS0 OE0 W0 A0 A1-A11(A12) U0 M372F320(8)0DJ3-C RAS3 CAS5 OE2 W2 B0 A1-A11(A12) DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U27 RAS1 CAS1 RAS2 CAS4 DQ0-35 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U18 U9 DQ36-71 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U1 U19 U10 U28 U2 U20 U11 U29 U3 U21 U12 U30 U4 U22 U13 U31 U5 U23 U14 U32 U6 U24 U15 U33 U7 U25 U16 U34 U8 U26 U17 U35 NOTE : A12 is used for only M372F3280DJ3(8K Ref.) Vcc 0.1 or 0.22uF Capacitor under each DRAM Vss To all DRAMs A0 B0 A1-A11(A12) W0, OE0 W2, OE2 U0-U8, U18-U26 U9-U17, U27-U35 U0-U35 U0-U8, U18-U26 U9-U17, U27-U35 REV. 0.1 Oct. 2000 DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS M372F320(8)0DJ3-C Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +125 36 50 Unit V V °C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3 *2 Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Unit V V V V *1 : VCC+1.3V at pulse width≤15ns, which is measured at VCC. *2 : -1.3V at pulse width≤15ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -50 -60 Don′t care -50 -60 -50 -60 Don′t care -50 -60 Don′t care Don′t care M372F3200DJ3 Min - M372F3280DJ3 Max Min -10 -10 2.4 Max 1458 1278 100 1458 1278 1638 1458 30 1998 1818 10 10 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V 1998 1818 100 1998 1818 1638 1458 30 1998 1818 10 10 0.4 -10 -10 2.4 - ICC1* : Operating Current * (RAS, CAS, Address cycling @ tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4* : Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0≤VIN≤Vcc+0.3V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3 , address can be changed maximum once while RAS=V IL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC. REV. 0.1 Oct. 2000 DRAM MODULE CAPACITANCE (TA = 25°C, f = 1MHz) Item Input capacitance[A0, B0, A1 - A12] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0 - RAS3] Input capacitance[CAS0, 1,4,5] Input/Output capacitance[DQ0 - 71] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min - M372F320(8)0DJ3-C Max 20 20 73 20 24 Unit pF pF pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command set-up time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period(4K & 8K) CAS to W delay time RAS to W delay time Symbol Min -50 Max Min 104 153 50 18 30 8 8 8 1 30 50 13 36 8 15 10 10 5 5 0 7 30 0 0 -2 0 7 7 13 7 -2 13 64 33 68 38 82 10K 32 20 10K 18 50 8 8 8 1 40 60 15 38 10 18 13 10 5 8 0 10 35 0 0 -2 0 10 10 15 10 -2 15 64 10K 40 25 10K 18 50 60 20 35 84 128 -60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 7 7,13 9,13 9,13 13 8 8,13 7 13 4,13 10,13 13 13 13 13 13 3,4,10 3,4,5,13 3,10,13 3,13 3,13 6,11,13 2 Unit Note tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL tDS tDH tREF tCWD tRWD REV. 0.1 Oct. 2000 DRAM MODULE AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Parameter Column address to W delay time CAS precharge time to W delay time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page cycle time Hyper page read-modify-write cycle time CAS precharge time(Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Output data hold time(C-B-R refresh) Output buffer turn off delay time from RAS Output buffer turn off delay time from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper page cycle) Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive Symbol -50 Min 45 47 10 8 3 33 20 70 8 50 35 15 8 18 15 8 5 10 3 8 20 5 5 5 5 13 18 18 18 8 5 10 3 8 20 5 5 5 5 200K 25 77 10 60 40 15 8 Max Min 53 58 10 8 3 M372F320(8)0DJ3-C -60 Max Unit ns ns ns ns ns Note 7 13 13 13 3,13 12 12 tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE 40 ns ns ns ns 200K ns ns ns ns 13 13 13 13 13 13 13 6,11 6,13 13 20 18 ns ns ns ns ns 13 18 ns ns ns ns ns ns ns tPD tPDOFF 10 2 7 2 10 7 ns ns REV. 0.1 Oct. 2000 DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC (max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes tha tRCD≥tRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWD≥tRWD(min), tCWD≥tCWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. M372F320(8)0DJ3-C 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going , the open circuit condition of the output is achieved by RAS going. 12. tASC≥6ns. 13. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. REV. 0.1 Oct. 2000 DRAM MODULE READ CYCLE M372F320(8)0DJ3-C tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tRAD tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tWEZ tAA OE VIH VIL - tCEZ tOEZ tOEA tOLZ tCAC VOH VOL - tRAC OPEN tCLZ tREZ DATA-OUT DQ Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN M372F320(8)0DJ3-C tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN M372F320(8)0DJ3-C tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ VIH VIL - Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE READ - MODIFY - WRITE CYCLE M372F320(8)0DJ3-C tRAS RAS VIH VIL - tRWC tRP tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tASR VIH VIL - tRAH tASC tCAH tCSH A ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL - tRWL tCWL tWP tRWD OE VIH VIL - tOEA tOLZ tCLZ tCAC tAA tOED tOEZ VALID DATA-OUT tDS tDH DQ VI/OH VI/OL - tRAC VALID DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE READ CYCLE M372F320(8)0DJ3-C tRASP RAS VIH VIL ¡ó tRP tCSH tCRP CAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRCD tCAS tRAD tASR A VIH VIL - tRAH tASC tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH tREZ ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tCPA tCAC tAA tAA tCPA tCAC tOEA tCAC tOEP tDOH VALID DATA-OUT tCAC tAA tCPA tOCH tOEA tCAC tAA tCHO tOEP OE VIH VIL - tOEA tOEZ VALID DATA-OUT VALID DATA-OUT tRAC DQ VOH VOL - tOEZ tOEZ tOLZ tCLZ VALID DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN M372F320(8)0DJ3-C tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP CAS VIH VIL - tHPC tRCD tCAS tRAD tCSH tCP tCAS ¡ó tHPC tCP tRSH tCAS tASR A VIH VIL - tRAH tASC tCAH tASC tCAH ¡ó ¡ó tASC tCAH ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP tCWL ¡ó ¡ó ¡ó tWCS tWCH tWP tCWL tRWL tWP tCWL OE VIH VIL - tDS DQ VIH VIL - tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDS tDH ¡ó VALID DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE READ-MODIFY-WRITE CYCLE M372F320(8)0DJ3-C RAS VIH VIL - tRASP tCSH tCRP tRSH tHPRWC tRCD tCAS tRAD tRAH tASR tASC COL. ADDR tRP tCP tCAS tRAL tCRP CAS VIH VIL - tCAH tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tCWL tWP tCWD tCWD tAWD tCPWD tOEA tOED tRWL tCWL tWP tAWD tRWD OE VIH VIL - tOEA tCAC tAA tRAC tOEZ tDS tCAC tOED tDH tAA tDH tOEZ tDS DQ VI/OH VI/OL - tCLZ tOLZ VALID DATA-OUT tCLZ VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE READ AND WRITE MIXED CYCLE M372F320(8)0DJ3-C tRASP RAS VIH VIL READ(tCAC ) READ(tCPA) WRITE READ(tAA) tRP tHPC tCP CAS VIH VIL - tHPC tCP tCP tCAS tASC COL. ADDR tHPC tCAS tASC tCAH COL. ADDR tRAD tASR tRAH tASC tCAS tCAH tCAS tCAH tCAH tASC COLUMN ADDRESS A VIH VIL - ROW ADDR COLUMN ADDRESS tRCS W VIH VIL - tRCH tRCS tRCH tWCS tWCH tRCH tWPE tCLZ tCPA OE VIH VIL - tWED tOEA tCAC tAA DQ VI/OH VI/OL - tWEZ tDH tWEZ VALID DATA-OUT tDS VALID DATA-IN tAA VALID DATA-OUT tREZ tRAC VALID DATA-OUT Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W , OE, DIN = Don′t care DOUT = OPEN tRC RAS VIH VIL - M372F320(8)0DJ3-C tRP tRAS tCRP tRPC tCRP CAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don′t care tRP RAS VIH VIL - tRC tRAS tRP tRPC tCP tCSR tCHR tRPC CAS VIH VIL - tWRP W VIH VIL - tWRH tCEZ DQ VOH VOL - OPEN Don′t care Undefined * In RAS -only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. REV. 0.1 Oct. 2000 DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) M372F320(8)0DJ3-C tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRRH tWRH tWRP tAA OE VIH VIL - tOEA tOLZ tCAC tCLZ tRAC tOEZ DATA-OUT tCEZ tREZ tWEZ DQ VOH VOL - OPEN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN M372F320(8)0DJ3-C tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP tRCD tRSH tCHR CAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWRP tWCH tWP tWRH OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Don′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE M372F320(8)0DJ3-C tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W OE VIH VIL VIH VIL - tWRP tWRH tRCS tAA tCAC tRRH tRCH DQ VOH VOL - tCLZ tOEA tOEZ DATA-OUT tCEZ tREZ tWEZ WRITE CYCLE W VIH VIL VIH VIL - tWRP tWRH tWCS tRWL tCWL tWCH tWP OE tDS DQ VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tRCS tAWD tCWD tCAC tWP tCWL tRWL tAA tOEA OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Don′t care Undefined NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. REV. 0.1 Oct. 2000 DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care M372F320(8)0DJ3-C tRP RAS VIH VIL - tRASS tRPS tRPC tCP tCHS tCSR tRPC CAS VIH VIL - tCEZ DQ VOH VOL - OPEN W VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Don′t care tRC tRAS tRPC tCP CAS VIH VIL - tRP RAS VIH VIL - tRP tRPC tCSR tCHR tWTS W VIH VIL - tWTH tCEZ DQ VOH VOL - OPEN Don ′t care Undefined REV. 0.1 Oct. 2000 DRAM MODULE PACKAGE DIMENSIONS M372F320(8)0DJ3-C Units : Inches (millimeters) 6.950 (176.53 ) 5.250 (133.350) 5.014 (127.350) 0.85 (21.59) 0.118 (3.000) 0.054 (1.372) R 0.079 (R 2.000) 1.65 (41.91) 0.157± 0.004 (4.000 ± 0.100) 0.700 (17.780) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) R 0.055(1.45) 0.118 (3.000) .118DIA±.004 (3.000DIA±.100) 0.350 (8.890) 0.100Min (2.540Min) A B C ( Front view ) 0.350Max (8.89Max) ( Back view ) 0.050±0.0039 (1.270±0.10) 0.250 (6.350) 0.250 (6.350) (2.540 M in) 0.100 M in 0.039±.002 (1.000±.050) 0.008±.0.006 (0.200±.0.150) 0.050 (1.270) 0.1230± .0050 (3.125± .125) 0.079±.0040 (2.000±.100) 0.1230± .0050 (3.125± .125) 0.079±.0040 (2.000±.100) Detail A Tolerances : ±.005(.13) unless otherwise specified The used device is 16Mx4 DRAM with EDO mode, SOJ. DRAM Part No. : M372F3200DJ3 - K4E640412D-J. M372F3280DJ3 - K4E660412D-J. Detail B Detail C REV. 0.1 Oct. 2000