S1M8831A

FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 INTRODUCTION The S1M8831A/33 is a Fractional-N frequency synthesizer with integrated prescalers, designed for RF operation up to 1.2GHz/K-PCS and for IF operation up to 520MHz. The fractional-N synthesizer allows fast-locking, low phase noise phase-locked loops to be built easily, thus having rapid channel switching and reducing standby time for extended battery life. The S1M8831A/33 based on ∑ - ∆ fractional-N techniques solves the fractional spur problems in other fractional-N synthesizers based on charge pump compensation. The synthesizer also has an additional feature that the PCS/CDMA channel frequency in steps of 10kHz can be accurately programmed. 24-QFN-3.5×4.5 The S1M8831A/33 contains dual-modulus prescalers. The S1M8831A RF synthesizer adopts an 8/9 prescaler (16/17 for the S1M8833) and the IF synthesizer adopts an 8/9 prescaler. Phase detector gain is user-programmable for maximum flexibility to address IS-95 CDMA and IMT2000. Various program-controlled power down options as well as low supply voltage help the design of wireless cell phones having minimum power consumption. Using the Samsung's proprietary digital phase-locked-loop technique, the S1M8831A/33 has a linear phase detector characteristic and can be used for very stable, low noise PLLs. Supply voltage can range from 2.7V to 4.0V. The S1M8831A/33 is available in a 24-QFN package. FEATURES • High operating frequency dual synthesizer — S1M8831A: 0.71 to 1.2GHz(RF)/ 45 to 520MHz(IF) — S1M8833: 1.6 to 1.65GHz(RF)/ 45 to 520MHz(IF) • • • • Operating voltage range: 2.7 to 4.0V Low current consumption (S1M8831A: 5.0mA, S1M8833: 7.0mA) Selectable power saving mode (ICC = 1uA typical @ 3V) Dual-modulus prescaler and Fractional-N/Integer-N: — S1M8831A — S1M8833 — S1M8831A/33 • • • • • (RF) 8/9 (RF) 16/17 (IF) 8/9 Fractional-N Fractional-N Integer-N Excellent in-band phase noise ( – 85dBc/Hz @ PCS, -90dBc/Hz @CDMA) Improved fractional spurious performance ( < 80dBc) Frequency resolution (= 10kHz/64 @ fref = 9.84MHz) Fast channel switching time: < 500us Programmable charge pump output current: from 50uA to 800uA in 50uA steps Programmability via on-chip serial bus interface 1 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL APPLICATIONS • • • High-rate data-service cellular telephones (for CDMA): S1M8831A, S1M8833 High-rate data-service portable wireless communications (for Korean-PCS): S1M8833 Other wireless communications systems ORDERING INFORMATION Device +S1M8831A01-G0T0 +S1M8833X01-G0T0 + : New Product Package 24-QFN-3.5×4.5 Operating Temperature -40 to +85C 2 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 BLOCK DIAGRAM OUT0 24 OUT1 23 VDDIF 22 VDDRF 1 RF LD 2 RF Charge Pump RF Phase Detector IF Phase Detector IF Charge Pump 20 RF Prescaler IF Prescaler -+ foLD Data Out Multiplexer IF LD 21 VPIF VPRF CPORF 3 CPOIF DGND 4 +- 19 DGND Prescaler Control finRF 5 RF Programmable Counter IF Programmable Counter Prescaler Control 18 finIF finRF 6 RF N-Latch IF N-Latch 2-Bit Control 17 finIF GNDRF 7 Frac-N Latch & Σ−∆ Modulator 24-Bit Shift Register 16 GNDIF OSCx 8 RF R-Latch IF R-Latch 15 LE OSCin 9 RF Reference Counter IF Reference Counter 14 DATA 13 10 foLD 11 RF_EN 12 IF_EN CLOCK 3 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL PIN CONFIGURATION OUT0 24 OUT1 23 VDDIF 22 VDDRF VPRF CPORF DGND finRF finRF GNDRF OSCx OSCin 1 2 3 4 5 6 7 8 9 S1M8831A/33 21 20 19 18 17 16 15 14 13 VPIF CPOIF DGND finIF finIF GNDIF LE DATA CLCOK 10 foLD 11 RF_EN 24-QFN 12 IF_EN 4 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 PIN DESCRIPTION Pin No. 1 2 3 4 5 6 Symbol VDDRF VPRF CPoRF DGND f inRF f inRF I/O – – O – I I Description RF PLL power supply(2.7V to 4.0V). Must be equal to VDDIF. Power supply for RF charge pump. Must be ≥ VDDRF and VDDIF. RF charge pump output. Connected to an external loop filter. Ground for RF PLL digital circuitry. RF prescaler input. Small signal input from the external VCO. RF prescaler complementary input. For a single-ended output RF VCO, a bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Ground for RF PLL analog circuitry. RF R counter input (IF_N[22]=0) or not-use (IF_N[22]=1) which can be configured depending on the state of the program bit IF_N[22]. Oscillator input to drive both the IF and RF R counter inputs (IF_N[22]=1) or only the IF R counter (IF_N[22]=0) which can be configured depending on the state of the program bit IF_N[22]. Multiplexed output of N or R divider and RF/IF lock detect. RF PLL Enable (enable when high, power down when low). Controls the RF PLL to power down directly, not depending on a program control. Also sets the charge pump output to be in TRI-STATE when LOW. Powers up when HIGH depends on the state of RF_CTL_WORD. IF PLL Enable(enable when high, power-down when low). Controls the IF PLL to power down directly. The same as RF_EN except that power-up depends on the state of IF_CTL_WORD. CMOS clock input. Data for the various counters is clocked into the 24-bit shift register on the rising edge. Binary serial data input. Data entered MSB (Most Significant Bit) first. Load enable when LE goes HIGH. High impedance CMOS input. Ground for IF analog circuitry. IF Prescaler complementary input. For a single-ended output IF VCO, a bypass capacitor should be placed as close as possible to this pin. IF prescaler input. Small signal input from the VCO. Ground for IF PLL digital circuitry. IF charge pump output. Connected to an external loop filter. 7 8 9 GNDRF OSCx OSCin – I I 10 11 foLD RF_EN O I 12 IF_EN I 13 14 15 16 17 18 19 20 CLOCK DATA LE GNDIF f inIF finIF DGND CPoIF I I I – I I – O 5 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL PIN DESCRIPTION (Continued) Pin No. 21 22 23 24 Pin Name VPIF VDDIF OUT1 OUT0 I/O – – O O Descriptions Power supply for IF charge pump. Must be ≥ VDDRF and VDDIF. IF PLL power supply (2.7V to 4.0V). Must be equal to VDDRF. Programmable CMOS output. Level of the output is controlled by RF_N[19] bit. Programmable CMOS output. Level of the output is controlled by RF_N[18] bit. In the speedy lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and tri-state. 6 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 EQUIVALENT CIRCUIT DIAGRAM CLOCK, DATA, LE foLD OSCin, OSCx CPORF, CPOIF finRF, finRF, finIF, finIF finRF, finIF finRF, finIF Vbias 7 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Characteristics Power supply voltage Voltage on any pin with GND = 0 volts Power dissipation Operating temperature Storage temperature Symbol VDD VI PD Ta TSTG Value 0.0 to 4.0 -0.3 to VDD + 0.3 600 -40 to +85 -65 to +150 Unit V V mW °C °C ELECTROSTATIC CHARACTERISTICS Characteristics Human body model Machine model Charge device model Pin No. All All All ESD Level < ± 2000 < ± 300 < ± 800 Unit V V V NOTE: These devices are ESD sensitive. These devices must be handled in an ESD protected environment. 8 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 ELECTRICAL CHARACTERISTICS (VDD = 3.0V, VP = 3.0V, Ta = 25°C, unless otherwise specified.) Characteristic Power supply voltage Symbol VDD VP Power supply current S1M8831A RF+IF S1M8833 RF+IF S1M8831A RF+IF S1M8833 RF+IF IF only Power down current Digital Inputs: CLOCK, DATA and LE High level input voltage Low level input voltage High level input current Low level input current Reference Oscillator Input: OSCin Input current IIHR IILR Digital Output: foLD High level output voltage Low level output voltage VOH VOL Iout = -500µA Iout = +500µA VDD-0.4 Test Conditions Min. 2.7 VDD Typ. 3.0 3.0 5.0 7.0 3.5 5.5 1.5 Max. 4.0 4.0 Unit V IDD Fractional-N mode (fosc = 19.68MHz, RF R = 2) Quiescent State mA IPWDN VIH VIL IIH IIL VDD = 3.0V VDD = 2.7V to 4.0V VDD = 2.7V to 4.0V VIH = VDD = 4.0V VIL = 0V, VDD = 4.0V VIH = VDD = 4.0V VIL = 0V, VDD = 4.0V -100 -1.0 -1.0 0.7VDD 1 10 µA V 0.3VDD V µA µA µA µA V +1.0 +1.0 +100 0.4 V 9 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL ELECTRICAL CHARACTERISTICS (Continued) (VDD = 3.0V, VP = 3.0V, Ta = 25°C, unless otherwise specified.) Characteristic RF operating frequency S1M8833 Symbol f inRF Test Conditions Fractional-N mode (fosc = 19.68MHz, RF R = 2) Fractional-N mode (fosc = 19.68MHz, RF R = 2) f inIF OSCin f PD PfinRF VDD = 3.0V VDD = 4.0V IF input sensitivity Reference oscillator input sensitivity RF charge pump output current PfinIF VOSCin VDD = 2.7V to 4.0V -15 -10 -10 0.5 VDD = 3.0 Min. 1.6 Typ. Max. 1.65 Unit GHz Operating Frequency, Input Sensitivity (Programmable Divider, PFD) S1M8831A 0.71 1.2 GHz IF operating frequency Reference oscillator input frequency Phase detector operating frequency RF input sensitivity 45 2 520 40 10 0 0 0 VDD MHz MHz MHz dBm dBm dBm VPP Charge Pump Outputs: CPoRF, CPoIF ICPRFSOURCE_min VCP = VP/2, RF_CP_WORD=0000 VCP = VP/2, RF_CP_WORD=0000 VCP = VP/2, RF_CP_WORD=1111 VCP = VP/2, RF_CP_WORD=1111 VCP = VP/2, CP_GAIN_8=0 VCP = VP/2, CP_GAIN_8=0 VCP = VP/2, CP_GAIN_8=1 VCP = VP/2, CP_GAIN_8=1 -50 +50 -800 uA uA uA ICPRFSIINK_min ICPRFSOURCE_ max ICPRFSIINK_max +800 -100 +100 -800 +800 uA uA uA uA uA IF charge pump output current ICPRFSOURCE_min ICPRFSIINK_min ICPRFSOURCE_max ICPRFSIINK_max 10 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 ELECTRICAL CHARACTERISTICS (Continued) (VDD = 3.0V, VP = 3.0V, Ta = 25°C, unless otherwise specified.) Characteristic Charge pump leakage current Sink vs. Source mismatch Output current magnitude variation vs. Voltage Output current vs. Temperature Serial Data Control CLOCK frequency CLOCK pulse width high CLOCK pulse width low DATA set up time to CLOCK rising edge DATA hold time after CLOCK rising edge LE pulse width CLOCK rising edge to LE rising edge f CLOCK tCWH tCWL tDS tDH tLEW tCLE 50 50 50 10 50 50 10 MHz ns ns ns ns ns ns Symbol ICPL ICP-SIINK vs ICP-SOURCE ICP vs VCP ICP vs TA Test Conditions 0.5V ≤ VCP ≤ VP0.5V VCP = VP/2 0.5V ≤ VCP ≤ VP-0.5V VCP = VP/2 Min. -2.5 3 10 10 Typ. Max. +2.5 10 15 Unit nA % % % 11 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL FUNCTIONAL DESCRIPTION finRF finRF + - RF Prescaler RF N Counter RF Phase Detector RF LD RF Charge Pump CPoRF ∑ -∆ Modulator CLOCK DATA LE Serial Data Control CMOS Output MUX OUT0 OSCx RF R Counter foLD Data Out Multiplexer foLD OSCin IF R Counter CMOS Output MUX IF LD IF Phase Detector IF Charge Pump OUT1 finIF finIF + - IF Prescaler IF N Counter CPoIF The Samsung S1M8831A/33 is RF/IF dual frequency synthesizer IC which supports Fractional-N mode for RF PLL and Integer-N mode for IF PLL depending on a program control. S1M8831A/33 combined with external LPFs and external VCOs forms PLL frequency synthesizer. The frequency synthesizer consists of prescalers, pulse-swallowed programmable N counters, programmable reference R counters, phase detectors, programmable charge pumps, analog LD (Lock Detector), serial data control, etc. An input buffer in the prescalers amplifies an RF input power of -10dBm from external RF/IF VCOs to a sufficient ECL switching level to drive the following ECL divider so that it can normally operate even in a smaller input power less than -10dBm. The amplified VCO output signal is divided by the prescaler with a pre-determined divide ratio (div. 8/9 in S1M8831A, div. 16/17 in S1M8833, div. 8/9 in IF), the N counter, or the Fractional-N circuitry ( Σ - ∆ modulator). External reference signal is divided by the R counter to set the comparison frequency of the PFD. The divide ratios of the programmable counters can be programmed via the serial bus interface. These two signals drive the both inputs of the phase detector. The phase detector drives the charge pump by comparing frequencies and phases of the above two signals. The charge pump and the external LPF make the control voltage for the external VCO and finally the VCO generates the appropriate frequency signal. 12 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 When the PLL is in the locked state, the RF VCO's frequency will be NINT + NFRAC times the comparison frequency, where NINT is the integer divide ratio and NFRAC is the fractional component. The S1M8831A/33 has new improved features compared to conventional Integer-N PLLs. The Fractional-N PLL is available for the RF. The fractional synthesis allows the PFD comparison frequency to be increased while maintaining the same channel frequency as in AMPS and IS-95A/B/C. It makes possible to widen a loop bandwidth as wide as 20kHz or more for a faster lock-up time and to improve in-band phase noise performance due to a reduced divide ratio N. Such S1M8831A/33 in the Fractional-N mode is suitable for CDMA, GSM and Korean PCS band applications. Also, from the programmability of the charge pump, the user can easily design a stable loop due to free selection of loop components and reach to a low spurs, a low power PLLs due to an optimized current selection. Prescaler The RF/IF prescaler consists of a differential input buffer and ECL frequency dividers. The input buffer amplifies an input signal from an external VCO to the required level set by sensitivity requirements. The output of the amplifier delivers a differential signal to the divider with the correct DC level. The buffer may be either singleended or differentially driven. The single-ended operation is preferred in typical applications due to external VCO. In this case, we recommend that the complementary input fin of the input buffer be AC coupled to ground through external capacitors, even though it is internally coupled to ground via an internal 10pF capacitor. The other input pin fin of the buffer also needs external capacitor for decoupling the DC component and controlling the input power level. The RF prescalers of S1M8831A and S1M8833 provide 8/9 and 16/17 prescaler ratio, respectively. The IF prescaler of S1M8831A/33 contains 8/9 dual modulus prescaler. Reference Oscillator Inputs The reference oscillator frequency is provided by an external reference such as TCXO the OSCin and OSCx pins. When the OSC bit is LOW, the oscillator input pins (OSCin and OSCx) drive the IF R and R counters separately. When the OSC bit is HIGH, on the other hand, the oscillator input pin OSCin drives both IF R and RF R counters. Programmable Dividers (RF/IF N Counters) The RF N counter can be configured as a fractional counter. The fractional-N counter is selected when the FracN_SEL bit becomes HIGH. In the fractional mode, the S1M8831A is capable of offering a continuous integer divide range from 72 to 1008 and the S1M8833 offering a continuous integer divide range from 161 to 168. The S1M8831A/33 IF N counter supports an integer counter mode only, not including fractional counter, and is capable of operating from 45MHz to 520MHz offering a continuous integer divide range from 72 to 32767. 13 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL ∑ - ∆ Modulator The RF part of S1M8831A/33 adopts the Σ -∆ modulator as a core of the fractional counter that makes it possible to obtain divide ratio N to be a fractional number between two contiguous integers. The Σ -∆ modulator effectively randomizes the quantization noise generated from digitizing process and results in extreme suppression of inband noise power by pushing it out to out-of-band as in conventional Σ -∆ data converter. This technique eliminates the need for compensation current injection into the loop filter and improves fractional spurious performance, suitable for high-tier applications. The ∑-∆ modulator operates only for fractional-N mode, when the Frac-N_SEL is HIGH. For proper use of the fractional mode, the user should be kept in mind that 1. A fractional number should be set in the range from -0.5 to 0.5 in step of 1/62976. 2. The clock frequency fixed at 9.84MHz ( = 19.68MHz/2) is recommended for the ∑-∆ modulator which is an optimum condition for achieving better electrical performances related to the fractional noise and power consumption. Only when using the clock frequency, the S1M8831A/33 guarantees the exact frequency resolutions: 10kHz for CDMA PCS and 30kHz for CDMA cellular. Note that the clock frequency much lower than 9.84MHz can deteriorate the fractional noise performance. Phase-Frequency Detector (PFD) and Charge Pump (CP) The RF/IF phase detector composed of PFD and CP outputs pump current into an external loop filter in proportional to the phase difference between outputs of N and R counter . The phase detector has a better linear transfer characteristic due to a feedback loop to eliminate dead zone. The polarity of the PFD can be programmed using RF_PFD_POL/IF_PFD_POL depending on whether RF/IF VCO characteristics are positive or negative. (programming descriptions for phase detector polarity) Power-Down (or Power-Save) Control Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits (PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the program control bits determine the state of power control. Power down forces all the internal blocks to be deactivated and the charge pump output to be in the TRISTATE. The control register, however, remains active for serial programming and is capable of loading and latching in data during the power down. 14 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 PROGRAMMING DESCRIPTION The S1M8831A/33 can be programmed via the serial bus interface. The interface is made of 3 functional signals: clock, data, and latch enable(LE). Serial data is moved into the 24-bit shift register on the rising edge of the clock. These data enters MSB first. When LE goes HIGH, data in the shift register is moved into one of the 4 latches (by the 2-bit control). MSB Data Flow (MSB First) DATA[23:2] LSB CTL[1:0] Control Bit Map (CTL[1:0]) Control Bits CTL2(CTL[1]) 0 0 1 1 CTL1(CTL[0] 0 1 0 1 RF/IF R counter IF N counter RF N counter RF Frac counter Data Location Data Bit Map (DATA[23:2]) First Bit 23 RIF_R IF_N TEST OSC 22 21 20 19 18 17 16 15 Register Bit Location 14 13 12 11 10 9 8 7 6 5 4 3 2 Last Bit 1 0 IF_NA_CNT R(3 bits) RF_CP_WORD RF_NB_CNTR(7 bits) FRAC_CNTR(17 bits) FoLD(4 bits) 1 1 0 1 0 0 0 1 TEST IF_CTL_ WORD IF_CP_ WORD IF_R_CNTR(15 bits) IF_NB_CNTR(3 bits) RF_N RF_Frac RF_CTL_WORD RF_NA_CNTR(4 bits) CMOS TEST NOTE: Test bits are reserved and should be set to be zero(Low) for normal usage. 15 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Control Words OSC Control bits IF_N[22] Acronym OSC LOW (0) Separate inputs; OSCin: for IF, OSCx: for RF Normal operation Power up Asynchronous power down 1X Negative slope Normal operation Power up Integer-N mode CMOS output Voltage LOW Voltage LOW HIGH (1) Comments Common input Reference through OSCin for oscillator input both RF and IF control IF counter reset Power down Synchronous power down 8X Positive slope RF counter reset Power down Fractional-N mode Speedy Lock mode Voltage HIGH Voltage HIGH pin #23 pin #24 RF charge pump IF IF RF and IF IF charge pump IF PFD RF RF RF; PLL mode selection IF_CTL_WORD IF_N[21] IF_N[20] IF_N[19] IF_CNT_RST PWDN_IF PWDN IF_CP_GAIN IF_PFD_POL RF_CNT_RST PWDN_RF Frac-N_SEL Speedy_Lock OUT1 OUT0 RF_CP_LVL IF_CP_WORD RF_CTL_WORD IF_N[18] IF_N[17] RF_N[23] RF_N[22] RF_N[21] CMOS RF_N[20] RF_N[19] RF_N[18] RF_CP_WORD RF_N[17:14] Select 16-level charge pump current (RF charge pump gain for control codes in detail) Negative slope Positive slope Select LDs and monitoring mode of internal counters. (foLD control for control codes in detail) RF_N[13] foLD RF_N[5:2] RF_PFD_POL foLD RF PFD Lock Detector (LD), test mode — Counter reset mode resets R & N counters. — IF charge pump current can be selected to high current (8X) or low current (1X) mode. — In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and tri-state. The Speedy Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a low impedance (< 150Ω) while a high charge pump gain (≥ S 8X) is selected and otherwise to the TRISTATE. — For using a programmable CMOS output, the CMOS output bit(RF_N[20]=L) should be activated and then the desired logic level should be programmed with the control bits RF_N[18] for OUT0 and RF_N[19] for OUT1. 16 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Programmable Reference Counter (IF_R_CNTR[16:2]) If the control bit is 00, data is moved from the 24-bit shift register into the R-latch which sets the IF reference counter. Serial data format is shown in the table below. MSB TEST 23 Reserved for Test 17 16 RIF_R[23:0] IF_R_CNTR[16:2] ; 3 ~ 32767 0 21 Division Ratio of the IF R Counter, IF_R_CNTR(RI) Control Bits LSB 0 0 • 15-Bit IF R Counter Division Ratio Division ratio: 3 to 32767 (The divide ratios less than 3 are prohibited) Data are shifted in MSB first Division Ratio 3 4 • 32767 RI 14 0 0 • 1 RI 13 0 0 • 1 RI 12 0 0 • 1 RI 11 0 0 • 1 RI 10 0 0 • 1 RI 9 0 0 • 1 RI 8 0 0 • 1 RI 7 0 0 • 1 RI 6 0 0 • 1 RI 5 0 0 • 1 RI 4 0 0 • 1 RI 3 0 0 • 1 RI 2 0 0 • 1 RI 1 0 0 • 1 RI 0 0 0 • 1 • RF R Counter Division Ratio Division Ratio: 2 (fixed value. Note it is not programmable.) 17 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Programmable Counter (N CoUnter) If the control bits are 01(IF), 10, and 11(RF), data is transferred from the 24-bit shift register into the N/Frac-latch. N Counter consists of swallow counter (A counter; 3-bit for IF & S1M8831A RF and 4-bit for S1M8833), main counter (B counter; 7-bit for S1M8831A/33 RF and 12-bit for IF), and fractional counter (F counter; 17-bit for S1M8831A/33 RF). Serial data format is shown below. IF N Counter MSB TEST OSC IF_CTL_ WORD [21:19] IF_CP-WORD [18:17] IF_N[23:0] IF_NB_CNTR[16:5] ; 3 - 4095 IF_NA_CNTR [4:2] ; 0 - 7 0 LSB 1 23 22 21 19 18 17 16 Division Ratio of the IF N Counter 54 21 0 Program Code Control Bits • IF Main Counter Division Ratio (B Counter) IF_NB_ CNTR[16:5] ; for S1M8831A/33 Division Ratio(B) 3 4 • 4095 N 11 0 0 • 1 N 10 0 0 • 1 N 9 0 0 • 1 N 8 0 0 • 1 N 7 0 0 • 1 N 6 0 0 • 1 N 5 0 0 • 1 N 4 0 0 • 1 N 3 0 0 • 1 N 2 0 1 • 1 N 1 1 0 • 1 N 0 1 0 • 1 Division Ratio: 3 to 4095 (The division ratios less than 3 are prohibited) • Swallow Counter Division Ratio (A Counter) IF_NA_CNTR[4:2] ; for S1M8831A/33 Division Ratio(A) 0 1 • 7 Division Ratio: 0 to 7 (B > A) N 2 0 0 • 1 N 1 0 0 • 1 N 0 0 1 • 1 18 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 RF N Counter MSB RF_CTL_WORD [23:21] CMOS[20:18] RF_CP_WORD [17:13] RF_N[23:0] RF_NB_CNTR[12:16] ; 3 - 127 FoLD[5:2] 1 LSB 0 23 21 20 18 17 13 12 Division Ratio of the RF N Counter 65 21 0 Program Code Control Bits RF_Frac[23:0] RF_NA_CNTR [23:20] TEST FRAC_CNTR[18:2] 1 1 • RF Main Counter Division Ratio (B Counter) RF_NB_ CNTR[12:6] ; for S1M8831A/33 Division Ratio(B) 3 4 • 127 N 6 0 0 • 1 N 5 0 0 • 1 N 4 0 0 • 1 N 3 0 0 • 1 N 2 0 1 • 1 N 1 1 0 • 1 N 0 1 0 • 1 Division Ratio: 3 to 127 (The division ratios less than 3 are prohibited) • RF Swallow Counter Division Ratio (A Counter) RF_NA_CNTR[23:20] ; for S1M8831A Division Ratio(A) 0 1 • 7 N 3 x x • x N 2 0 0 • 1 N 1 0 0 • 1 N 0 0 1 • 1 0 1 • 15 RF_NA_CNTR[23:20] ; for S1M8833 Division Ration(A) N 3 0 0 • 1 N 2 0 0 • 1 N 1 0 0 • 1 N 0 0 1 • 1 Division Ratio: 0 to 7 (B > A) x = Don' t care condition Division Ratio: 0 to 15 (B > A) 19 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL RF Fractional Counter MSB RF_NA_CNTR [23:20] 23 TEST 20 19 Program Code 18 RF_Frac[23:0] FRAC_CNTR[18:2] 1 21 Division Ratio of the RF Fractional Counter Control Bits LSB 1 0 • RF Fractional Counter Value (F Counter) FRAC_ CNTR[18:2] ; for S1M8831A/33 RF Counter Value(F) 31488 • 2 1 0 -1 -2 • -31488 F 16 0 • 0 0 0 1 1 • 1 F 15 0 • 0 0 0 1 1 • 1 F 14 1 • 0 0 0 1 1 • 0 F 13 1 • 0 0 0 1 1 • 0 F 12 1 • 0 0 0 1 1 • 0 F 11 1 • 0 0 0 1 1 • 0 F 10 0 • 0 0 0 1 1 • 1 F 9 1 • 0 0 0 1 1 • 0 F 8 1 • 0 0 0 1 1 • 1 F 7 0 • 0 0 0 1 1 • 0 F 6 0 • 0 0 0 1 1 • 0 F 5 0 • 0 0 0 1 1 • 0 F 4 0 • 0 0 0 1 1 • 0 F 3 0 • 0 0 0 1 1 • 0 F 2 0 • 0 0 0 1 1 • 0 F 1 0 • 1 0 0 1 1 • 0 F 0 0 • 0 1 0 1 0 • 0 F Counter Value: -31488(2's complementary) to 31488 NOTE: For a negative integer, the counter value should be inputted as the corresponding 2's complementary binary code. For instance, the 2's complementary binary code of -2 is 1 1111 1111 1111 1110. 20 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Programmable PFD and Charge Pump IF Charge Pump Gain (IF_CP_WORD; IF_N[18]) Control Words IF_CP_WORD Control Bits IF_N[18] Acronym IF_CP_GAIN LOW (0) 1X (100uA) HIGH (1) 8X (800uA) Comments IF charge pump RF Charge Pump Gain (RF_CP_WORD; RF_N[17:14]) Control Words RF_CP_WORD Control Bits RF_N[17:14] Acronym RF_CP_LVL LOW (0) HIGH (1) Comments RF charge pump Select 16-level charge pump current Icpo (uA) 50 100 • 200 250 • 400 450 • 800 8X RF_N[17] 0 0 • 0 0 • 0 1 • 1 4X RF_N[16] 0 0 • 0 1 • 1 0 • 1 2X RF_N[15] 0 0 • 1 0 • 1 0 • 1 1X RF_N[14] 0 1 • 1 0 • 1 0 • 1 21 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Phase Detector Polarity (RF_CP_WORD/IF_CP_WORD; RF_N[13]/IF_N[17]) Depending on VCO characteristics, IF_N[17] and RF_N[13] bits should be set as follows: Control Bits IF_N[17] RF_N[13] LOW (0) Negative Slope Negative Slope HIGH (1) Positive Slope Positive Slope Comments IF PFD RF PFD VCO Characteristics (1) VCO Output Frequency (2) VCO Input Voltage 22 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Program Mode Control Power Down Mode Operation Control Words IF_CTL_WORD Control bits IF_N[20] IF_N[19] RF_CTL_WORD RF_N[22] Acronym PWDN_IF PWDN PWDN_RF LOW (0) Power Up Asynchronous Power Down Power Up HIGH (1) Power Down Synchronous Power Down Power Down Comments IF RF and IF RF Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits (PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the program control bits determine the state of power control. Power down forces all the internal analog blocks to be deactivated and the charge pump output to be in a TRISTATE. The oscillator circuitry function becomes disabled dependent on the state of IF and RF power-down bits, IF_N[20] and RF_N[22]. The RF(or IF) oscillator buffer is powered down when the power down bit (RF_N[22] or IF_N[20]) becomes HIGH. The control register and R/N counters, however, remains active for permitting serial programming and is capable of loading and latching in data during the power down. The PLL returns to the active power-up mode when IF_N[20] and RF_N[22] become LOW. There are synchronous and asynchronous power-down modes for S1M8831A/33. The power-down bit IF_N[19] is used to select between synchronous and asynchronous power down. Synchronous power down mode occurs if IF_N[19] bit is HIGH and then the power down bit (RF_N[22] or IF_N[20]) becomes HIGH. In the synchronous power down mode, the power-down function will go into power down mode upon the completion of a charge pump pulse event because it is synchronized with the charge pump and thus can diminish undesired frequency jumps. Asynchronous power down mode occurs if IF_N[19] bit is LOW and then the power down bit (RF_N[22] or IF_N[20]) becomes HIGH. Activation of the asynchronous function will go into power-down mode immediately. RF Power Down Mode Table RF_N[22] 0 0 1 1 IF Power Down Mode Table IF_N[20] 0 0 1 1 IF_N[19] 0 1 0 1 IF PLL active IF PLL active, only charge pump to TRISTATE Asynchronous power down Synchronous power down Power Down Mode Status IF_N[19] 0 1 0 1 RF PLL active RF PLL active, only charge pump to TRISTATE Asynchronous power down Synchronous power down Power Down Mode Status 23 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Reference Oscillator Input Control Control Words OSC Control bits IF_N[22] Acronym OSC LOW (0) separate inputs; OSCin: for IF, OSCx: for RF HIGH (1) common input through OSCin for both RF and IF Comments reference oscillator input control The reference oscillator frequency is provided from an external reference such as TCXO through the OSCin and OSCx pins. When the OSC bit is LOW, the oscillator input pins( OSCin and OSCx) drive the IF R and RF R counters separately. When the OSC bit is HIGH, on the other hand, the oscillator input pin OSCin drives the IF R and RF R counters commonly. IF_N[22] = LOW PWDN_IF IF_N[20] 0 0 1 1 PWDN_RF RF_N[22] 0 1 0 1 OSCin OSCin LOW(powerdown) LOW(powerdown) OSCx LOW(powerdown) OSCx LOW(powerdown) IF RF IF_N[22] = HIGH PWDN_IF IF_N[20] 0 0 1 1 PWDN_RF RF_N[22] 0 1 0 1 OSCin OSCin LOW(powerdown) LOW(powerdown) OSCin LOW(powerdown) OSCin LOW(powerdown) IF RF 24 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Programmable Counter Reset Control Control Words IF_CTL_WORD RF_CTL_WORD Control Bits IF_N[21] RF_N[23] Acronym IF_CNT_RST RF_CNT_RST LOW (0) Normal Operation Normal Operation HIGH (1) IF Counter Reset RF Counter Reset Comments IF RF Counter Reset Mode Resets R & N Counters. RF Fractional-N Selection Control Words RF_CTL_WORD Control Bits RF_N[21] Acronym Frac-N_SEL LOW (0) Reserved HIGH (1) Fractional-N Mode Comments RF; PLL Mode Selection CMOS Output Control Control Words CMOS Control Bits RF_N[20] RF_N[19] RF_N[18] Acronym Speedy Lock OUT1 OUT0 LOW (0) CMOS Output Voltage LOW Voltage LOW HIGH (1) Speedy Lock Mode Voltage HIGH Voltage HIGH Pin #23 Pin #24 Comments In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and a tri-state. The Speedy Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a low impedance ( < 150Ω) while a high charge pump gain ( ≥ 8X) is selected and otherwise to a tri-state. For using a programmable CMOS output, the CMOS output bit(RF_N[20] = LOW) should be activated and then the desired logic level should be programmed with the control bits RF_N[18] for OUT0 and RF_N[19] for OUT1. 25 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL foLD Control Control Words foLD Control Bits RF_N[5:2] Acronym foLD LOW (0) HIGH (1) Comments Lock Detector(LD), Test Mode Select LDs and monitoring mode of internal counters. foLD[3] 0 0 0 0 X X X X 1 1 1 1 foLD[2] 0 0 0 0 1 1 1 1 0 0 0 0 foLD[1] 0 0 1 1 0 0 1 1 0 0 1 1 foLD[0] 0 1 0 1 0 1 0 1 0 1 0 1 foLD Output State Disabled (default LOW) RF and IF analog lock detect Reserved test mode Reserved test mode Reserved test mode IF R counter output IF N counter output RF R counter output RF N counter output Reserved test mode Reserved test mode Reserved test mode — When the PLL is locked and the analog lock detect mode is selected, the foLD output is HIGH, with narrow pulses LOW. Lock Detector (LD) There is analog mode for S1M8831A/33. The foLD bits, RF_N[5:2], are used to select the lock detection mode and to output the selected lock signal through the foLD pin. The foLD output becomes HIGH with narrow pulsed LOW while both RF and IF PLLs are locked and thereby the output should be low-pass filtered for a DC locked voltage HIGH. 26 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Pulse Swallow Function The RF VCO's frequency fVCO becomes NINT + NFRAC times the comparison frequency (fOSC/R) where NINT is the integer divide ratio and NFRAC is the fractional component; fVCO = (NINT + NFRAC) × fOSC/R = N × fOSC/R where NINT = (P × B) + A, RF PLL: NFRAC = F/62976, -31488 ≤ F ≤ 31488, B > P, and R = 2 IF PLL: NFRAC = 0, B > A, and 3 ≤ R ≤ 32767 f VCO : External VCO output frequency f OSC : External reference frequency (From external oscillator) R : Preset divide ratio of programmable R counter (RF: 2, IF: 3 to 32767); P : Preset modulus of dual modulus prescaler (S1M8831 RF: P=8, S1M8833 RF: P=16, IF: P=8) B : Preset value of main counter (S1M8831A/33 RF: 3 to 126, IF: 3 to 4095) A : Preset value of swallow counter division ratio (S1M8831 RF: 0 ≤ A ≤ 7, S1M8833 RF: 0 ≤ A ≤ 15, IF: 0 ≤ A ≤ 7, A < B) NFRAC : Fractional component of Pulse-swallowed division ratio N (for IF: NFRAC = 0) F : Preset value of fractional register (-31488 ≤ F ≤ 31488); For a negative integer, F should be inputted as its 2's complementary binary code. For examples in S1M8831 fractional-N mode (fOSC = 19.68MHz, R=2, P=8) 1) for fvco = 955.02MHz 0000) 2) for fvco = 955.03MHz 3) for fvco = 956.25MHz 4) for fvco = 979.35MHz ; N = 97.05487805, B=12, A=1, F=3456 (= 0 0000 1101 1000 ; N = 97.05589431, B=12, A=1, F=3520 ; N = 97.17987805, B=12, A=1, F=11328 ; N = 99.52743902, B=12, A=4, F=-29760 ∴ F= 0.52743903 X 62976 = 33125 → 33125 > 31488 (A=3+1=4) = 33215 – 62976 = -29760 (1 1000 1011 1100 0000) For examples in S1M8833 fractional-N mode (fOSC = 19.68MHz, R=2, P=16) 1) for fvco = 1620.87MHz(CH25) 2) for fvco = 1620.88MHz 3) for fvco = 1622.12MHz(CH50) 4) for fvco = 1632.12MHz(CH250) 5) for fvco = 1648.37MHz(CH575) ; N = 164.722561, B=10, A=5, F=-17472 (= 1 1011 1011 1100 0000) ; N = 164.7235772, B=10, A=5, F=-17408 ; N = 164.8495935, B=10, A=5, F=-9472 ; N = 165.8658537, B=10, A=6, F=-8448 ; N = 167.5172764, B=10, A=8, F=-30400 27 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Serial Data Input Timing MSB DATA DATA[23] DATA[22] DATA[10] DATA[9] CTL[1] LSB CTL[0] CLOCK tDS LE tDH tCLE tCWL tCWH tLEW Phase Detector and Charge Pump Characteristics Phase difference detection range: -2π to +2π When the positive-slope polarity of PFD is selected, IF_N[17] = HIGH or RF_N[13] = HIGH; fr fp LD CPo fr > fp fr = fp fr < fp fr < fp fr < fp 28 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 SIMPLIFIED SCHEMATIC DIAGRAM FOR RF SENSITIVITY TEST 2.7V to 4.0V RF Signal Generator 50Ω Microstrip 100pF 10dB ATTN 51Ω VDD fin fin S1M8831A /33 LE foLD DATA CLOCK PC Parallel Port VP 100pF 2.2µF 100pF 2.2µF 100pF OSCin Frequency Counter 12kΩ 39kΩ NOTES: 1. Sensitivity limit is determined when the error of the divided RF output (fOLD) becomes 10Hz. 2. fVCO = 1.0GHz, N = 1000, P = 8, R = 2 in S1M8831 Integer-N test mode fVCO = 1.6GHz, N = 1600, P = 16, R = 2 in 1M8833 Integer-N test mode 29 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL TYPICAL APPLICATION CIRCUIT VP R3 VCO 10pF RF Out Reference Input 1000pF 51Ω 10pF 100pF Rin 9 OSCin foLD 10 foLD 8 OSCx 7 GNDRF 6 finRF 5 finRF 4 DGND 3 CPORF 2 VPRF 1 VDDRF OUT0 24 22Ω C3 C2 R1 C1 100pF 0.01µ F 100pF 0.01µ F VDD 0.1µ F VDD 11 RF_EN S1M8831A/33 OUT1 23 0.1µ F 12 IF_EN CLCOK 13 From Controller DATA 14 LE 15 GNDIF 16 finIF 17 finIF 18 Rin 56pF IF Out 56pF DGND 19 CPOIF 20 VDDIF VPIF 21 22 22Ω VDD 100pF 0.01µ F 1000pF VP . CDMA : UCVA4X103A . K-PCS : UCVW4X102A . US-PCS : UCVA3X120A VCO C13 R13 100pF C12 R11 C11 0.01µ F NOTE: The role of Rin: Rin makes a large portion of VCO output power go to the load rather than the PLL. The value of Rin depends on the VCO power level. 30 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 PCB LAYOUT GUIDE In doing PCB layouts for S1M8831A/33, we recommend that you apply the following design guide to your handsets, thus improving the phase noise and reference spurious performances of the phones. 1. The S1M8831A/33 has external four power supply pins to supply on-chip bias, each for analog and digital blocks of RF and IF PLLs. Basically in doing PCB layout, it is important that power supply lines should be separated from one another and thus coupling noises through the voltage supply lines can be minimized. If you have some troubles with the direction to separate, you can choose the following recommendations for your convenience; • • Tying analog power lines, VCCRF and VCCIF, is possible. Tying digital power lines, VP1 and VP2, is possible. • A point connecting the analog and digital power lines should be near to battery line as close as possible. It minimizes coupling noise effects from a digital switching noise into analog blocks. We also recommend that a passive RC low pass filter (R(22Ω), C(100nF)) be utilized for suppressing high frequency noise on the analog power supply line and reducing any digital noise couplings. 2. VCO power lines should be well separated from those of PLL because VCO is generally a very sensitive device from power line noises and PLL is a digital noise generator. 3. For more improvement of reference spurious performance, it is recommended that the LPF ground be tied to the PLL ground, not the VCO ground. 31 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL PACKAGE DIMENSIONS 1.00MAX #1 INDEX AREA 0.27 + 0.05 0.70 + 0.05 4.50 + 0.10 B 3.50 + 0.10 A 0.08 C C (0.05) (0.05) 4X0.50 + 0.10 #24 #1 2X4.00 #1 ID MARK 2X 0.10 20X0.50 2X 0.10 C 2X1.00 0.10 M CB CS 24X0.30 + 0.05 C 32