S1T8825X01-R0B0

PRELIMINARY ( VER.2.1 ) 1.1GHZ DUAL PLL S1T8825 INTRODUCTION The S1T8825 is a high performance dual frequency synthesizer with two integrated high frequency pre-scalers for RF operation up to 1.1 GHz. The S1T8825 is composed of modulus pre-scalers providing 64 and 66, no dead-zone PFD, selectable charge pump current, selectable power down mode circuits, lock detector output, and loop filter’s time constant switch. It is fabricated using the ASP5HB Bi-CMOS process and is available 16-TSSOP with surface mount plastic packaging. Serial data is transferred into the S1T8825 via three-wire interface (CK, DATA, EN). 16−TSSOP−0044 FEATURES • • • Two systems for receiver and transmitter Very low operating current consumption: Icc = Typ. 5.5mA @ 3.0V Low operating power supply voltage : 2.2 ~ 5.5V ( 200MHz ~ 550MHz Operating ) 2.7 ~ 3.6V ( 550MHz ~ 1.1GHz Operating ) • • • • • • Modulus pre-scaler: 64 / 66 No dead-zone PFD Colpitts type local oscillation Selectable charge pump current Selectable power down mode TSSOP 16-pin package (0.65 mm pitch) ORDERING INFORMATION Device +S1T8825X01-R0B0 +: New Product Package 16−TSSOP−0044 Operating Temperature −30 °C to + 85 °C APPLICATIONS • • • • Cordless telephone systems Portable wireless communications (PCS) Wireless Local Area Networks (WLANs) Other wireless communication systems 1 PRELINIMARY( VER.2.1 ) S1T8825 1.1GHZ DUAL PLL BLOCK DIAGRAM Fin1 1 Pre_Amp 1/2 Prescaler 1 32, 33 Buffer Prescaler 1 32, 33 Buffer 1/2 Pre_Amp 16 Fin2 VCC 2 Charge Pump Phase Detector Lock Detector 6 2 15 VCC 2 Charge Pump Phase Detector Switch 14 CP2 13 GND CP1 3 GND 4 Channel 1 Programable Divider Channel 2 Programable Divider LD 5 12 SW CK 6 Control Circuit Reference Divider Local OSC 1/2 Buffer 11 OSCI DATA 7 10 OSCO 17 12 EN 8 9 BO PIN CONFIGURATION Fin1 VCC CP1 GND LD CK DATA EN 1 2 3 4 5 6 7 8 16 15 14 13 Fin2 VCC CP2 GND SW OSCI OSCO BO KB8825 S1T8825 12 11 10 9 16TSSOP 2 PRELIMINARY ( VER.2.1 ) 1.1GHZ DUAL PLL S1T8825 PIN DESCRIPTION Pin No. 1 2, 15 3 4, 13 5 6 7 8 9 10 11 12 14 16 Symbol Fin1 Vcc CP1 GND LD CK DATA EN BO OSCO OSCI SW CP2 Fin2 I/O I − O − O I I I O O I O 0 I Description Input terminal of channel 1 RF signal. Power supply voltage input. PIN2 and PIN15 are connected together. Output terminal of channel 1 charge pump. Charge pump is constant current output circuit, and output current is selected by input serial data. Terminal of GND. PIN4 and PIN13 are connected together. Output terminal of lock detection. It is the open drain output. Input terminal of clock. Input terminal of data. Input terminal of enable signal. Output terminal of buffer amplifier. The signal of local oscillation is output through the buffer amplifier. Output terminal of local oscillation signal. Input terminal of local oscillation signal. In case of external input, connecting it to this terminal. Switch-over terminal for the time constant of loop filter. It is an open drain output. If you don’t switch the time constant of loop filter, general output is available. Output terminal of channel 2 charge pump. Charge pump is a constant current output circuit, and the output current is selected by input serial data. Input terminal of channel 2 RF signal. ABSOLUTE MAXIMUM RATINGS Characteristic Power Supply Voltage Power Dissipation Operating temperature Storage temperature Take care ! ESD sensitive device Symbol Vcc PD TOPR TSTG Value 6 600 −30 — + 85 −55 — + 50 1 Unit V mW °C °C 3 PRELINIMARY( VER.2.1 ) S1T8825 1.1GHZ DUAL PLL ELECTRICAL CHARACTERISTICS (Ta = 25°C, VCC = 3V, unless otherwise specified) Characteristic Operating power supply voltage Operating current consumption Standby current Fin operating frequency Symbol VCC ICC ISB Fin Test Conditions Fin1=Fin2= 200MHz ~ 550MHz Fin1=Fin2= 550MHz ~ 1.1GHz Fin1=Fin2=1.1GHz/ -5dBm input Standby mode Fin1 = Fin2 = − 5dBm Vcc=2.2V Fin1 = Fin2 = 200MHz Vcc=3.0V Vcc=5.5V Vcc=2.2V Fin input sensitivity Fin Fin1 = Fin2 = 550MHz Vcc=3.0V Vcc=5.5V Vcc=2.7V Fin1 = Fin2 = 1.1GHz OSCI operating frequency Fosc Vcc=3.0V Vcc=3.6V VFin = 0dBm, sinewave Vcc = 2.2V fosc = 10MHz OSCI input voltage Vosc fosc = 20MHz Vcc = 3.0V Vcc = 5.5V Vcc = 2.2V Vcc = 3.0V Vcc = 5.5V Serial data input high voltage (CK, DATA, EN) Serial data input low voltage (CK, DATA, EN) Charge pump output current VIH VIL ICP1 ICP2 ICP3 ICP4 Charge pump leakage ICPL VCC = 2.2 to 5.5V VCC = 2.2 to 5.5V CP1 = 0, CP2 = 0 CP1 = 1, CP2 = 0 CP1 = 0, CP2 = 1 CP1 = 1, CP2 = 1 VCP = 1.5 V VCP = 1.5V VCP = 1.5V VCP = 1.5V Min. 2.2 2.7 3.5 − 200 − 15 − 15 − 10 −15 −15 − 10 − 10 − 10 − 10 5 − 10 − 10 0 − 10 − 10 −5 VCC − 0.4 − – – − − −1 Typ. 3.0 3.0 5.5 0 − − − − − − − − − − 0 0 0 0 0 − − ± 100 ± 200 ± 400 ± 800 − Max. 5.5 3.6 7.5 10 1100 0 0 0 0 0 0 0 0 0 25 5 5 5 5 5 5 0.4 − − − − +1 V V µA µA µA µA µA dBm MHz dBm Unit V V mA µA MHz Standby mode, Vcp = 1.5V 4 PRELIMINARY ( VER.2.1 ) 1.1GHZ DUAL PLL S1T8825 FUNCTIONAL DESCRIPTIONS SERIAL DATA INPUT AND TIMING CK (Pin6), DATA (Pin7), EN (Pin8) terminals in S1T8825 are used for MCU serial data interface (MSB: 1st input data; LSB: Last input data). Serial data controls the programmable reference divider, programmable divider (CH1), programmable divider (CH2), and control latch separately by means of group code. Binary serial data is entered via the DATA pin. One bit of data is shifted into the internal shift register on the rising edge of the clock. When EN pin is high, stored data is latched. The three terminals, CK, DATA, and EN, contain Schmitt trigger circuits to keep the data from errors caused by noise, etc. < Notice > 1. When power supply of S1T8825 is disconnected, CLK, DATA, EN port from MCU should be pulled low. 2. When power goes up first, R counter data should be entered earlier than N1 and N2 counter data. 3. When power goes up first, control data should be entered earlier than N1 and N2 counter data. ≥ 1us ≥ 0.2us ≥ 0.2us CK DATA MSB N1 (R1) ≥ 0.2us ≥ N2 (R2) N3 (R3) N16 (R11) N17 (R12) GC2 LSB GC1 MSB ≥ 0.1us EN ≥0.1us ≥ 0.2us ≥ 0.2us Figure 1. NOTE: Start data input with MSB first SERIAL DATA GROUP AND GROUP CODE The S1T8825 can be controlled through 4 kinds of group selection. Each group is identified by selective a 2-bit group code given below. Serial Bits GC1 (LSB) 0 0 1 1 GC2 (LSB-1) 0 1 0 1 Control Latch Ch 1 N Latch Ch 2 N Latch OSC R Latch Group Location 5 PRELINIMARY( VER.2.1 ) S1T8825 1.1GHZ DUAL PLL CONTROL LATCH The control register executes the following functions: • • • • • Mode selection (H: test mode, L: normal mode) Charge pump’s polarity and output current selection for each channel. Output state selection for Lock Detector. Standby control of each channel and reference divider. ON / OFF control in filter switch. MSB CH1 CH2 GC2 "0" LSB GC1 "0" T CP CP1 CP2 SB1 CP1 CP2 SB2 SBR LD1 LD2 SW Group Code Figure 2. Bit Name Description Bit 1 T test mode Bit 2 CP charge pump output polarity Bit 3 CP1 channel 1 charge pump output current Bit 4 CP2 channel 1 charge pump output current Bit 5 SB1 channel 1 standby Bit 6 CP1 channel 2 charge pump output current Bit 7 CP2 channel 2 charge pump output current Bit Name Description Bit 8 SB2 channel 2 standby Bit 9 SBR reference divider standby Bit 10 LD1 lock detector control 1 Bit 11 LD2 lock detector control 2 Bit 12 SW filter switch Bit 13 GC2 group code “ 0” Bit 14 GC1 group code “0” 6 PRELIMINARY ( VER.2.1 ) 1.1GHZ DUAL PLL S1T8825 CHARGE PUMP OUTPUT POLARITY (CP) In normal operation, the CP should be “0”. In reverse operation, the CP should be “1”. Depending upon VCO characteristics, CP should be set accordingly; When VCO characteristics are like (1), CP should be set to low When VCO characteristics are like (2), CP should be set to high. VCO Characteristics (1) VCO Output Frequency (2) VCO Input Voltage CHARGE PUMP OUTPUT CURRENT (CP1, CP2) The S1T8825 includes a constant current output type charge pump circuit. Output current is varied according to control bit “CP1” and “CP2”. In order to get high speed lock-up, select the best charge pump output current. Control Bit CP1 0 0 1 1 CP2 0 1 0 1 Charge Pump Output Current ± 100 µA ± 200 µA ± 400 µA ± 800 µA 7 PRELINIMARY( VER.2.1 ) S1T8825 1.1GHZ DUAL PLL TEST MODE AND LOCK DETECTOR OUTPUT (T, LD1, LD2) When T is normal “0”, LD (Pin5) state is varied by controlling “SB1”, “SB2”, “LD1” and “LD2”. When T is high “1”, LD (Pin5) state is changed to be useful for test T SB1 SB2 LD1 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 1 0 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 1 0 1 0 × × LD2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 × × LD Output State low channel2 channel1 channel1. AND. channel2 low high channel1 channel1 low channel2 high channel2 low high high high low pres2 fpll2 fref div4 pres1 fpll1 fosc/2 low low 8 PRELIMINARY ( VER.2.1 ) 1.1GHZ DUAL PLL S1T8825 LOCK DETECTOR OUTPUT When the phase comparator detects a phase difference, LD (Pin5) outputs “L”. When the phase comparator locks, LD outputs “H”. On standby, it outputs “H”. When T is less than 2/fosc (T