S3C2800

S3C2800 32-BIT RISC MICROPROCESSOR DATA SHEET Revision 1.0 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product. S3C2800 32-Bit Microprocessor Data Sheet, Revision 1.0 Publication Number: 11.0-S3-C2800-072002 © 2002 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Lee, Giheung-Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(31)-209-6530 FAX: (82)-(31)-209-6547 Home-Page URL: Http://www.samsungsemi.com Printed in the Republic of Korea S3C2800 32-Bit RISC Microprocessor Data Sheet OVERVIEW SAMSUNG's S3C2800 32-bit RISC microprocessor is designed to provide a cost-effective and high-performance micro-controller solution for general applications. The S3C2800 features the following integrated on-chip support to help design a system a low cost: 16KB I/D caches, 2-ch UART with handshake, 4-ch DMA, memory controller, 3-ch timer, GPIO (General-Purpose Input/Output) ports, RTC (Real Time Clock), 2-ch IIC-BUS interface, and a built-in PLL for system clock. Based on ARM920T core, the S3C2800 is developed using 0.18 um CMOS standard cells and a memory compiler. Its simple, elegant, and fully static low-power design is particularly suitable for both cost-sensitive and power-sensitive applications. The 32-bit ARM920T RISC processor core (220Mips @200MHz), designed by Advanced RISC Machines, Ltd., provides architectural enhancements such as the Thumb de-compressor, a 32bit hardware multiplier, and an on-chip ICE debug support. Also, the S3C2800 features the Harvard BUS architecture for efficient data/instruction transfers. By integrating various common system peripherals, the S3C2800 minimizes the overall system cost and eliminates the need to configure additional components. The integrated on-chip functions are summarized as follows : • • • • • • • • • • • • PCI BUS interface (32-bit, up to 66MHz). 1.8V static ARM920T CPU core with 16KB I/D (Instruction/Data) cache. (Harvard bus architecture up to 200MHz). External memory controller. (FP/EDO/SDRAM control, Chip select logic). 4-ch general DMAs with external request pins. 2-ch UART with handshake (IRDA1.0, 16-byte FIFO), Modem Interface. 2-ch multi-master IIC-BUS controller. 3-ch 16-bit timer. 16-bit Watchdog timer. 44 general-purpose GPIO ports including 8 external interrupt source. Power management: Normal, Slow, and Idle modes. RTC with calendar function. On-chip PLL clock generator. S3C2800 MICROCONTROLLER DATA SHEET FEATURES Architecture · • • • • algorithm • • • Little-/Big-endian support for external memory. Address space: 32Mbytes per each bank (Total 256Mbyte) Supports programmable 8/16/32-bit data bus width for each memory bank Fixed bank start address for all (static memory and dynamic memory banks) 8 memory banks – 4 memory banks for static memory (ROM, SRAM, FLASH etc) – 4 memory banks for dynamic memory (Fast Page, EDO, and Synchronous DRAM) Fully programmable access cycles for all static memory banks Supports external wait signal to extend the bus cycle Supports self-refresh mode in DRAM/SDRAM. Supports asymmetric/symmetric address of DRAM Write-through and Write-back cache operation. The write buffer can hold 16 words of data and 4 addresses Low voltage cache for reduced power consumption Clock & Power Manager • The on-chip PLL generates the necessary clock for the operation of MCU at maximum of 200MHz@1.8V Input frequency range: (Fin) = 6MHz – 10MHz. Output frequency range: (FCLK) = 20MHz – 200MHz Clock can be selectively provided to each function block by software Power Down Mode: NORMAL, SLOW, and IDLE mode – NORMAL mode: Normal operating mode – SLOW mode: Low frequency clock without PLL – IDLE mode: Clock to CPU is disabled • • • • • • • • I/D (Instruction/Data) Cache Memory • • • 64-way set-associative ICache (16KB) and DCache (16KB) 8 words per line with one valid bit and 2 dirty bits per line Pseudo-random or round-robin replacement PCI Bus Interface • • Embedded PCI Host Bridge 32-bit data bus at 66MHz 2 DATA SHEET S3C2800 MICROCONTROLLER FEATURES (Continued) Interrupt Controller • UART • • • • • • • 34 Interrupt sources. (3 for Timers, 6 for UART, 8 for External interrupts, 4 for DMA, 2 for RTC, 2 for IIC, 2 for RCSR (Remote Control Signal Receiver), and 7 for PCI)) Software polling Interrupt mode Selectable level- or edge-triggered external interrupts source Programmable IRQ/FIQ for each interrupt request Supports FIQ (Fast Interrupt Request) for very urgent interrupt request 2-channel UART with DMA-based or interrupt based operation Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive Supports hardware handshaking during transmit/receive operation Programmable baud rates (up to 230.4Kbps). Supports IrDA 1.0 (up to 115.2Kbps) Loop back mode for testing Program accessible 16-byte FIFO (2x16 byte FIFO for transmit/receive data) • • • • Timer • DMA Controller • • 3-ch 16-bit Timer with DMA-based or interruptbased operation 4-channel general-purpose Direct Memory Access controller without CPU intervention. Support memory to memory, memory to I/O and I/O to I/O DMA operations of the following 6 types: Software, 3 internal function blocks (UART0, UART1, Timer), and 2 External requests Watchdog Timer • 16-bit Watchdog Timer RCSR (Remote Control Signal Receiver) • • 8-step FIFO FIFO interrupt is generated on full (8) step overflow • Burst transfer mode to enhance the transfer rate on the FPDRAM, EDODRAM and SDRAM IIC-BUS Interface • • RTC (Real Time Clock) • • • • Full clock feature: sec, min, hour, date, day, week, month, and year 32.768 kHz input clock Alarm interrupt Time tick interrupt 2-ch Multi-Master IIC-Bus with interrupt-based operation Serial, 8-bit oriented, bi-directional data transfers at up to 100 Kbit/s in the standard mode or up to 400 Kbit/s in the fast mode Operating Voltage Range • Core: 1.8 V -0.1 V/+0.15 V I/O: 3.3 V ± 0.3 V GPIO (General-Purpose Input/Output) Ports • • • 8 external interrupt ports 44 multiplexed input/output ports. Operating Frequency • Up to 200 MHz. Package • 208-pin LQFP 3 S3C2800 MICROCONTROLLER DATA SHEET BLOCK DIAGRAM JTAG DV2A[31:0] IV2 A[31:0] Data MMU DPA[31:0] ARM9TDMI Processor core (Integral EmbeddedICE) DVA[31:0] IVA[31:0] DD[31:0] ID[31:0] C13 C13 Instruction MMU IPA[31:0] Data cache Instruction cache CP15 Write back PA tag RAM Write buffer WBPA[31:0] External coproc interface AMBA bus Interface ASB ASB to AHB bus Bridge 4ch-GDMA Arbiter/Decode PCI Bridge Memory Controller BUS Controller Arbiter/Decode Interrupt Controller Clock(PLL) & Power Manage AHB BUS 32-bit AHB to APB Bridge AHB Watch-dog APB BUS 32-bit 2ch-IIC 2ch-IIC 2ch-IIC GPIO 2ch-IIC 2ch-UART 2ch-IIC 3ch-Timers RTC RMT Receive 2ch-IIC Figure 1. S3C2800 Block Diagram 4 PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER PIN DIAGRAM (208-LQFP) nSDCS2/nDRAS2/GPA4 nSDCS3/nDRAS3/GPA5 VDD3OP VSS3OP nDCAS0/GPA6 nDCAS1/GPA7 nDCAS2/nSDCAS/GPB0 nDCAS3/nSDRAS/GPB1 SDCKE SDCLK nBE0/nWBE0/DQM0/GPB2 nBE1/nWBE1/DQM1/GPB3 nBE2/nWBE2/DQM2/GPB4 nBE3/nWBE3/DQM3/GPB5 DATA16 ADDR16 DATA17 ADDR17 DATA18 ADDR18 VDD3OP VSS3OP DATA19 ADDR19 DATA20 ADDR20 VDD VSS DATA21 ADDR21 DATA22 ADDR22 DATA23 ADDR23 DATA24 ADDR24 DATA25 DATA26 DATA27 DATA28 VDD3OP VSS3OP DATA29 DATA30 DATA31 nOE nWE GPB6/nWAIT GPB7/CLKout GPC0 GPC1 GPC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 nSDCS1/nDRAS1/GPA3 nSDCS0/nDRAS0 nSCS3/GPA2 nSCS2/GPA1 nSCS1/GPA0 nSCS0 ADDR15 DATA15 ADDR14 DATA14 ADDR13 DATA13 ADDR12 DATA12 VSS3OP VDD3OP ADDR11 DATA11 ADDR10 DATA10 VSS VDD ADDR9 DATA9 ADDR8 DATA8 ADDR7 DATA7 ADDR6 DATA6 ADDR5 DATA5 ADDR4 DATA4 VSS3OP VDD3OP ADDR3 DATA3 ADDR2 DATA2 ADDR1 DATA1 ADDR0 DATA0 PCI_nINTA PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 VSS3OP PCI_AD5 S3C2800X 208-LQFP VDD/VSS : Internal 1.8V power AVDD/AVSS : Analog 1.8V Power VDD3OP/VSS3OP : I/O 3.3V power PCI_AD6 PCI_AD7 PCI_C0/nBE0 VDD3OP PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 VSS3OP PCI_AD15 PCI_C1/nBE1 PCI_PAR PCI_nSERR PCI_nPERR PCI_nLOCK PCI_nSTOP PCI_nDEVSEL PCI_nTRDY VDD3OP PCI_nIRDY PCI_nFRAME PCI_C2/nBE2 VSS3OP PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 VSS VDD PCI_AD22 PCI_AD23 PCI_IDSEL PCI_C3/nBE3 VSS3OP PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 VDD3OP PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_nREQx3 PCI_nREQx2 VSS3OP PCI_nREQ1 GPC3/ENDIAN nTRST TCK TMS TDI TDO IRIN GPD0/IICSDA0 GPD1/IICSCLK0 GPD2/IICSDA1 GPD3/IICSCLK1 GPD4/RxD0 GPD5/TxD0 GPD6/nCTS0 GPD7/nRTS0 nRESET_OUT GPE0/RxD1 GPE1/TxD1 GPE2/nCTS1 GPE3/nRTS1 VDD VSS GPE4/nXDREQ0 GPE5/nXDACK0 GPE6/nXDREQ1 GPE7/nXDACK1 GPF0/EXTINT0 GPF1/EXTINT1 GPF2/EXTINT2 GPF3/EXTINT3 GPF4/EXTINT4 GPF5/EXTINT5 GPF6/EXTINT6 GPF7/EXTINT7 VDD3OP VSS3OP XTAL0 EXTAL0 TEST nRESET XTAL1 EXTAL1 OM0 OM1 AVDD PLLCAP AVSS PCI_nRST PCI_CLK PCI_nGNT1 PCI_nGNTx2 PCI_nGNTx3 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Figure 2. S3C2800 Pin Assignment (208-LQFP) 5 S3C2800 MICROCONTROLLER DATA SHEET PIN ASSIGNMENTS Table 1. Pin Assignment Description I/O Type vdd1ih, vss3I vdd1ih_pci, vss3I_pci vdd1t_abb, vss1t_abb vdd3op, vss3op vdd3op_pci, vss3op_pci poar50_abb phsoscm16 phsosck17 Phis Phisu phob8 phob8sm phot8 phob12 phbsud4 phbsu50cd4sm phbsu50ct8sm phbsu50ct12sm ptipci ptopci ptbpci ptbdpci Descriptions 1.8V power/ground for internal logic 1.8V power/ground for analog circuitry 3.3V power/ground for external interface logic 1.8V analog output (A capacitor is connected between the pin and analog ground) Oscillator cell width enable and feedback resistor (6 M – 40 MHz) Oscillator cell width enable and feedback resistor (– 100 kHz) 3.3V interface LVCMOS schmitt trigger level input buffers 3.3V interface LVCMOS schmitt trigger level input buffers with 100 KΩ pull-up resistor. 3.3V LVCMOS normal output buffers, Io = 8 mA 3.3V LVCMOS normal output buffers with medium slew-rate, Io = 8 mA 3.3V LVCMOS tri-state output buffers, Io = 8 mA 3.3V LVCMOS normal output buffers, Io = 12 mA 3.3V open-drain bi-directional buffers with 100 KΩ pull-up resistor. Io=4mA 3.3V bi-directional pad, LVCMOS schmitt trigger, open-drain, 50 KΩ pull-up resistor with control, tri-state, Io = 4 mA 3.3V bi-directional pad, LVCMOS schmitt trigger, 50 KΩ pull-up resistor with control, tri-state, Io = 8 mA 3.3V bi-directional pad, LVCMOS schmitt trigger, 50 KΩ pull-up resistor with control, tri-state, Io = 12 mA 3.3V input buffer 3.3V output buffer with tri-state 3.3V bi-directional buffer with input and tri-state output 3.3V bi-directional buffer with input and open-drain output, tri-state NOTES: 1. ENDIAN value is latched only at the rising edge of nRESET: when nRESET is Low, the ENDIAN (GPC3) pin operates in input mode; nRESET becomes High, the ENDIAN pin will automatically switch to output mode. 2. IICSDA, IICSCLK, PCI_nSERR, and PCI_nINTA pins are of open-drain type. 3. AI/AO means analog input/output. 6 PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER Table 2. 208-Pin LQFP Pin Assignment Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin Name nSDCS2/nDRAS2/GPA4 nSDCS3/nDRAS3/GPA5 VDD3OP VSS3OP nDCAS0/GPA6 nDCAS1/GPA7 nDCAS2/nSDCAS/GPB0 nDCAS3/nSDRAS/GPB1 SDCKE SDCLK nBE0/nWBE0/DQM0/GPB2 nBE1/nWBE1/DQM1/GPB3 nBE2/nWBE2/DQM2/GPB4 nBE3/nWBE3/DQM3/GPB5 DATA16 ADDR16 DATA17 ADDR17 DATA18 ADDR18 VDD3OP VSS3OP DATA19 ADDR19 DATA20 ADDR20 VDD VSS DATA21 ADDR21 DATA22 ADDR22 DATA23 ADDR23 DATA24 Default Function nSDCS2 nSDCS3 VDD3OP VSS3OP nDCAS0 nDCAS1 nSDCAS nSDRAS SDCKE SDCLK DQM0 DQM1 DQM2 DQM3 DATA16 ADDR16 DATA17 ADDR17 DATA18 ADDR18 VDD3OP VSS3OP DATA19 ADDR19 DATA20 ADDR20 VDD VSS DATA21 ADDR21 DATA22 ADDR22 DATA23 ADDR23 DATA24 I/O State @Initial O/IO O/IO P P O/IO O/IO O/IO O/IO O O O/IO O/IO O/IO O/IO I/O O I/O O I/O O P P I/O O I/O O P P I/O O I/O O I/O O I/O phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 vdd3op vss3op phbsu50ct12sm phot8 phbsu50ct12sm phot8 vdd1ih vss3i phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phob8 phob12 phbsu50ct8sm vdd3op vss3op phbsu50ct8sm I/O TYPE phbsu50ct8sm 7 S3C2800 MICROCONTROLLER DATA SHEET Table 2. 208-Pin LQFP Pin Assignment (Continued) Pin # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 ADDR24 DATA25 DATA26 DATA27 DATA28 VDD3OP VSS3OP DATA29 DATA30 DATA31 nOE nWE GPB6/nWAIT GPB7/CLKout GPC0 GPC1 GPC2 GPC3/ENDIAN nTRST TCK TMS TDI TDO IRIN GPD0/IICSDA0 GPD1/IICSCLK0 GPD2/IICSDA1 GPD3/IICSCLK1 GPD4/RxD0 GPD5/TxD0 GPD6/nCTS0 GPD7/nRTS0 nRESET_OUT GPE0/RxD1 GPE1/TxD1 Pin Name Default Function ADDR24 DATA25 DATA26 DATA27 DATA28 VDD3OP VSS3OP DATA29 DATA30 DATA31 nOE nWE GPB6 GPB7 GPC0 GPC1 GPC2 ENDIAN nTRST TCK TMS TDI TDO IRIN GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 nRESET_OUT GPE0 GPE1 I/O State @Initial O I/O I/O I/O I/O P P I/O I/O I/O O O IO IO IO IO IO I(1) I I I I O I IO(2) IO(2) IO(2) IO(2) IO IO IO IO O IO IO phob8 phbsu50ct8sm phbsu50ct8sm phis phis phis phis phot8 phis phbsu50cd4sm phbsu50ct8sm phob8sm vdd3op vss3op phbsu50ct12sm I/O TYPE phot8 phbsu50ct12sm 8 PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER Table 2. 208-Pin LQFP Pin Assignment (Continued) Pin # 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Pin Name GPE2/nCTS1 GPE3/nRTS1 VDD VSS GPE4/nXDREQ0 GPE5/nXDACK0 GPE6/nXDREQ1 GPE7/nXDACK1 GPF0/EXTINT0 GPF1/EXTINT1 GPF2/EXTINT2 GPF3/EXTINT3 GPF4/EXTINT4 GPF5/EXTINT5 GPF6/EXTINT6 GPF7/EXTINT7 VDD3OP VSS3OP XTAL0 EXTAL0 TEST nRESET XTAL1 EXTAL1 OM0 OM1 AVDD PLLCAP AVSS PCI_nRST PCI_CLK PCI_nGNT1 PCI_nGNTx2 PCI_nGNTx3 PCI_nREQ1 Default Function GPE2 GPE3 VDD VSS GPE4 GPE5 GPE6 GPE7 GPF0 GPF1 GPF2 GPF3 GPF4 GPF5 GPF6 GPF7 VDD3OP VSS3OP XTAL0 EXTAL0 TEST nRESET XTAL1 EXTAL1 OM0 OM1 AVDD PLLCAP AVSS PCI_nRST PCI_CLK PCI_nGNT1 PCI_nGNTx2 PCI_nGNTx3 PCI_nREQ1 I/O State @Initial IO IO P P IO IO IO IO IO IO IO IO IO IO IO IO P P AI(3) AO(3) I I I O I(1) I(1) P AO(3) P I I IO O O IO ptbpci ptbpci ptopci vdd1t_abb poar50_abb vss1t_abb/vbb1_abb ptipci phis phis phisu phsosck17 vdd3op vss3op phsoscm16 vdd1ih vss3i phbsu50ct8sm I/O TYPE phbsu50ct8sm 9 S3C2800 MICROCONTROLLER DATA SHEET Table 2. 208-Pin LQFP Pin Assignment (Continued) Pin # 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 VSS3OP PCI_nREQx2 PCI_nREQx3 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 VDD3OP PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 VSS3OP PCI_C3/nBE3 PCI_IDSEL PCI_AD23 PCI_AD22 VDD VSS PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 VSS3OP PCI_C2/nBE2 PCI_nFRAME PCI_nIRDY VDD3OP PCI_nTRDY PCI_nDEVSEL PCI_nSTOP PCI_nLOCK PCI_nPERR Pin Name Default Function VSS3OP PCI_nREQx2 PCI_nREQx3 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 VDD3OP PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 VSS3OP PCI_C3/nBE3 PCI_IDSEL PCI_AD23 PCI_AD22 VDD VSS PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 VSS3OP PCI_C2/nBE2 PCI_nFRAME PCI_nIRDY VDD3OP PCI_nTRDY PCI_nDEVSEL PCI_nSTOP PCI_nLOCK I/O State @Initial P I I I/O I/O I/O I/O P I/O I/O I/O I/O P I/O I I/O I/O P P I/O I/O I/O I/O I/O I/O P I/O I/O I/O P I/O I/O I/O I ptipci ptbpci vdd3op_pci ptbpci vss3op_pci ptbpci vdd1ih_pci vss3i_pci ptb_pci vss3op_pci ptbpci ptipci ptbpci vdd3op_pci ptbpci ptbpci I/O TYPE vss3op_pci ptipci PCI_nPERR I/O Table 2. 208-Pin LQFP Pin Assignment (Continued) 10 PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER Pin # 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Pin Name PCI_nSERR PCI_PAR PCI_C1/nBE1 PCI_AD15 VSS3OP PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 VDD3OP PCI_C0/nBE0 PCI_AD7 PCI_AD6 PCI_AD5 VSS3OP PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PCI_nINTA DATA0 ADDR0 DATA1 ADDR1 DATA2 ADDR2 DATA3 ADDR3 VDD3OP VSS3OP DATA4 Default Function PCI_nSERR PCI_PAR PCI_C1/nBE1 PCI_AD15 VSS3OP PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 VDD3OP PCI_C0/nBE0 PCI_AD7 PCI_AD6 PCI_AD5 VSS3OP PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PCI_nINTA DATA0 ADDR0 DATA1 ADDR1 DATA2 ADDR2 DATA3 ADDR3 VDD3OP VSS3OP DATA4 I/O State @Initial I/O(2) I/O I/O I/O P I/O I/O I/O I/O I/O I/O I/O P I/O I/O I/O I/O P I/O I/O I/O I/O I/O I/O(2) I/O O I/O O I/O O I/O O P P I/O I/O TYPE ptbdpci ptbpci vss3op_pci ptbpci vdd3op_pci ptbpci vss3op_pci ptbpci phbsud4 phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 vdd3op vss3op phbsu50ct12sm 11 S3C2800 MICROCONTROLLER DATA SHEET Table 2. 208-Pin LQFP Pin Assignment (Continued) Pin # 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 ADDR4 DATA5 ADDR5 DATA6 ADDR6 DATA7 ADDR7 DATA8 ADDR8 DATA9 ADDR9 VDD VSS DATA10 ADDR10 DATA11 ADDR11 VDD3OP VSS3OP DATA12 ADDR12 DATA13 ADDR13 DATA14 ADDR14 DATA15 ADDR15 nSCS0 nSCS1/GPA0 nSCS2/GPA1 nSCS3/GPA2 nSDCS0/nDRAS0 nSDCS1/nDRAS1/GPA3 Pin Name Default Function ADDR4 DATA5 ADDR5 DATA6 ADDR6 DATA7 ADDR7 DATA8 ADDR8 DATA9 ADDR9 VDD VSS DATA10 ADDR10 DATA11 ADDR11 VDD3OP VSS3OP DATA12 ADDR12 DATA13 ADDR13 DATA14 ADDR14 DATA15 ADDR15 nSCS0 nSCS1 nSCS2 nSCS3 nSDCS0 nSDCS1 I/O State @Initial O I/O O I/O O I/O O I/O O I/O O P P I/O O I/O O P P I/O O I/O O I/O O I/O O O O/IO O/IO O/IO O O/IO I/O TYPE phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 vdd1ih vss3i phbsu50ct12sm phot8 phbsu50ct12sm phot8 vdd3op vss3op phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 phbsu50ct12sm phot8 phob8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phob8sm phbsu50ct8sm 12 PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER SIGNAL DESCRIPTIONS Table 3. S3C2800 Signal Descriptions Signal OM[1:0] I/O I Description OM [1:0] is used to determines the bus width of static memory bank0 (boot ROM). The pull-up/down resistor determines the logic level. 00 = 8-bit ADDR[24:0] DATA[31:0] nSCS[3:0] O IO O 01 = 16-bit 10 = 32-bit 11 = Not used ADDR [24:0] (Address Bus) outputs the memory address of the corresponding bank. DATA [31:0] (Data Bus) inputs data during memory read and outputs data during memory write. The bus width is programmable among 8/16/32-bit. nSCS[3:0] (Static memory bank Select) are activated when the address of a static memory is within the address region of each bank. The number of access cycles and the bank size can be programmed. nWE (Write Enable) indicates that the current bus cycle is a write cycle. Write Byte Enable. 16-bit SRAM Byte Enable. Request to prolong a current bus cycle. As long as nWAIT is Low, the current bus cycle can’t be completed. nOE (Output Enable) indicates that the current bus cycle is a read cycle. It determines whether or not the data type is Little-endian or Big-endian. The pullup/down resistor determines the logic level during the reset cycle. ENDIAN value is latched only at the rising edge of nRESET: when nRESET is Low, the ENDIAN (GPC3) pin operates in input mode; nRESET becomes High, the ENDIAN pin will automatically switch to output mode. 0 = Little-endian DRAM/SDRAM nDRAS[3:0] nDCAS[3:0] nSDRAS nSDCAS nSDCS[3:0] DQM[3:0] SDCLK SDCKE EXTINT[7:0] DMA nXDREQ[1:0] nXDACK[1:0] I O External DMA request. External DMA acknowledge. O O O O O O O O I Row Address Strobe. Column Address Strobe. SDRAM Row Address Strobe. SDRAM Column Address Strobe. SDRAM Chip Select. SDRAM Data Mask. SDRAM Clock (SDCLK = HCLK). SDRAM Clock Enable. External Interrupt request. 1 = Big-endian BUS CONTROLLER nWE nWBE[3:0] nBE[3:0] nWAIT nOE ENDIAN O O O I O I INTERRUPT CONTROL UNIT 13 S3C2800 MICROCONTROLLER DATA SHEET Table 3. S3C2800 Signal Descriptions (Continued) Signal UART RxD[1:0] TxD[1:0] nCTS[1:0] nRTS[1:0] IIC-BUS IICSDA[1:0] IICSCL[1:0] IRIN GPx[7:0] x 5 GPC[3:0] RESET & CLOCK nRESET ST nRESET suspends any operation in progress and places S3C2800 into a known reset state. For a reset, nRESET must be held to low level for at least 4 CPUCLK after the processor power is stabilized. The nRESET_OUT pin is asserted during hardware reset(POR,nRESET), software reset and watchdog reset. Crystal Input for internal OSC circuit for system clock. If it isn't used, XTAL0 has to be high level. IO IO I IO IIC-bus data. IIC-bus clock. Remote controller signal receive interrupt General-purpose input/output ports (GPA[7:0], GPB[7:0], GPC[3:0], GPD[7:0] , GPE[7:0], GPF[7:0]) I O I O UART receives data input. UART transmits data output. UART clear to send input signal. UART request to send output signal. I/O Description Remote Control Signal Input Interrupt GENERAL-PURPOSE I/O PORTs nRESET_OUT XTAL0 EXTAL0 PLLCAP XTAL1 EXTAL1 JTAG TEST LOGIC nTRST O AI AO Crystal output for internal OSC circuit for system clock. It is the inverted output of XTAL0. If it isn't used, it has to be a floating pin. AI AI Loop filter capacitor for system clocks PLL. (1uF ) 32 KHz crystal input for RTC. AO 32 KHz crystal output for RTC. It is the inverted output of XTAL1. I nTRST(TAP Controller Reset) resets the TAP controller at start. If debugger is used, A 10K pull-up resistor has to be connected. If debugger(black ICE) isn't used, nTRST pin has to be low level or low active pulse. TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's states. A 10K pull-up resistor has to be connected to TMS pin. TCK (TAP Controller Clock) provides the clock input for the JTAG logic. A 10K pull-up resistor has to be connected to TCK pin. TDI (TAP Controller Data Input) is the serial input for test instructions and data. A 10K pull-up resistor has to be connected to TDI pin. TDO (TAP Controller Data Output) is the serial output for test instructions and data. TMS TCK TDI TDO I I I O 14 PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER Table 3. S3C2800 Signal Descriptions (Continued) Signal POWER VDD VSS AVDD AVSS VDD3OP VSS3OP PCI-BUS PCI_AD[31:0] PCI_C[3:0]/ nBE[3:0] PCI_PAR I/O PCI Address/Data Bus. Multiplexed address and data bus. I/O PCI C (bus command) or Byte enables. I/O PCI-parity. Parity is even across PCI_AD[31:0] and PCI_C[3:0]/nBE[3:0]. PCI_PAR is valid one cycle after either an address or data phase. The PCI device that drives PCI_AD[31:0] is responsible for driving PCI_PAR on the next PCI bus clock. I/O PCI_nFRAME is driven by the current PCI bus master to indicate beginning and duration of a PCI access. I/O The target of the current PCI transaction drives PCI_nTRDY. Assertion of PCI_nTRDY indicates that the PCI target is ready to transfer data. I/O The current PCI bus master drives PCI_nIRDY. Assertion of PC_nIRDY indicates that the PCI initiator is ready to transfer data. I/O The target of the current PCI transaction may assert PCI_nSTOP to indicate to the requesting PCI master that it wants to end the current transaction. I/O The target of the current PCI transaction drives PCI_nDEVSEL. A PCI target asserts PCI_nDEVSEL when it decodes an address and command encoding, and claims the transaction. I PCI_IDSEL is used during configuration cycles to select the PCI slave interface for configuration. P P P P P P S3C2800 core logic VDD (1.8 V). S3C2800 core logic VSS. S3C2800 Analog logic (PLL loop filter) VDD(1.8V). S3C2800 Analog logic (PLL loop filter) VSS. S3C2800 GPIO port VDD (3.3 V). S3C2800 GPIO port VSS. I/O Description PCI_nFRAME PCI_nTRDY PCI_nIRDY PCI_nSTOP PCI_nDEVSEL PCI_IDSEL PCI_nPERR I/O PCI_nPERR is used for reporting data parity errors on PCI transactions. PCI_nPERR is driven active by the device receiving PCI_AD[31:0], PCI_C[3:0]/nBE[3:0], and PCI_PARITY, two PCI clocks following the data in which bad parity is detected. I/O PCI_nSERR is used for reporting address parity errors or catastrophic failures detected by a PCI target. PCI_nLOCK indicates an atomic operation to a bridge that may require multiple transactions to complet. When PCI_nLOCK is asserted, non-exclusive transactions may proceed to a bridge that is not currently locked. A grant to start a transaction on PCI does not guarantee a control of PCI_nLOCK. Locked transactions may be initiated only by the host bridges. I/O When internal arbiter is used, PCI_nREQ1 is input mode. or when external arbiter is used, PCI_nREQ1 is output mode. PCI_nSERR PCI_nLOCK PCI_nREQ1 15 S3C2800 MICROCONTROLLER DATA SHEET Table 3. S3C2800 Signal Descriptions (Continued) Signal PCI_nREQx[3:2] I/O I Description PCI_nREQx[3:2] input when internal arbiter is used. Request indicates to the arbiter that this agent desires use of the bus. This is a point-to-point signal. Every master has its own PCI_nREQx, which must be tri-stated, while PCI_nRST is asserted. When internal arbiter is used, PCI_nGNT1 is output mode. Or when external arbiter is used, PCI_nGNT1 is input mode. PCI_nGNTx[3:2] output when internal arbiter is used. Grant indicates to the agent that access to the bus has been granted. This is a point-to-point signal. Every master has its own PCI_nGNTx, which must be ignored while PCI-nRST is asserted. PCI_CLK is used as the asynchronous PCI clock. PCI specific reset PCI interrupt. PCI_nGNT1 PCI_nGNTx[3:2] I/O O PCI_CLK PCI_nRST PCI_nINTA I O O 16 PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 4. Absolute Maximum Rating Symbol VDD VDDP VIN VOUT Ilatch T STG Parameter 1.8V Core DC Supply Voltage 3.3V I/O DC Supply Voltage DC Input Voltage DC Output Voltage Latch-up Current Storage Temperature 3.3 V Input buffer 3.3 V Output buffer ± 200 – 65 to 150 Rating 2.4 3.8 3.8 3.8 Unit V V V V mA o C RECOMMENDED OPERATING CONDITIONS Table 5. Recommended Operating Conditions Symbol VDD VDDP VIN VOUT TOPR IDD Parameters 1.8V Core DC Supply Voltage 3.3V I/O DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature 1.8V core supply current 3.3V I/O supply current IDD1 1.8V core supply current 3.3V I/O supply current IDD2 Condition Commercial Commercial 3.3V Input buffer 3.3V Output buffer Commercial FCLK = 200MHz, VDD = 1.95V FCLK = 200MHz, VDDP = 3.6V FCLK = 200MHz, VDD = 1.95V FCLK = 200MHz, VDDP = 3.6V FCLK = 6MHz, VDD = 1.95V FCLK = 6MHz, VDDP = 3.6V Min 1.7 3.0 3.0 3.0 0 – – – – 210 75 75 15 Type 1.8 3.3 3.3 3.3 Max 1.95 3.6 3.6 3.6 70 300 110 mA 110 30 mA – – 15 5 30 10 Unit V V V V o C Normal operating current (FCLK : HCLK : PCLK = 1: 1/2 : 1/4) mA Idle mode current (FCLK : HCLK : PCLK = 1: 1/2 : 1/4) Slow mode current (FCLK : HCLK : PCLK = 1: 1/2 : 1/2) 1.8V core supply current 3.3V I/O supply current 17 S3C2800 MICROCONTROLLER DATA SHEET DC ELECTRICAL CHARACTERISTICS Table 6. Normal I/O PAD DC Electrical Characteristics (VDD = 1.8 V -0.1 V/+0.15 V, VDDP = 3.3 V ± 0.3 V, TOPR = 0 to 70 °C) Symbol VIH VIL VT VT+ VTIIH Parameters High level input voltage LVCMOS interface Low level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer IIL Low level input current Input buffer Input buffer with pull-up VOH High level output voltage Type B4 Type B8 Type B12 VOL Low level output voltage Type B4 Type B8 Type B12 CIN Input capacitance IOL = 4 mA IOL = 8 mA IOL = 12 mA Any Input and Bi-directional Buffers Any Output Buffers 0.4 0.4 0.4 4 pF IOH = -4 mA IOH = -8 mA IOH = -12 mA 2.4 2.4 2.4 V VIN = V SS -10 -120 -66 10 -20 V VIN = V DDP -10 10 µA CMOS CMOS 0.8 µA 1.4 2.0 0.8 V V 2.0 V Condition Min Type Max Unit V COUT Output capacitance 4 pF 18 PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER Table 7. PCI I/O PAD DC Electrical Characteristics (VDD = 1.8 V -0.1 V/+0.15 V, VDDP = 3.3 V ± 0.3 V, TOPR = 0 to 70 °C) Symbol VIH VIL II VOH VOL Parameters High level input voltage Low level input voltage Input Leakage Current High level output voltage Low level output voltage IOH = -500 µA IOL = 1500 µA Condition Min 0.47VDDP -0.5 -10 0.9VDDP 0.1VDDP Type Max VDDP+0.5 0.33VDDP 10 Unit V V µA V V 19 S3C2800 MICROCONTROLLER DATA SHEET MECHANICAL DATA PACKAGE DIMENSIONS 30.00 ± 0.30 28.00 ± 0.20 0~8 0.127 - 0.05 + 0.10 30.00 ± 0.30 28.00 ± 0.20 208-LQFP-2828 0.10 MAX #208 #1 0.50 0.20 + 0.10 - 0.05 0.08 MAX 0.10 ± 0.05 (1.25) 1.40 ± 0.10 1.60 MAX NOTE: Dimensions are in millimeters. Figure 3. 208-LQFP-2828 Package Dimensions 20 0.50 ¡¾0.20