S3C7324

S3C7324/P7324 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C7324 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as LCD direct drive capability, 4-channel A/D converter, 24-bit AM/FM frequency counter and watch timer, the S3C7324 offers an excellent design solution for a wide variety of applications that require LCD functions and audio applications. Up to 32 pins of the 64-pin QFP package, it can be dedicated to I/O. Five vectored interrupts provide fast response to internal and external events. In addition, the S3C7324 's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The S3C7324 microcontroller is also available in OTP (One Time Programmable) version, S3P7324 . The S3P7324 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7324 is comparable to S3C7324, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C7324/P7324 FEATURES Memory — 256 × 4-bit RAM — 4096 × 8-bit ROM I/O Pins — Input only: 8 pins — I/O: 16 pins — Output only: 8 pins sharing with segment driver outputs LCD Controller/Driver — Maximum 14-digit LCD direct drive capability — 28 segment and 4 common pins — Display modes: Static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) — Internal resistor circuit for LCD bias Oscillation Sources 8-Bit Basic Timer — Programmable interval timer — Watchdog timer 8-Bit Timer — Programmable 8-bit timer Watch Timer — Real-time and interval time measurement — Four frequency outputs to BUZ pin — Clock source generation for LCD 24-Bit Frequency Counter (FC) — Level = 300mVpp (Min.) — AMF input range = 0.5 MHz to 10 MHz — FMF input range = 30 MHz to 150 MHz A/D Converter — 4-channels with 8-bit resolution — 17 µs (Min.) conversion speed — Crystal, ceramic, or RC for main system clock — Crystal or external oscillator for subsystem clock — Main system clock frequency: 4.19 MHz (typical) — Subsystem clock frequency: 32.768 kHz — CPU clock divider circuit (by 4, 8, or 64) Instruction Execution Times — 0.95, 1.91, 15.3 µs at 4.19 MHz (main) — 122 µs at 32.768 kHz (subsystem) Operating Temperature — – 40 °C to 85 °C Operating Voltage Range — 1.8 V to 5.5 V at 3 MHz — 3.0 V to 5.5 V at FC mode Package Type — 64-pin QFP Two Power-Down Modes — Idle mode (only CPU clock stops) — Stop mode (main system clock stops) — Subsystem clock stops Bit Sequential Carrier — Support 16-bit serial data transfer in arbitrary format Interrupts — Two internal vectored interrupts — Three external vectored interrupts — Two quasi-interrupts Memory-Mapped I/O Structure — Data memory bank 15 1-2 S3C7324/P7324 PRODUCT OVERVIEW BLOCK DIAGRAM RESET X IN XTIN X OUT XTOUT Watchdog Timer P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT3 P2.0 P2.1 P2.2/FMF P2.3/AMF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 I/O Port 1 Interrupt Control Block Clock Instruction Register Basic Timer Watch Timer Input Port 2 Input Port 3 A/D Converter I/O Port 4, 5 Internal Interrupts Program Counter Freq. Counter FMF AMF 8-Bit Timer Program Status Word LCD Driver/ Countroller Stack Pointer Instruction Decoder COM0-COM3 SEG0-SEG19 P8.0-P8.3/ SEG27-SEG24 P9.0-P9.3/ SEG23-SEG20 P4.0-P4.3 P5.0-P5.3 P6.0/BUZ P6.1/KS0 P6.2/KS1 P6.3/KS2 Arithmetic and Logic Unit Output Port 8,9 I/O Port 6 256 x 4-Bit Data Memory 4-Kbyte Program Memory Figure 1-1. S3C7324 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C7324/P7324 PIN ASSIGNMENTS P2.0 P2.1 P2.2/FMF P2.3/AMF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 VDD V SS XOUT XIN TEST XTIN XTOUT RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 S3C7324 (Top View) SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 P9.3/ SEG20 P9.2/ SEG21 P9.1/SEG22 P9.0/ SEG23 P8.3/ SEG24 P8.2/ SEG25 P8.1/SEG26 P8.0/ SEG27 Figure 1-2. S3C7324 64-QFP Pin Assignment 1-4 P1.3/INT4 P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/BUZ P6.1/KS0 P6.2/KS1 P6.3/KS2 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C7324/P7324 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C7324 Pin Descriptions Pin Name P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0–P4.3 P5.0–P5.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read, write, and test are possible. Each pin can be specified as input or output port. Pull-up resistors can be configured by software. 4-bit input port. 1-bit and 4-bit read and test are possible. Pull-up resistors can be configured by software. 4-bit input port. 1-bit and 4-bit read and test are possible Pull-up resistors can be configured by software. 4-bit I/O ports. N-channel open-drain output up to 5 V. 1-bit and 4-bit read, write, and test are possible. Ports 4 and 5 can be paired to support 8-bit data. Pull-up resistors can be configured by software. 1-bit and 4-bit read, write, and test are possible. Each pin can be specified as input or output port. Pull-up resistors can be configured by software. LCD segment signal output 4-bit output ports. 1-bit and 4-bit write and test are possible. Ports 8 and 9 can be paired to support 8-bit data. LCD common signal output Main power supply Main ground Crystal, ceramic, or RC oscillator pins for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) Crystal oscillator pin for a subsystem clock. (For external clock input, use XTIN and input XTIN's reverse phase to XTOUT) Number 17 18 19 20 1 2 3 4 5 6 7 8 21–24 25–28 Share Pin INT0 INT1 INT2 INT4 – – FMF AMF ADC0 ADC1 ADC2 ADC3 – – Reset Value Input Circuit Type D-4 I Input A-4 A-4 B-4 B-4 F-13 I Input I/O Input E-2 P6.0 P6.1 P6.2 P6.3 SEG0–SEG19 P8.0–P8.3 P9.0–P9.3 COM0–COM3 VDD VSS XOUT, XIN I/O 29 30 31 32 60–41 33–36 37–40 64–61 9 10 11,12 BUZ KS0 KS1 KS2 – SEG27– SEG20 – – – – Input D-2 D-4 D-4 D-4 H-16 H-16 O O Output Output O – – – Output – – – H-16 – – – XTOUT, XTIN – 15,14 – – – 1-5 PRODUCT OVERVIEW S3C7324/P7324 Table 1-1. S3P7324 Pin Descriptions (Continued) Pin Name SEG20–SEG27 ADC0–ADC3 FMF AMF INT4 INT2 INT1 INT0 Pin Type O I I I I I Description LCD segment signal output ADC input ports External FM/AM frequency inputs External interrupt input with detection of rising or falling edges. Quasi-interrupt with detection of rising edge signals. External interrupt. The triggering edges for INT0 and INT1 are able to be selected. Only INT0 is synchronized with the system clock. 2, 4, 8, or 16 kHz frequency output for buzzer sound with 4.19 MHz main system clock. Quasi-interrupt input with falling edge detection. System reset signal System test pin(must be connected to VSS) Number 40–33 5–8 3 4 20 19 18 17 Share Pin P9.0–P9.3 P8.0–P8.3 P3.0–P3.3 P2.2 P2.3 P1.3 P1.2 P1.1 P1.0 Reset Value Output Input Input Input Input Input Circuit Type H-16 F-13 B-4 A-4 A-4 A-4 BUZ O 29 P6.0 Input D-2 KS0–KS2 RESET TEST I I – 30–32 16 13 P6.1–P6.3 – – Input Input – D-4 B – NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode. 1-6 S3C7324/P7324 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD P-CHANNEL IN VDD IN N-CHNNEL Figure 1-3. Pin Circuit Type A Figure 1-5. Pin Circuit Type B VDD Type A Pull-up Enable Feedback Enable Pull-down Enable In Figure 1-4. Pin Circuit Type A-4 Figure 1-6. Pin Circuit Type B-4 1-7 PRODUCT OVERVIEW S3C7324/P7324 VDD VDD Data Out Output Disable Pull-up Enable Data Output Disable Circuit TYPE C I/O Figure 1-7. Pin Circuit Type C Figure 1-9. Pin Circuit Type D-4 VDD PNE VDD VDD Pull-up Enable I/O Pull-up Enable Data Output Disable Circuit TYPE C Data I/O Output Disable Figure 1-8. Pin Circuit Type D-2 Figure 1-10. Pin Circuit Type E-2 1-8 S3C7324/P7324 PRODUCT OVERVIEW VDD Pull-up Enable Data ADCEN In ADC Select To ADC Figure 1-11. Pin Circuit Type F-13 1-9 PRODUCT OVERVIEW S3C7324/P7324 VDD VLC0 VLC1 SEG/COM and Port Data Out VLC2 Figure 1-12. Pin Circuit Type H-16 1-10 S3C7324/P7324 ELECTRICAL DATA 15 OVERVIEW ELECTRICAL DATA In this section, information on S3C7324 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — Main system clock oscillator characteristics — Subsystem clock oscillator characteristics — I/O capacitance — A.C. electrical characteristics — Operating voltage range Miscellaneous Timing Waveforms — A.C timing measurement point — Clock timing measurement at XIN — Clock timing measurement at XTIN — Input timing for RESET — Input timing for external interrupts Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 15-1 ELECTRICAL DATA S3C7324/P7324 Table 15-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VIN VO I OH I OL All I/O ports – One I/O port active All I/O ports active Output Current Low One I/O port active Conditions – Rating – 0.3 to + 6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 15 – 30 + 30 (Peak value) + 15 (note) Total value for ports 1, 4, 5 and 6 Operating Temperature Storage Temperature TA Tstg – – + 100 (Peak value) + 60 (note) Units V mA – 40 to + 85 – 65 to + 150 Duty . °C NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value × Table 15-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 Conditions All input pins except those specified below P1, P3, RESET, P2.0−1 and P6.1−3 XIN, XOUT, XTIN, and XTOUT All input pins except those specified below P1, P3, RESET, P2.0−1 and P6.1−3 XIN, XOUT, XTIN, and XTOUT VDD = 4.5 V to 5.5 V IOH = – 1 mA Ports 1, 4, 5, and 6 VDD = 4.5 V to 5.5 V IOH = –100 µA Port 8 and 9 VDD – 1.0 – Min 0.7 VDD 0.8 VDD VDD – 0.1 – – Typ – Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 – V V Units V VOH2 VDD – 2.0 15-2 S3C7324/P7324 ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Output low voltage Symbol VOL1 VOL2 Input high leakage current (note) Input low leakage current (note) Output high leakage current (note) Output low leakage current (note) Pull-up resistor ILIH1 Conditions VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 1, 4, 5, and 6 VDD = 4.5 V to 5.5 V IOL = 100 µA ; Ports 8and 9 VIN = VDD All input pins VIN = 0 V All input pins VOUT = VDD All output pins VOUT = 0 V All output pins VIN = 0 V; VDD = 5 V Ports 1, 2, 3, 4, 5, and 6 VDD = 3 V RL2 VIN = 0 V; VDD = 5 V RESET Min – – – Typ 0.4 – – Max 2 1 3 Units V µA ILIL1 – – –3 ILOH1 – – 3 ILOL –3 RL1 20 30 100 40 95 230 80 200 400 KΩ VDD = 3 V NOTE: Except for XIN, XOUT, XTIN, and XTOUT 200 480 800 15-3 ELECTRICAL DATA S3C7324/P7324 Table 15-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter LCD voltage dividing resistor COM output impedance SEG output impedance COM output voltage deviation SEG output voltage deviation Oscillator feedback resistor VDC RSEG Symbol RLCD TA = 25 øC VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V (VLC0-COMi) Io = ± 15uA (I = 0–3) VDS VDD = 5 V (VLC0-SEGi) Io = ± 15uA (I = 0–27) VDD = 5.0 V; TA = 25; XIN = VDD, XOUT = 0 V VDD = 5.0 V; TA = 25; XTIN = VDD, XTOUT = 0 V – ± 45 ± 90 – – Conditions Min 60 Typ 84 Max 130 Units KΩ RCOM − 3 5 3 5 ± 45 6 15 6 15 ± 90 mV ROSC1 300 600 1500 KΩ ROSC2 1230 2630 4000 15-4 S3C7324/P7324 ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply Current(1) Symbol IDD1 Conditions Main operating: FC enable PCON = 0011B, SCMOD = 0000B Crystal oscillator C1 = C2 = 22 pF VDD = 5 V ± 10% Main operating: PCON = 0011B, SCMOD = 0000B Crystal oscillator C1 = C2 = 22 pF VDD = 5 V ± 10% VDD = 3 V ± 10% IDD3 (2) Main idle mode(3): PCON = 0111B, SCMOD =0000B Min 4.19 MHz – Typ 5.2 Max 10 Units mA IDD2 (2) 6.0 MHz 4.19 MHz – 3.5 2.5 8 5.5 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz – 1.6 1.2 1.0 0.9 4 3 2.5 2.0 Crystal oscillator C1 = C2 = 22 pF VDD = 5 V ± 10% VDD = 3 V ± 10% IDD4(2) Sub operating mode: PCON = 0011B, SCMOD = 1001B VDD = 3 V ± 10% 32 kHz crystal oscillator Sub idle mode: PCON = 0111B, SCMOD = 1001B VDD = 3 V ± 10% 32 kHz crystal oscillator Stop mode: CPU = fxt/4, SCMOD = 1101B VDD = 5 V ± 10% Stop mode: CPU = fx/4, SCMOD = 0100B VDD = 5 V ± 10% 6.0 MHz 4.19 MHz – 0.5 0.4 15 1.0 0.8 30 uA IDD5 (2) – 6 15 IDD6(2) – 0.5 3 IDD7(2) – NOTES: 1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors. 2. AMF or FMF is a normal input mode. 3. Data includes the power consumption for sub-system clock oscillation. 15-5 ELECTRICAL DATA S3C7324/P7324 Table 15-3. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT (1) Parameter Oscillation frequency Test Condition – Min 0.4 Typ – Max 6.0 Units MHz C1 C2 Stabilization time (2) Stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – – 4 ms Crystal Oscillator XIN XOUT Oscillation frequency (1) 0.4 – 6.0 MHz C1 C2 Stabilization time (2) VDD = 2.7 V to 5.5 V VDD = 1.8 V to 2.7 V – – 0.4 – – – 10 30 6.0 ms External Clock XIN XOUT XIN input frequency (1) – MHz XIN input high and low level width (tXH, tXL) RC Oscillator XIN XOUT R – VDD = 5 V R = 15 KΩ, VDD = 5 V R = 25 KΩ, VDD = 3 V 83.3 0.4 – − 2.0 1.0 – 2.5 ns MHz Frequency (1) NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated. 15-6 S3C7324/P7324 ELECTRICAL DATA Table 15-4. Subsystem Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration XT IN XT OUT (1) Parameter Oscillation frequency Test Condition – Min 32 Typ 32.768 Max 35 Units kHz C1 C2 Stabilization time (2) VDD = 2.7 V to 5.5 V VDD = 1.8 V to 2.7 V – – 32 1.0 – – 2 10 100 s External Clock XT IN XT OUT XTIN input frequency (1) – kHz XTIN input high and low level width (tXTL, tXTH) – 5 – 15 µs NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs. 15-7 ELECTRICAL DATA S3C7324/P7324 Table 15-5. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Condition f CLK = 1 MHz; Unmeasured pins are returned to VSS Min – – – Typ – – – Max 15 15 15 Units pF pF pF Table 15-6. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) Interrupt input high, low width RESET Input Low Symbol tCY tINTH, tINTL tRSL Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V INT0 INT1, INT2, INT4, KS0–KS2 Input Min 0.67 1.3 (2) Typ – Max 64 64 Units µs µs µs – – 10 10 – – Width NOTES: 1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fxx as assigned by the IMOD0 register setting. Table 15-6. A.C. Electrical Characteristics (continued) (TA = – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V) Parameter A/D converting Resolution Absolute accuracy AD conversion time Analog input voltage Analog input impedance Symbol – – tCON VIAN RAN Conditions – – – – – Min 8 – 17 VSS 2 Typ 8 – 34/fxx (note) – 1000 Max 8 ±2 – VDD – Units bits LSB µs V MΩ NOTE: fxx stands for the system clock (fx or fxt). 15-8 S3C7324/P7324 ELECTRICAL DATA Table 15-6. A.C. Electrical Characteristics (continued) (TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V) Parameter Input voltage (peak to peak) Frequency Symbol VIN f AMF f FMF Conditions AMF/FMF mode, sine wave input AMF mode, sine wave input; VIN = 300mVP-P FMF mode, sine wave input; VIN = 300mVP-P Min 0.3 0.5 30 Typ – – Max VDD 10 150 Units V MHz CPU CLOCK 1.5 MHz 1.0475 MHz 750 kHz 500 kHz 250 kHz Main OSC. Freq. 6 MHz 4.19 MHz 3 MHz 15.6 kHz 400 kHz 1 2 3 4 5 6 7 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64) When FC operates, operating voltage range is 3.0 V to 5.5 V. Figure 15-1. Standard Operating Voltage Range Table 15-7. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Normal operation VDDDR = 1.8 V Min 1.8 – Typ – 0.1 Max 5.5 1 Unit V µA 15-9 ELECTRICAL DATA S3C7324/P7324 TIMING WAVEFORMS INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE OPERATING MODE VDD VDDDR EXECUTION OF STOP INSTRUCTION RESET tWAIT t SREL Figure 15-2. Stop Mode Release Timing When Initiated by RESET RESET IDLE MODE STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE VDD VDDDR EXECUTION OF STOP INSTRUCTION tSREL POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) t WAIT Figure 15-3. Stop Mode Release Timing When Initiated by an Interrupt Request 15-10 S3C7324/P7324 ELECTRICAL DATA 0.8 VDD 0.2 VDD MEASUREMENT POINTS 0.8 VDD 0.2 VDD Figure 15-4. A.C. Timing Measurement Points (Except for Xin and XTin) 1 / fx tXL t XH Xin VDD – 0.1 V 0.1 V Figure 15-5. Clock Timing Measurement at Xin 1 / fxt t XTL t XTH XTin VDD – 0.1 V 0.1 V Figure 15-6. Clock Timing Measurement at XTin 15-11 ELECTRICAL DATA S3C7324/P7324 tRSL RESET 0.2 VDD Figure 15-7. Input Timing for RESET Signal RESET tINTL t INTH INT0, 1, 2, 4 KS0 to KS2 0.8 VDD 0.2 VDD Figure 15-8. Input Timing for External Interrupts and Quasi-Interrupts 15-12 S3C7324/P7324 MECHANICAL DATA 16 OVERVIEW MECHANICAL DATA The S3C7324 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F). Package dimensions are shown in Figure 16-1. 23.90 ± 0.3 20.00 ± 0.2 0-8° 0.15 +0.10 - 0.05 17.90 ± 0.3 14.00 ± 0.2 64-QFP-1420F 0.80 ± 0.20 #1 1.00 0.40 - 0.05 ± 0.15MAX +0.10 0.10 MAX #64 (1.00 ) 0.05~0.25 (1.00) 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE : Dimensions are in millimeters. Figure 16-1. 64-QFP-1420F Package Dimensions 16-1 S3C7324/P7324 S3P7324 OTP 17 OVERVIEW S3P7324 OTP The S3P7324 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7324microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The S3P7324 is fully compatible with the S3C7324, both in function and in pin configuration. Because of its simple programming requirements, the S3P7324 is ideal for use as an evaluation chip for the S3C7324. 17-1 S3P7324 OTP S3C7324/P7324 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 54 SEG7 53 64 63 62 61 60 59 58 57 56 55 P2. 0 P2.1 P2.2/FMF P2.3/AMF P3.0/ADC0 P3.1/ADC1 SDAT /P3.2/ADC2 SCLK /P3.3/ADC3 V DD /V DD V SS/V SS XOUT XIN V PP/TEST XTIN XTOUT RESET / RESET R ESET P1.0/INT0 P1.1/INT1 P1.2/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG8 S3P7324 (Top View) SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 P9.3/ SEG20 P9.2/ SEG21 P9.1/SEG22 P9.0/ SEG23 P8.3/ SEG24 P8.2/ SEG25 P8.1/SEG26 P8.0/ SEG27 23 24 25 26 27 28 29 30 P6.1/KS0 31 P6.2/KS1 P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P1.3/INT4 Figure 17-1. S3P7324 Pin Assignments (64-QFP) 17-2 P6.0/BUZ P6.3/KS2 32 S3C7324/P7324 S3P7324 OTP Table 17-1. Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name P3.2 Pin Name SDAT Pin No. 7 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input or push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P3.3 TEST SCLK VPP (TEST) 8 13 I/O I RESET VDD / VSS RESET VDD / VSS 16 9/10 I I Table 17-2. Comparison of S3P7324 and S3C7324 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P7324 4K bytes EPROM 2.0 V to 5.5 V at 4.19 MHz 1.8 V to 5.5 V at 3 MHz VDD = 5 V, VPP (TEST) = 12.5 V 64 QFP User Program 1 time 64 QFP Programmed at the factory S3C7324 4K bytes mask ROM 2.0 V to 5.5 V at 4.19 MHz 1.8 V to 5.5 V at 3 MHz – OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P7324, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below. Table 17-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode NOTE: "0" means low level; "1" means high level. 17-3 S3P7324 OTP S3C7324/P7324 Table 17-4. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 Conditions All input pins except those specified below P1, P3, RESET, P2.0−1 and P6.1−3 XIN, XOUT, XTIN, and XTOUT All input pins except those specified below P1, P3, RESET, P2.0−1 and P6.1−3 XIN, XOUT, XTIN, and XTOUT VDD = 4.5 V to 5.5 V IOH = – 1 mA Ports 1, 4, 5, and 6 VDD = 4.5 V to 5.5 V IOH = –100 µA Port 8 and 9 VDD – 1.0 – Min 0.7 VDD 0.8 VDD VDD – 0.1 – – Typ – Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 – V V Units V VOH2 VDD – 2.0 17-4 S3C7324/P7324 S3P7324 OTP Table 17-4. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Output low voltage Symbol VOL1 VOL2 Input high leakage current(note) Input low leakage current(note) Output high leakage current(note) Output low leakage current (note) Pull-up resistor ILIH1 Conditions VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 1, 4, 5, and 6 VDD = 4.5 V to 5.5 V IOL = 100 µA ; Ports 8 and 9 VIN = VDD All input pins VIN = 0 V All input pins VOUT = VDD All output pins VOUT = 0 V All output pins VIN = 0 V; VDD = 5 V Ports 1, 2, 3, 4, 5, and 6 VDD = 3 V RL2 VIN = 0 V; VDD = 5 V RESET Min – – – Typ 0.4 – – Max 2 1 3 Units V µA ILIL1 – – –3 ILOH1 – – 3 ILOL – – –3 RL1 20 30 100 40 95 230 80 200 400 KΩ VDD = 3 V NOTE: Except for XIN, XOUT, XTIN, and XTOUT 200 480 800 17-5 S3P7324 OTP S3C7324/P7324 Table 17-4. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter LCD voltage dividing resistor COM output impedance SEG output impedance COM output voltage deviation SEG output voltage deviation Oscillator feedback resistor VDC RSEG Symbol RLCD TA = 25 øC VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V (VLC0-COMi) Io = ± 15uA (I = 0–3) VDS VDD = 5 V (VLC0-SEGi) Io = ± 15uA (I = 0–27) VDD = 5.0 V; TA = 25; XIN = VDD, XOUT = 0 V VDD = 5.0 V; TA = 25; XTIN = VDD, XTOUT = 0 V – ± 45 ± 90 – – Conditions Min 60 Typ 84 Max 130 Units KΩ RCOM − 3 5 3 5 ± 45 6 15 6 15 ± 90 mV ROSC1 300 600 1500 KΩ ROSC2 1230 2630 4000 17-6 S3C7324/P7324 S3P7324 OTP Table 17-4. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply Current(1) Symbol IDD1 Conditions Main operating: FC enable PCON = 0011B, SCMOD = 0000B Crystal oscillator C1 = C2 = 22 pF VDD = 5 V ± 10% Main operating: PCON = 0011B, SCMOD = 0000B Crystal oscillator C1 = C2 = 22 pF VDD = 5 V ± 10% VDD = 3 V ± 10% IDD3 (2) Main idle mode(3): PCON = 0111B, SCMOD =0000B Min 4.19 MHz – Typ 5.2 Max 10 Units mA IDD2 (2) 6.0 MHz 4.19 MHz – 3.5 2.5 8 5.5 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz – 1.6 1.2 1.0 0.9 4 3 2.5 2.0 Crystal oscillator C1 = C2 = 22 pF VDD = 5 V ± 10% VDD = 3 V ± 10% IDD4(2) Sub operating mode: PCON = 0011B, SCMOD = 1001B VDD = 3 V ± 10% 32 kHz crystal oscillator Sub idle mode: PCON = 0111B, SCMOD = 1001B VDD = 3 V ± 10% 32 kHz crystal oscillator Stop mode: CPU = fxt/4, SCMOD = 1101B VDD = 5 V ± 10% Stop mode: CPU = fx/4, SCMOD = 0100B VDD = 5 V ± 10% 6.0 MHz 4.19 MHz – 0.5 0.4 15 1.0 0.8 30 uA IDD5 (2) – 6 15 IDD6(2) – 0.5 3 IDD7(2) – NOTES: 1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors. 2. AMF or FMF is a normal input mode. 3. Data includes the power consumption for sub-system clock oscillation. 17-7 S3P7324 OTP S3C7324/P7324 Table 17-5. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT (1) Parameter Oscillation frequency Test Condition – Min 0.4 Typ – Max 6.0 Units MHz C1 C2 Stabilization time (2) Stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – – 4 ms Crystal Oscillator XIN XOUT Oscillation frequency (1) 0.4 – 6.0 MHz C1 C2 Stabilization time (2) VDD = 2.7 V to 5.5 V VDD = 1.8 V to 2.7 V – – 0.4 – – – 10 30 6.0 ms External Clock XIN XOUT XIN input frequency (1) – MHz XIN input high and low level width (tXH, tXL) RC Oscillator XIN XOUT R – VDD = 5 V R = 15 KΩ, VDD = 5 V R = 25 KΩ, VDD = 3 V 83.3 0.4 – − 2.0 1.0 – 2.5 ns MHz Frequency (1) NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated. 17-8 S3C7324/P7324 S3P7324 OTP Table 17-6. Subsystem Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration XT IN XT OUT (1) Parameter Oscillation frequency Test Condition – Min 32 Typ 32.768 Max 35 Units kHz C1 C2 Stabilization time (2) VDD = 2.7 V to 5.5 V VDD = 1.8 V to 2.7 V – – 32 1.0 – – 2 10 100 s External Clock XT IN XT OUT XTIN input frequency (1) – kHz XTIN input high and low level width (tXTL, tXTH) – 5 – 15 µs NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs. 17-9 S3P7324 OTP S3C7324/P7324 Table 17-7. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Condition f CLK = 1 MHz; Unmeasured pins are returned to VSS Min – – – Typ – – – Max 15 15 15 Units pF pF pF Table 17-8. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) Interrupt input high, low width RESET Input Low Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V Min 0.67 1.3 (2) Typ – Max 64 64 Units µs µs µs tINTH, tINTL tRSL INT0 INT1, INT2, INT4, KS0–KS2 Input – – 10 10 – – Width NOTES: 1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fxx as assigned by the IMOD0 register setting. Table 17-8. A.C. Electrical Characteristics (continued) (TA = – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V) Parameter A/D converting Resolution Absolute accuracy AD conversion time Analog input voltage Analog input impedance Symbol – – tCON VIAN RAN Conditions – – – – – Min 8 – 17 VSS 2 Typ 8 – 34/fxx (note) – 1000 Max 8 ±2 – VDD – Units bits LSB µs V MΩ NOTE: fxx stands for the system clock (fx or fxt). 17-10 S3C7324/P7324 S3P7324 OTP Table 17-8. A.C. Electrical Characteristics (continued) (TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V) Parameter Input voltage (peak to peak) Frequency Symbol VIN f AMF f FMF Conditions AMF/FMF mode, sine wave input AMF mode, sine wave input; VIN = 300mVP-P FMF mode, sine wave input; VIN = 300mVP-P Min 0.3 0.5 30 Typ – – Max VDD 10 150 Units V MHz CPU CLOCK 1.5 MHz 1.0475 MHz 750 kHz 500 kHz 250 kHz Main OSC. Freq. 6 MHz 4.19 MHz 3 MHz 15.6 kHz 400 kHz 1 2 3 4 5 6 7 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64) When FC operates, operating voltage range is 3.0 V to 5.5 V. Figure 17-2. Standard Operating Voltage Range Table 17-9. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Normal operation VDDDR = 1.8 V Min 1.8 – Typ – 0.1 Max 5.5 1 Unit V µA 17-11 S3P7324 OTP S3C7324/P7324 TIMING WAVEFORMS INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE OPERATING MODE VDD VDDDR EXECUTION OF STOP INSTRUCTION RESET tWAIT t SREL Figure 17-3. Stop Mode Release Timing When Initiated by RESET RESET IDLE MODE STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE VDD VDDDR EXECUTION OF STOP INSTRUCTION tSREL POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) t WAIT Figure 17-4. Stop Mode Release Timing When Initiated by an Interrupt Request 17-12 S3C7324/P7324 S3P7324 OTP 0.8 VDD 0.2 VDD MEASUREMENT POINTS 0.8 VDD 0.2 VDD Figure 17-5. A.C. Timing Measurement Points (Except for Xin and XTin) 1 / fx tXL t XH Xin VDD – 0.1 V 0.1 V Figure 17-6. Clock Timing Measurement at Xin 1 / fxt t XTL t XTH XTin VDD – 0.1 V 0.1 V Figure 17-7. Clock Timing Measurement at XTin 17-13 S3P7324 OTP S3C7324/P7324 tRSL RESET 0.2 VDD Figure 17-8. Input Timing for RESET Signal RESET tINTL t INTH INT0, 1, 2, 4 KS0 to KS2 0.8 VDD 0.2 VDD Figure 17-9. Input Timing for External Interrupts and Quasi-Interrupts 17-14