S3C7524

S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable for its low energy consumption and low operating voltage. You can select from two ROM sizes: 4K or 8K bytes Except for the difference in ROM size, the features and functions of the S3C7524 and the S3C7528, the S3C7534 and the S3C7538 are identical. With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, theS3C7524/C7528 /C5304/C5308 offers an excellent design solution for a wide variety of telecommunication applications. Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the S3C7524/C7528, and up to 23 pins of the available 30-pin SDIP or 32-pin SOP package for the S3C7534/C7538 can be assign to I/O. Six vectored interrupts for S3C7524/C7528 and four vectored interrupts for S3C7534/C7538 provide fast response to internal and external events. In addition, the S3C7524/C7528/C7534/C7538 's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The S3C7524/C7528 microcontroller is also available in OTP (One Time Programmable) version, S3P7528. The S3C7534/C7538 microcontroller is also available in OTP (One Time Programmable) version, S3P7538. The S3P7528/P7538 microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM. The S3P7528 is comparable to S3C7524/C7528, both in function and in pin configuration. Also, the S3P7538 is comparable to the S3C7534/C7538, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 FEATURES SUMMARY Memory • • 768 × 4-bit RAM 4,096 × 8-bit ROM (S3C7524/C7534) 8,192 × 8-bit ROM (S3C7528/C7538) Interrupts • • • 3 external interrupt vectors (S3C7524/C7528) 1 external interrupt vectors (S3C7534/C7538) 3 internal interrupt vectors 2 quasi-interrupts 35 I/O Pins • • • Input only: 4 pins (S3C7524/C7528) 1 pins (S3C7534/C7538) I/O: 23 pins (S3C7524/C7528) 14 pins (S3C7534/C7538) N-channel open-drain I/O: 8 pins Power-Down Modes • • Idle: Only CPU clock stops Stop: System clock stops Oscillation Sources • • • Crystal, or ceramic for main system clock Main system clock frequency: 0.4–6.0 MHz (typical) CPU clock divider circuit (by 4, 8, or 64) Memory-Mapped I/O Structure • Data memory bank 15 DTMF Generator • 16 dual-tone frequencies for tone dialing Instruction Execution Times • • • 0.95, 1.91, and 15.3 µs at 4.19 MHz 1.12, 2.23, 17.88 µs at 3.58 MHz 0.67, 1.33, 10.7 µs at 6.0 MHz 8-Bit Basic Timer • • Programmable interval timer Watchdog timer Two 8-Bit Timer/Counters • • • Programmable 8-bit timer External event counter function Arbitrary clock frequency output Operating Temperature • – 40 °C to 85 °C Operating Voltage Range • 2.0 V to 5.5 V Watch Timer • • Real-time and interval time measurement Four frequency outputs to the BUZ pin Package Types • • 42 SDIP, 44 QFP (S3C7524/C7528) 30 SDIP, 32 SOP (S3C7534/C7538) Bit Sequential Carrier • Supports 8-bit serial data transfer in arbitrary format 1-2 S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW BLOCK DIAGRAM INT0, INT1, INT2, INT4 8-BIT TIMER/ COUNTER 0 8-BIT TIMER/ COUNTER 1 P6.0–P6.3 / KS0–KS3 P7.0–P7.3 / KS4–KS7 RESET Xin Xout BASIC TIMER WATCH TIMER WATCH-DOG TIMER INPUT PORT 1 PROGRAM STATUS WORD I/O PORT 2 FLAGS I/O PORT 3 P1.0 / INT0 P1.1 / INT1 P1.2 / INT2 P1.3 / INT4 P2.0 / TCLO0 P2.1 / TCLO1 P2.2 / CLO P2.3 / BUZ P3.0 / TCL0 P3.1 / TCL1 P3.2 P3.3 P4.0 / BTCO P4.1 −P4.3 P5.0–P5.3 INTERRUPT CONTROL BLOCK CLOCK STACK POINTER I/O PORT 6 I/O PORT 7 INTERNAL INTERRUPTS INSTRUCTION DECODER PROGRAM COUNTER P8.0–P8.3 P9.0–P9.2 I/O PORT 8 I/O PORT 9 ARITHMETIC AND LOGIC UNIT I/O PORT 4 I/O PORT 5 768 x 4-BIT DATA MEMORY PROGRAM MEMORY S3C7524/C7534: 4 KBytes S3C7528/C7538: 8 KBytes DTMF GENERATOR DTMF NOTE: S3C7534/C7538 does not use P1.1/INT1, P1.2/INT2, P1.3/INT3, P3.2, P3.3, INT1, INT2, INT4, P8.0-P8.3, and P9.0-P9.2. Figure 1–1. S3C7524/C7528 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 PIN ASSIGNMENTS P1.0 / INT0 P1.1 / INT1 P1.2 / INT2 P1.3 / INT4 P2.0 / TCLO0 P2.1 / TCLO1 P2.2 / CLO P2.3 / BUZ P3.0 / TCL0 P3.1 / TCL1 VDD V SS XOUT XIN TEST P4.0 / BTCO P4.1 RESET P3.2 P3.3 P4.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P9.2 P9.1 P9.0 DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 S3C7524/C7528 Figure 1–2. S3C7524/C7528 Pin Assignment Diagrams (42–SDIP) (42-SDIP-600) 1-4 S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW P2.2 / CLO P2.3 / BUZ P3.0 / TCL0 P3.1 / TCL1 VDD VSS XOUT XIN TEST P4.0 / BTCO P4.1 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 KS57C5204/C5208 29 28 (44-QFP-1010B) 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 P2.1 / TCLO1 P2.0 / TCLO0 P1.3 / INT4 P1.2 / INT2 P1.1 / INT1 P1.0 / INT0 NC P9.2 P9.1 P9.0 DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 Figure 1–3. S3C7524/C7528 Pin Assignment Diagrams (44–QFP) RESET P3.2 P3.3 P4.2 NC P4.3 P8.0 P8.1 P8.2 P8.3 P5.0 1-5 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 VSS XOUT XIN TEST P4.0 / BTCO P4.1 RESET P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P3.1 / TCL1 P3.0 / TCL0 P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 S3C7534/C7538 Figure 1–4. S3C7534/C7538 Pin Assignment Diagrams (30–SDIP) (30-SDIP-400) VSS XOUT XIN TEST P4.0 / BTCO P4.1 RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P3.1 / TCL1 P3.0 / TCL0 P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 NC DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 S3C7534/C7538 Figure 1–5. S3C7534/C7538 Pin Assignment Diagrams (32–SOP) (32-SOP-405A) 1-6 S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C7524/C7528 Pin Descriptions Pin Name P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 P5.0–P5.3 I/O I Pin Reset Type Value I I Description 4-bit input port. 1-bit and 4-bit read and test is possible. Each pull-up resistors are assignable by software. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 2 and 3 can be paired to enable 8-bit data transfer. 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. N-channel open-drain or push-pull output can be selected by software (1-bit unit) Ports 4 and 5 can be paired to support 8-bit data transfer. 4-bit I/O ports. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 8 and 9 can be paired to enable 8-bit data transfer. Pin Number 1 (39) 2 (40) 3 (41) 4 (42) 5 (43) 6 (44) 7 (1) 8 (2) 9 (3) 10 (4) 19 (13) 20 (14) 16 (10) 17 (11) 21 (15) 22 (17) 27–30 (22–25) Share Pin INT0 INT1 INT2 INT4 TCLO0 TCLO1 CLO BUZ TCL0 TCL1 Circuit Type A-4 I/O I D-2 D-4 BTCO E-2 P6.0–P6.3 P7.0–P7.3 I/O I 31–34 (26–29) 35–38 (30–33) KS0–KS3 KS4–KS7 D-4 P8.0–P8.3 P9.0–P9.2 I/O I 23–26 (18–21) 40–42 (35–37) – D-2 1-7 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 Table 1-1. S3C7524/C7528 Pin Descriptions (Continued) Pin Name DTMF BTCO INT0 INT1 INT2 INT4 TCLO0 TCLO1 CLO BUZ Pin Reset Type Value O I/O I I I I/O I/O I/O I/O – I I I I I I I I DTMF output. Basic timer clock output External interrupts. The triggering edge for INT0 and INT1 is selectable. Quasi-interrupt with detection of rising edges External interrupt with detection of rising and falling edges. Timer/counter 0 clock output Timer/counter 1 clock output Clock output 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 4.19 MHz for buzzer sound External clock input for timer/counter 0 External clock input for timer/counter 1 Quasi-interrupt inputs with falling edge detection Description Pin Number 39 (34) 16 (10) 1 (39) 2 (40) 3 (41) 4 (42) 5 (43) 6 (44) 7 (1) 8 (2) Share Pin – P4.0 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 Circuit Type G-6 E-2 A-3 A-3 A-3 D-2 D-2 D-2 D-2 TCL0 TCL1 KS0–KS3 KS4–KS7 VDD VSS RESET I/O I/O I/O I I I 9 (3) 10 (4) 31–34 (26–29) 35–38 (30–33) 11 (5) 12 (6) 18 (12) 14 (8) 13 (7) 15 (9) (16, 38) P3.0 P3.1 P6.0– P6.3 P7.0– P7.3 – – – – D-4 D-4 D-4 – – – – – – – – Power supply Ground RESET signal – – B – Xin Xout TEST NC Crystal, or ceramic oscillator signal for main system clock. (For external clock input, use Xin and input Xin's reverse phase to Xout) Test signal input No connection – – – – – – – – NOTE: Parentheses indicate pin number for 44 QFP package. 1-8 S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW Table 1-2. S3C7534/C7538 Pin Descriptions Pin Name P1.0 Pin Type I Description 1-bit input port. 1-bit and 4-bit read and test is possible. Each bit pull-up resistors are assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. Ports 2 and 3 can be paired to enable 8-bit data transfer. 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. The N-channel open-drain or push-pull output can be selected by software (1-bit unit). Ports 4 and 5 can be paired to enable 8-bit data transfer. 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. Pin Number 23 (25) Share Pin INT0 Circuit Type A-4 P2.0 P2.1 P2.2 P2.3 I/O 24 (26) 25 (27) 26 (28) 27 (29) TCLO0 TCLO1 CLO BUZ D-2 P3.0 P3.1 P4.0 P4.1 P4.2 P4.3 P5.0–P5.3 I/O 28 (30) 29 (31) 5 (5) 6 (6) 8 (8) 9 (10) 10–13 (11–14) TCL0 TCL1 BTCO D-4 E-2 P6.0–P6.3 P7.0–P7.3 I/O 14–17 (15–18) 18–21 (19–22) KS0–KS3 KS4–KS7 D-4 1-9 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 Table 1-1. S3C7534/C7538 Pin Descriptions (Continued) Pin Name DTMF INT0 TCLO0 TCLO1 CLO BUZ I/O Type O I I/O I/O I/O I/O DTMF output. External interrupt input. The triggering edge for INT0 is selectable. Timer/counter 0 clock output Timer/counter 1 clock output Clock output 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 4.19 MHz for buzzer sound External clock input for timer/counter 0 External clock input for timer/counter 1 Basic timer clock output Power supply Ground Crystal, or ceramic oscillator signal for main system clock. (For external clock input, use Xin and input Xin's reverse phase to Xout) No connection Test signal input RESET signal Description Pin Number 22 (23) 23 (25) 24 (26) 25 (27) 26 (28) 27 (29) Share Pin – P1.0 P2.0 P2.1 P2.2 P2.3 Circuit Type G-6 A-3 D-2 D-2 D-2 D-2 TCL0 TCL1 BTCO VDD VSS Xin Xout NC TEST RESET I/O I/O I/O – – – 28 (30) 29 (31) 5 (5) 30 (32) 1 (1) 3 (3) 2 (2) (9, 24) 4 (4) 7 (7) 14–17 (15–18) 18–21 (19–22) P3.0 P3.1 P4.0 – – – D-4 D-4 E-2 – – – – – – I/O – – – P6.0– P6.3 P7.0– P7.3 – – B D-4 KS0–KS3 KS4–KS7 Quasi-interrupt inputs with falling edge detection NOTE: Parentheses indicate the pin number for 32-SOP package. 1-10 S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD PULL-UP RESISTOR P-CHANNEL RESISTOR ENABLE IN N-CHANNEL P-CHANNEL IN SCHMITT TRIGGER Figure 1–6. Pin Circuit Type A Figure 1–8. Pin Circuit Type A-4 VDD VDD PULL-UP RESISTOR P-CHANNEL DATA OUT IN N-CHANNEL SCHMITT TRIGGER OUTPUT DISABLE Figure 1–7. Pin Circuit Type B Figure 1–9. Pin Circuit Type C 1-11 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308 MICROCONTROLLER VDD PULL-UP RESISTOR RESISTOR ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE C PNE VDD VDD PULL-UP RESISTOR P-CHANNEL DATA P-CHANNEL I/O PULL-UP RESISTOR ENABLE I/O OUTPUT DISABLE N-CHANNEL Figure 1–10. Pin Circuit Type D-2 Figure 1–12. Pin Circuit Type E-2 VDD PULL-UP RESISTOR RESISTOR ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE C P-CHANNEL DTMF OUT I/O OUTPUT DISABLE SCHMITT TRIGER Figure 1–11. Pin Circuit Type D-4 Figure 1–13. Pin Circuit Type G-6 1-12 S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA 13 — I/O capacitance ELECTRICAL DATA In this section, information on S3C7524/C7528 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — System clock oscillator characteristics — A.C. electrical characteristics — Operating voltage range Miscellaneous Timing Waveforms — A.C timing measurement point — Clock timing measurement at Xin and Xout — TCL timing — Input timing for RESET — Input timing for external interrupts — Serial data transfer timing Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 13–1 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 Table 13-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI1 VO I OH I OL All I/O ports – One I/O port active All I/O ports active Output Current Low One I/O port active Conditions – Rating – 0.3 to + 6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 15 – 35 + 30 (Peak value) + 15 (note) All I/O ports active Operating Temperature Storage Temperature TA Tstg – – + 100 (Peak value) + 60 (note) – 40 to + 85 – 65 to + 150 Duty . °C °C Units V V V mA mA NOTE: The values for output current low ( IOL ) are calculated as peak value × Table 13-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Conditions All input pins except those specified below for VIH2 – VIH3 Ports 1, 3, 6, 7, and RESET Xin and Xout All input pins except those specified below for VIL2–VIL3 Ports 1, 3, 6, 7, and RESET Xin and Xout Min 0.7 VDD 0.8 VDD VDD – 0.1 – – Typ – Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 V Units V 13–2 S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA Table 13-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Output high voltage Output low voltage Symbol VOH VOL1 Conditions IOH = – 1 mA Ports except 1 VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 4 and 5 only VDD = 2.0 to 5.5 V, IOL = 1.6mA VOL2 VDD = 4.5 V to 5.5 V IOL= 4 mA, all out ports except 4,5 VDD = 2.0 to 5.5 V, IOL = 1.6mA Input high leakage current ILIH1 VI = VDD All input pins except those specified below VI = VDD Xin and Xout VI = 0 V All input pins except below and RESET ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL RL1 VI = 0 V Xin and Xout only VO = VDD All out pins VO = 0 V Xin and Xout only VDD = 5 V; VI = 0 V except RESET VDD = 3 V RL2 VDD = 5 V; VI = 0 V; RESET VDD = 3 V 50 100 200 95 220 450 200 400 800 – – 25 – – 47 – 20 3 –3 100 µA µA kΩ – – Min VDD – 1.0 – – – – – Typ – 0.4 – – – – Max – 2 0.4 2 0.4 3 µA V Units V V ILIH2 Input low leakage current ILIL1 20 –3 µA 13–3 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 Table 13-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 Conditions Min – Typ 2.9 Max 5.0 Units mA Run mode; VDD = 5 V ± 10% (2) (DTMF on) 3.58 MHz crystal oscillator, C1 = C2 = 22 pF VDD = 3 V ± 10% IDD2 Run mode; VDD = 5 V ± 10% VDD = 3 V ± 10% IDD3 Idle mode; = VDD = 5 V ± 10% crystal oscillator, C1 = C2 = 22 pF VDD = 3 V ± 10% IDD4 Stop mode; VDD = 5 V ± 10% Stop mode; VDD = 3 V ± 10% 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 1.6 – 2.6 1.8 1.8 1.2 – 0.7 0.6 0.3 0.2 – 0.01 0.01 3.0 8.0 4.0 4.0 2.3 2.5 1.8 1.5 1.0 3 2 dBV µA mA mA (DTMF off) crystal oscillator, C1 = C2 = 22 pF Row tone level VROW VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2 V RL = 5kΩ VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2 V RL = 5kΩ VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2 V RL = 5kΩ, 1MHz band – 16.0 – 14.0 – 11.0 Ratio of column to row tone dBCR 1 2 3 Distortion (Dual tone) THD – – 5 % NOTES 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers. 2. For D.C. electrical values, the power control register (PCON) must be set to 0011B. 13–4 S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA Table 13-3. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration Xin Xout Parameter Oscillation frequency (1) Test Condition VDD = 2.7 V to 5.5 V Min 0.4 Typ – Max 6.0 Units MHz C1 C2 VDD = 2.0 V to 5.5 V Stabilization time (2) Crystal Oscillator Xin Xout 0.4 – 0.4 – – – 4.2 4 6.0 ms MHz VDD = 3 V VDD = 2.7 V to 5.5 V Oscillation frequency (1) C1 C2 VDD = 2.0 V to 5.5 V Stabilization time (2) External Clock Xin Xout 0.4 – 0.4 – – – 4.2 10 6.0 ms MHz VDD = 3 V VDD = 2.7 V to 5.5 V Xin input frequency (1) VDD = 2.0 V to 5.5V Xin input high and low level width (tXH, tXL) – 0.4 83.3 – – 4.2 1250 ns NOTES 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 13–5 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 Table 13-4. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min – – – Typ – – – Max 15 15 15 Units pF pF pF Table 13-5. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Instruction Cycle Time (1) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0, TCL1 Input f TI0, f TI1 Frequency VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5V TCL0, TCL1 Input tTIH0, tTIL0 High, Low Width tTIH1, tTIL1 VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V Interrupt Input High, Low Width RESET Input Low Min 0.67 0.95 0 Typ – Max 64 Units µs – 1.5 1 MHz MHz µs 0.48 1.8 10 10 – – tINTH, tINTL tRSL INT0, INT1, INT2, INT4, KS0–KS7 Input – – – – µs µs Width 13–6 S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA CPU CLOCK 1.5 MHz Main Osc. Freq. 6 MHz 1.05 MHz 4.2 MHz 15.625 kHz 1 2 3 2.7 V SUPPLY VOLTAGE (V) CPU CLOCK = oscillator frequency x 1/n (n = 4, 8, 64) 4 5 6 7 Figure 13-1. Standard Operating Voltage Range Table 13-6. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions – VDDDR = 1.5 V – Released by RESET Released by interrupt Min 1.5 – 0 – 17 Typ – 0.1 – 2 /fx (2) Max 5.5 10 – – Unit V µA µs ms ms NOTES 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 13–7 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 TIMING WAVEFORMS INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE OPERATING MODE VDD EXECUTION OF STOP INSTRUCTION RESET VDDDR tWAIT t SREL Figure 13-2. Stop Mode Release Timing When Initiated By RESET RESET IDLE MODE STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE VDD VDDDR EXECUTION OF STOP INSTRUCTION tSREL tWAIT POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request 13–8 S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA Timing Waveforms (continued) 0.8 VDD 0.2 VDD MEASUREMENT POINTS 0.8 VDD 0.2 VDD Figure 13-4. A.C. Timing Measurement Points (Except for Xin) 1/fx tXL tXH Xin VDD - 0.1 V 0.1 V Figure 13-5. Clock Timing Measurement at Xin 1 / f TI tTIL tTIH TCL 0.8 V DD 0.2 V DD Figure 13-6. TCL Timing 13–9 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 tRSL RESET 0.2 VDD Figure 13-7. Input Timing for RESET Signal RESET tINTL t INTH INT0, 1, 2, 4 K0 to K7 0.8 VDD 0.2 VDD Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts 13–10 S3C7524/C7528/P7528/C7534/C7538/P7538 MECHANICAL DATA 14 — Pad diagram #42 14.00 ± 0.20 MECHANICAL DATA This section contains the following information about the device package: — Package dimensions in millimeters — Pad/pin coordinate data table #22 0-15 #1 #21 0.20 39.50 MAX 39.10 ± 0.20 0.51 MIN 0.50 ± (1.77) 1.00 ± 0.10 0.10 1.78 NOTE: Dimensions are in millimeters. Figure 14-1. 42-SDIP-600 Package Dimensions 3.30 ± 0.30 5.08 MAX 3.50 ± 0.2 5 +0 - 0 .10 .05 42-SDIP-600 15.24 14–1 MECHANICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 13.20 ± 0.30 0-8 10.00 ± 0.20 0.15 + 0.10 - 0.05 13.20 ± 0.30 10.00 ± 0.20 44-QFP-1010B 0.80 ± 0.20 #1 0.80 + 0.10 0.10 MAX #44 0.35 - 0.05 0.15 MAX (1.00) 0.05 MIN 2.05 ± 0.10 2.30 MAX NOTE: Dimensions are in millimeters. Figure 14-2. 44-QFP-1010B Package Dimensions 14–2 S3C7524/C7528/P7528/C7534/C7538/P7538 MECHANICAL DATA #30 #16 0-15 8.94 ± 0.20 #1 #15 0.20 27.88 MAX 27.48 ± 0.20 0.51 MIN 0.56 ± (1.30) 1.12 ± 0.10 0.10 1.778 NOTE: Dimensions are in millimeters. Figure 14-3. 30-SDIP-400 Package Dimensions 3.30 ± 0.30 5.21 MAX 3.81 ± 0.2 5 +0 - 0 .10 .05 30-SDIP-400 10.16 14–3 MECHANICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 0-8 #32 #17 12.00 ± 0.30 0.20 32-SOP-450A 8.34 ± 0.25 0.10 20.30 MAX 19.90 ± 0.20 2.20 MAX 2.00 ± 0.10 MAX (0.43) 0.40 ± 0.10 1.27 NOTE: Dimensions are in millimeters. Figure 14-4. 32-SOP-450A Package Dimensions 14–4 0.05 MIN 0.90 ± 0.20 #1 #16 + 0.10 - 0.05 11.43 S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP 15 OVERVIEW S3P7528/P7538 OTP The S3P7528/P7538 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7524/C7528/C7534/C7538 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The S3P7528/P7538 is fully compatible with the S3C7528/C7538, both in function and in pin configuration. Because of its simple programming requirements, the S3P7528/P7538 is ideal for use as an evaluation chip for the S3C7528/C7538. P1.0 / INT0 P1.1 / INT1 P1.2 / INT2 P1.3 / INT4 P2.0 / TCLO0 P2.1 / TCLO1 P2.2 / CLO P2.3 / BUZ SDAT / P3.0 / TCL0 SCLK / P3.1 / TCL1 VDD / VDD VSS / VSS XOUT XIN VPP / TEST P4.0 / BTCO P4.1 RESET / RESET RESET P3.2 P3.3 P4.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P9.2 P9.1 P9.0 DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 NOTE: The bold words indicate OTP pin names. Figure 15-1. S3P7528 Pin Assignments (42-SDIP) (42-SDIP-600) S3P7528 15–1 S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538 VSS / V SS XOUT XIN VPP / TEST P4.0 / BTCO P4.1 RESET / RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD / VDD P3.1 / TCL1 / SCLK P3.0 / TCL0 / SDAT P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 NC DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 Figure 15-2. S3P7528 Pin Assignments (44-QFP) KS57P5308 (32-SOP-405A) 15–2 S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP VSS / V SS XOUT XIN VPP / TEST P4.0 / BTCO P4.1 RESET / RESET P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD / VDD P3.1 / TCL1 / SCLK P3.0 / TCL0 / SDAT P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 Figure 15-3. S3P7538 Pin Assignments (30-SDIP) S3C7538 (30-SDIP-400) 15–3 S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538 VSS / V SS XOUT XIN VPP / TEST P4.0 / BTCO P4.1 RESET / RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD / VDD P3.1 / TCL1 / SCLK P3.0 / TCL0 / SDAT P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 NC DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 Figure 15-4. S3P7538 Pin Assignments (32-SOP) S3P7538 (32-SOP-405A) 15–4 S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP Table 15-1. S3P7528 Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name P3.0 Pin Name SDAT Pin No. 9 (3) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P3.1 TEST SCLK VPP (TEST) 10 (4) 15 (9) I/O I RESET VDD / VSS RESET VDD / VSS 18 (12) 11/12 (5/6) I I NOTE: Parentheses indicate pin numbers of 44 QFP package. Table 15-2. S3P7538 Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name P3.0 Pin Name SDAT Pin No. 28 (30) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P3.1 TEST SCLK VPP (TEST) 29 (31) 4 (4) I/O I RESET VDD / VSS RESET VDD / VSS 7 (7) 30/1 (32/1) I I NOTE: Parentheses indicate pin numbers of 32 SDIP package. 15–5 S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538 Table 15-3. Comparison of S3P7528 and S3C7528 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P7528 8 K byte EPROM 2.0 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 42 SDIP / 44 QFP User Program 1 time S3C7528 8 K byte mask ROM 2.0 V to 5.5 V – 42 SDIP / 44 QFP Programmed at the factory Table 15-4. Comparison of S3P7538 and S3C7538 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P7538 8 K byte EPROM 2.0 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 30 SOP / 32 SOP User Program 1 time S3C7538 8 K byte mask ROM 2.0 V to 5.5 V – 30 SOP / 32 SOP Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P7528, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-5. Operating Mode Selection Criteria VDD 5V Vpp (TEST) 5V 12.5V 12.5V 12.5V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode NOTE: "0" means Low level; "1" means High level. 15–6 S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP START Address= First Location VDD =5V, V PP=12.5V x=0 Program One 1ms Pulse Increment X YES x = 10 NO FAIL Verify Byte Verify 1 Byte FAIL Last Address NO Increment Address VDD = VPP= 5 V FAIL Compare All Byte PASS Device Failed Device Passed Figure 15-5. OTP Programming Algorithm 15–7 S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538 NOTES 15–8