S3C8248

S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels. S3C8248/C8245/P8245/C8247/C8249/P8249 MICROCONTROLLER The S3C8248/C8245/P8245/C8247/C8249/P8249 single-chip CMOS microcontroller are fabricated using the highly advanced CMOS process, based on Samsung’s newest CPU architecture. The S3C8248, S3C8245, S3C8247, S3C8249 are a microcontroller with a 8K-byte, 16K-byte, 24K-byte. 32K-byte mask-programmable ROM embedded respectively. The S3P8245 is a microcontroller with a 16K-byte one-time-programmable ROM embedded. The S3P8249 is a microcontroller with a 32K-byte one-time-programmable ROM embedded. Using a proven modular design approach, Samsung engineers have successfully developed the S3C8248/C8245/P8245/C8247/C8249/P8249 by integrating the following peripheral modules with the powerful SAM8 core: — Six programmable I/O ports, including five 8-bit ports and one 5-bit port, for a total of 45 pins. — Eight bit-programmable pins for external interrupts. — One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). — Two 8-bit timer/counter and two 16-bit timer/counter with selectable operating modes. — Watch timer for real time. — 8-input A/D converter — Serial I/O interface The S3C8248/C8245/P8245/C8247/C8249/P8249 is versatile microcontroller for camera, LCD and ADC application, etc. They are currently available in 80-pin TQFP and 80-pin QFP package OTP The S3P8245/P8249 are OTP (One Time Programmable) version of the S3C8245/C8249 microcontroller. The S3P8245 microcontroller has an on-chip 16K-byte one-time-programmable EPROM instead of a masked ROM. The S3P8249 microcontroller has an on-chip 32K-byte one-time-programmable EPROM instead of a masked ROM. The S3P8245 is comparable to the S3P8245, both in function and in pin configuration. The S3P8249 is comparable to the S3P8249, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 FEATURES Memory • • • • • • • • • • • • • • ROM: 32K-byte (S3C8249/P8249) ROM: 16K-byte (S3C8245/P8245) RAM: 1056-Byte (S3C8249/P8249, S3C8247) RAM: 544-Byte (S3C8245/P8245, S3C8248) Data memory mapped I/O Crystal, ceramic, RC (main) Crystal for subsystem clock Main system clock frequency 1-10 MHz (3 MHz at 1.8 V, 10 MHz at 2.7 V) Subsystem clock frequency: 32.768 kHz CPU clock divider (1/1, 1/2, 1/8, 1/16) Idle (only CPU clock stops) Stop (System clock stops) 6 level 8 vector 8 internal interrupt 2 level 8 vector 8 external interrupt 45 I/O Pins • • • • • • • • • • 45 configurable I/O pins Overflow signal makes a system reset. Watchdog function Programmable 8-bit timer Interval, capture, PWM mode Match/capture, overflow interrupt Programmable 8-bit timer Carrier frequency generator Programmable 16-bit timer Match interrupt generates Basic Timer Oscillation Sources 8-Bit Timer/Counter A 8-Bit Timer/Counter B Two Power-Down Modes 16-Bit Timer/Counter 0 Interrupts 16-Bit Timer/Counter 1 • • • • • • • • • • • • Programmable 16-bit timer Interval, capture, PWM mode Match/capture, overflow interrupt Programmable detection voltage (2.2 V, 2.4 V, 3.0 V, 4.0 V) En/Disable S/W selectable 400 ns at 10 MHz (main) 122 us at 32.768 kHz (subsystem) -40 °C to 85 °C 1.8 V to 5.5 V 80-pin QFP 80-pin TQFP S3C8247 (ROM 24K-byte) Watch Timer • • • • • • • • • • • • • • • • Real-time and interval time measurement Clock generation for LCD Four frequency outputs for buzzer sound Maximum 16-digit LCD direct drive capability Display modes: static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) Eight analog input channels 50 µs conversion speed at 1 MHz fADC clock 10-bit conversion resolution 8-bit transmit/receive mode 8-bit receive mode LSB-first/MSB-first transmission selectable Internal/external clock source LCD display voltage supply S/W control en/disable 3.0 V drive Voltage Detector LCD Controller/Driver Instruction Execution Times Operating Temperature Range Operating Voltage Range Package Type A/D Converter 8-Bit Serial I/O Interface S3C8249’s ROM version device S3C8245’s ROM version device • S3C8248 (ROM 8K-byte) Voltage Booster 1-2 S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW BLOCK DIAGRAM XIN XTIN TAOUT/TAPWM/P3.1 TACLK/P3.2 TACAP/P3.3 8-Bit Timer/ Counter A 8-Bit Timer/ Counter B 16-Bit Timer/ Counter 0 T1CAP/P1.0 T1CLK/P1.1 T1OUT/T1PWM/P1.2 P0.0-P0.7/ INT0-INT7 P1.0-P1.7 AVREF AVSS P2.0-P2.7/ ADC0-ADC7 P3.0-P3.4 16-Bit Timer/ Counter 1 I/O Port 0 I/O Port 1 A/D Converter I/O Port 4 I/O Port 2 I/O Port 3 544/1056 Byte Register File 16/32-Kbyte ROM I/O Port 5 P5.0-P5.7 SAM88 RC CPU LCD Driver RESET XOUT XTOUT BUZ/P1.4 Voltage Detector OSC/ RESET Basic Timer Watch Timer VVLDREF TBPWM/P3.0 Voltage Booster CB CA VLC0-VLC2 COM0-COM3 SEG0-SEG15 SEG16-SEG31 I/O Port and Interrupt Control Serial I/O Port SI/P1.7 SO/P1.5 SCK/P1.6 P4.0-P4.7 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 PIN ASSIGNMENT SEG26/P5.2 SEG27/P5.3 SEG28/P5.4 SEG29/P5.5 SEG30/P5.6 SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3.2/TACLK P3.3/TACAP/SDAT P3.4/SCLK VDD VSS XOUT XIN TEST XTIN XTOUT RESET P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 S3C8248/C8245 /C8247/C8249 (80-QFP-1420C) SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 CA CB AVSS AVREF P2.7/ADC7/VVLDREF P2.6/ADC6 P2.5/ADC5 Figure 1-2. S3C8248/C8245/C8247/C8249 Pin Assignments (80-QFP) 1-4 P0.5/INT5 P0.6/INT6 P0.7/INT7 P1.0/T1CAP P1.1/T1CLK P1.2/T1OUT/T1PWM P1.3 P1.4/BUZ P1.5/SO P1.6/SCK P1.7/SI P2.0/ADC0 P2.1/ADC1 P2.2/ADC3 P2.3/ADC4 P2.4/ADC4 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW SEG26/P5.2 SEG27/P5.3 SEG28/P5.4 SEG29/P5.5 SEG30/P5.6 SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3.2/TACLK P3.3/TACAP/SDAT P3.4/SCLK VDD VSS XOUT XIN TEST XTIN XTOUT RESET P0.0/INT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 S3C8248/C8245 /C8247/C8249 (80-TQFP-1212) SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 CA CB AVSS AVREF P2.7/ADC7/V VLDREF P2.6/ADC6 P2.5/ADC5 Figure 1-3. S3C8248/C8245/C8247/C8249 Pin Assignments (80-TQFP) P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 P0.5/INT5 P0.6/INT6 P0.7/INT7 P1.0/T1CAP P1.1/T1CLK P1.2/T1OUT/T1PWM P1.3 P1.4/BUZ P1.5/SO P1.6/SCK P1.7/SI P2.0/ADC0 P2.1/ADC1 P2.2/ADC3 P2.3/ADC4 P2.4/ADC4 21 22 23 24 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 1-5 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 PIN DESCRIPTIONS Table 1-1. S3C8248/C8245/C8247/C8249 Pin Descriptions Pin Names P0.0–P0.7 Pin Type I/O Pin Description I/O port with bit programmable pins; Schmitt trigger input or output mode selected by software; software assignable pull-up. P0.0–P0.7 can be used as inputs for external interrupts INT0–INT7 (with noise filter and interrupt control). I/O port with bit programmable pins; Input or output mode selected by software; Open-drain output mode can be selected by software; software assignable pull-up. Alternately P1.0–P1.7 can be used as SI, SO, SCK, BUZ, T1CAP, T1CLK, T1OUT, T1PWM I/O port with bit programmable pins; normal input and AD input or output mode selected by software; software assignable pull-up. I/O port with bit programmable pins. Input or push-pull output with software assignable pull-up. Alternately P3.0–P3.3 can be used as TACAP, TACLK, TAOUT, TAPWM, TBPWM I/O port with bit programmable pins. Push-pull or open drain output and input with software assignable pull-up. P4.0–P4.7 can alternately be used as outputs for LCD SEG Have the same characteristic as port 4 Circuit Type D–4 Pin Numbers (note) 20–27 Share Pins INT0–INT7 P1.0–1.7 I/O E–2 28-35 SI, SO, SCK, BUZ, T1CAP T1CLK T1OUT T1PWM P2.0–P2.7 I/O F–10 F–18 36–42, 43 ADC0–ADC6 VVLDREF (ADC7) TACAP TACLK TAOUT TAPWM TBPWM P3.0–P3.4 I/O D–2 7–11 P4.0–P4.7 I/O H–14 71–78 SEG16–SEG23 P5.0–P5.7 I/O H–14 79–6 SEG24–SEG31 1-6 S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW Table 1-1. S3C8248/C8245/C8247/C8249 Pin Descriptions (Continued) Pin Names ADC0–ADC6 ADC7 AVREF AVSS INT0–INT7 RESET TEST Pin Type I – – I I I Pin Description A/D converter analog input channels A/D converter reference voltage A/D converter ground External interrupt input pins System reset pin (pull-up resistor: 250 kΩ) 0 V: Normal MCU operating 5 V: Test mode 12 V: for OTP writing Serial OTP interface pins; serial data and clock Power input pins for CPU operation (internal) and Power input for OTP Writing Main oscillator pins Serial I/O interface clock signal Voltage detector reference voltage input Timer A Capture input Timer A External clock input Timer A output and PWM output Timer B PWM output Timer 1 Capture input Timer 1 External clock input Timer 1 output and PWM output LCD common signal output LCD segment output LCD segment output LCD Segment output LCD power supply 0.5, 1, 2 or 4 kHz frequency output for buzzer sound with 4.19 MHz main system clock or 32768 Hz subsystem clock Capacitor terminal for voltage booster Circuit Type F–10 F–18 – – D–4 B – Pin Numbers (note) 36–42 43 44 45 20–27 19 16 Share Pins P2.0–P2.6 P2.7 – – P0.0–P0.7 – – SDAT, SCLK VDD, VSS O – D–2 – 10, 11 12, 13 P3.3, P3.4 – XOUT, XIN SCK, SO, SI VVLDREF TACAP TACLK TAOUT/TAPWM TBPWM T1CAP T1CLK T1OUT/T1PWM COM0–COM3 SEG0–SEG15 SEG16–SEG23 SEG24–SEG31 VLC0–VLC2 BUZ – I/O I I I O O I I O O O O O O O – E–2 F–18 D–2 D–2 D–2 D–2 E–2 E–2 E–2 H H H–14 H–14 – E–2 14, 15 33–35 43 10 9 8 7 28 29 30 51–54 55–70 71–78 79–6 48–50 32 – P1.5–P1.7 P2.7 P3.3 P3.2 P3.1 P3.0 P1.0 P1.1 P1.2 – – P4.0–P4.7 P5.0–P5.7 – P1.4 CA, CB – – 46–47 – 1-7 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 PIN CIRCUITS VDD VDD Pull-up Enable Data In Output Disable P-Channel Circuit Type C I/O Figure 1-4. Pin Circuit Type B (RESET) Figure 1-6. Pin Circuit Type D-2 (P3) VDD V DD VDD Data Output Disable Pull-up Enable I/O Data P-Channel Out Pin Circuit Type C Output Disable N-Channel Noise Filter Ext.INT Input Normal Figure 1-5. Pin Circuit Type C Figure 1-7. Pin Circuit Type D-4 (P0) 1-8 S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW VDD VDD Open drain Enable VDD Pull-up Resistor Pull-up Enable P-CH Data I/O N-CH Output Disable Data Output Disable ADC & VLD Enable Data VLDREF Circuit Type C I/O Schmitt Trigger To ADC Figure 1-8. Pin Circuit Type E-2 (P1) Figure 1-10. Pin Circuit Type F-18 (P2.7/VLDREF) VDD VLC2 Pull-up Enable VLC1 Data Output Disable Circuit Type C I/O SEG/ COM Out ADCEN VLC0 Data To ADC Figure 1-9. Pin Circuit Type F-10 (P2.0–P2.6) Figure 1-11. Pin Circuit Type H (SEG/COM) 1-9 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 VLC2 VLC1 SEG Output Disable VLC0 Figure 1-12. Pin Circuit Type H-4 VDD VDD Open Drain EN Pull-up Enable Data LCD Out EN SEG Output Disable Circuit Type H-4 Figure 1-13. Pin Circuit Type H-14 (P4, P5) 1-10 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA 19 OVERVIEW ELECTRICAL DATA In this chapter, S3C8248/C8245/C8247/C8249 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.C. electrical characteristics — A.C. electrical characteristics — Oscillation characteristics — Oscillation stabilization time — Data retention supply voltage in stop mode — Serial I/O timing characteristics — A/D converter electrical characteristics 19-1 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-1. Absolute Maximum Ratings (TA= 25 °C) Parameter Supply voltage Input voltage Output voltage Output current high Symbol VDD VI VO IOH IOL TA TSTG One I/O pin active All I/O pins active Output current low One I/O pin active Total pin current for port Operating temperature Storage temperature Conditions Rating – 0.3 to +6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 18 – 60 + 30 + 100 – 40 to + 85 – 65 to + 150 °C Unit V mA Table 19-2. D.C. Electrical Characteristics (TA = -40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Operating voltage Symbol VDD Conditions f CPU = 10 MHz f CPU = 3 MHz Input high voltage VIH1 VIH2 Input low voltage VIL1 VIL2 All input pins except VIH2 XIN, XTIN All input pins except VIL2 XIN, XTIN Min 2.7 1.8 0.8 VDD VDD-0.1 – Typ – – – – – 0.2 VDD 0.1 Max 5.5 5.5 VDD Unit V 19-2 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-2. D.C. Electrical Characteristics (Continued) (TA = -40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Output high voltage Output low voltage Input high leakage current Symbol VOH VOL ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Oscillator feed back resistors Pull-up resistor ILOH ILOL Rosc1 RL1 RL2 VLC0 out voltage (Booster run mode) VLC0 Conditions VDD = 5 V; IOH = -1 mA All output pins VDD = 5 V; IOL = 2 mA All output pins VIN = VDD All input pins except ILIH2 VIN = VDD, XIN, XTIN VIN = 0 V All input pins except ILIL2 VIN = 0 V, XIN, XTIN, RESET VOUT = VDD All I/O pins and output pins VOUT = 0 V All I/O pins and output pins VDD = 5.0 V TA = 25 °C XIN = VDD, XOUT = 0 V Port 0,1,2,3,4,5 TA = 25°C TA=25 °C, RESET only VIN = 0 V; VDD = 5 V ±10% TA = 25 °C, (1/3 bias mode) TA = 25 °C, (1/2 bias mode) VLC1 out voltage (Booster run mode) VLC2 out voltage (Booster run mode) COM output voltage deviation SEG output voltage deviation VLC1 VLC2 VDC TA = 25 °C (1/2 and 1/3 bias mode) TA = 25 °C (1/3 bias mode) VDD = VLC2 = 3 V (VLCD-COMi) IO = ± 15 µA (i = 0-3) VDD = VLC2 = 3 V (VLCD-SEGi) IO = ± 15 µA (i = 0-31) VIN = 0 V; VDD = 5 V ±10 % – – 800 – – 1000 – – Min VDD–1.0 – – Typ – – – Max – 0.4 3 20 -3 -20 3 -3 1200 kΩ uA Unit V 25 50 100 110 210 310 0.9 1.0 1.1 V 1.4 2VLC0 - 0.1 3VLC0 - 0.1 – 1.5 – 1.7 2VLC0 + 0.1 3VLC0 + 0.1 ± 120 mV – ± 60 VDs – ± 60 ± 120 19-3 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-2. D.C. Electrical Characteristics (Concluded) (TA = -40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 (2) Conditions VDD = 5 V ± 10 % 10 MHz crystal oscillator 3 MHz crystal oscillator VDD = 3 V ± 10 % 10 MHz crystal oscillator 3 MHz crystal oscillator IDD2 Idle mode: VDD = 5 V ± 10 % 10 MHz crystal oscillator 3 MHz crystal oscillator Idle mode: VDD = 3 V± 10 % 10 MHz crystal oscillator 3 MHz crystal oscillator IDD3 Sub operating: main-osc stop VDD = 3 V ± 10 % 32768 Hz crystal oscillator Sub idle mode: main-osc stop VDD = 3 V ± 10 % 32768 Hz crystal oscillator Main stop mode : sub-osc stop VDD = 5 V ± 10 % VDD = 3 V ± 10 % – – Min – Typ 12 4 3 1 3 1.5 1.2 0.5 20 Max 25 10 8 5 10 4 3 1.5 40 uA Unit mA IDD4 – 7 14 IDD5 – 1 0.5 3 2 NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. IDD1 and IDD2 include a power consumption of subsystem oscillator. 3. IDD3 and IDD4 are the current when the main system clock oscillation stop and the subsystem clock is used. 4. 5. And does not include the LCD and Voltage booster and voltage level detector IDD5 is the current when the main and subsystem clock oscillation stop. Voltage booster’s operating voltage range is 2.0 V to 5.5 V. The range of 1.8 V to 2.0 V could be referenced in page 17-4. 19-4 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA In case of S3C8248/C8245, the characteristic of VOH and VOL is differ with the characteristic of S3C8247/C8249 like as following. Other characteristics are same each other. Table 19-3. D.C Electrical Characteristics of S3C8248/C8245 (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Output high voltage Symbol VOH1 VOH2 Output low voltage VOL1 VOL2 Conditions VDD = 5 V; IOH = -1 mA All output pins except VOH2 VDD = 5 V; IOH = -6 mA Port 3.0 only in S3C8248/C8245 VDD = 5 V; IOL = 2 mA All output pins except VOL2 VDD = 5 V; IOH = 12 mA Port 3.0 only in S3C8248/C8245 Min VDD-1.0 VDD-0.7 – – 0.4 0.7 Typ – Max – Unit V 19-5 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-4. A.C. Electrical Characteristics (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Interrupt input high, low width (P0.0–P0.7) RESET input low width Symbol tINTH, tINTL tRSL Conditions P0.0–P0.7, VDD = 5 V Min 200 Typ – Max Unit ns VDD = 5 V 1 – – us NOTE: User must keep more large value then min value. tTIL tTIH 0.8 VDD 0.2 VDD 0.2 VDD Figure 19-1. Input Timing for External Interrupts (Ports 0) tRSL RESET 0.2 V DD Figure 19-2. Input Timing for RESET 19-6 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-5. Input/Output Capacitance (TA = -40 °C to +85 °C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are returned to VSS Min – Typ – Max 10 Unit pF Table 19-6. Data Retention Supply Voltage in Stop Mode (TA = -40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR = 2 V Conditions Min 2 – Typ – – Max 5.5 3 Unit V uA RESET Occurs Stop Mode Data Retention Mode Oscillation Stabilization Time Normal Operating Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instrction RESET 0.2 V DD NOTE: tWAIT is the same as 4096 x 16 x 1/fxx tWAIT Figure 19-3. Stop Mode Release Timing Initiated by RESET 19-7 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Oscillation Stabilization Time Stop Mode Data Retention Mode Idle Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instruction Interrupt 0.2 VDD tWAIT Normal Operating Mode NOTE: tWAIT is the same as 4096 x 16 x BT clock Figure 19-4. Stop Mode (Main) Release Timing Initiated by Interrupts Oscillation Stabilization Time Stop Mode Data Retention Mode Idle Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instruction Interrupt 0.2 VDD tWAIT Normal Operating Mode NOTE: When the case of select the fxx/128 for basic timer input clock before enter the stop mode. tWAIT = 128 x 16 x (1/32768) = 62.5 ms Figure 19-5. Stop Mode (Sub) Release Timing Initiated by Interrupts 19-8 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-7. A/D Converter Electrical Characteristics (TA = - 40 °C to +85 °C, VDD = 1.8 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy VDD = 5 V AVREF = 5 V AVSS = 0 V Integral Error Linearity ILE DLE EOT EOB tCON VIAN RAN AVREF AVSS IADIN IADC – – – – – AVREF = VDD = 5 V AVREF = VDD = 5 V AVREF = VDD = 3 V AVREF = VDD = 5 V When power down mode – AVSS 2 2.5 VSS – – – – ±1 ±0.5 40 – 1000 – – – 1 0.5 100 ±2 ±1 ±3 ±2 – AVREF – VDD VSS + 0.3 10 3 1.5 500 nA uA mA fxx V Mohm V Symbol Conditions Min – – Typ 10 – Max – ±3 Unit bit LSB Differential Linearity Error Offset Error of Top Offset Error of Bottom Conversion time (1) Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block current (2) NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during A/D conversion. 19-9 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-8. Synchronous SIO Electrical Characteristics (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V, VSS = 0 V, fxx = 10 MHz oscillator) Parameter SCK Cycle time Serial Clock High Width Serial Clock Low Width Serial Output data delay time Serial Input data setup time Serial Input data Hold time Symbol tCYC tSCKH tSCKL tOD tID tIH Conditions – – – – – – Min 200 60 60 – 40 100 Typ – – – – – – Max – – – 50 – – Unit ns tCYC tSCKL tSCKH SCK 0.8 VDD 0.2 VDD tID tIH 0.8 VDD SI Input Data 0.2 VDD tOD SO Output Data Figure 19-6. Serial Data Transfer Timing 19-10 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-9. Main Oscillator Frequency (fOSC1) (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Clock Circuit XIN XOUT Test Condition Crystal oscillation frequency Min 1 Typ – Max 10 Unit MHz C1 C2 Ceramic XIN XOUT Ceramic oscillation frequency 1 – 10 MHz C1 C2 External clock XIN XOUT XIN input frequency 1 – 10 MHz RC XIN R XOUT r = 35 kΩ, VDD = 5 V 2 MHz Table 19-10. Main Oscillator Clock Stabilization Time (tST1) (TA = -40 °C to +85 °C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Ceramic External clock Test Condition VDD = 4.5 V to 5.5 V Stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low level width (tXH, tXL) Min – – 50 Typ – – – Max 10 4 – Unit ms ms ns NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. The RESET should therefore be held at low level until the tST1 time has elapsed 19-11 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 1 / f OSC1 tXL tXH XIN VDD – 0.5 V 0.4 V Figure 19-7. Clock Timing Measurement at XIN Table 19-11. Sub Oscillator Frequency (fOSC2) (TA = -40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Clock Circuit XTIN XTOUT R C1 C2 Test Condition Crystal oscillation frequency C1 = 22 pF, C2 = 33 pF R = 39 KΩ XTIN and XTOUT are connected with R and C by soldering. Min 32 Typ 32.768 Max 35 Unit kHz Table 19-12. Sub Oscillator(crystal) Stabilization Time (tST2) (TA = 25 °C) Oscillator normal mode Test Condition VDD = 4.5 V to 5.5 V VDD = 1.8 V to 3.0 V strong mode VDD = 4.5 V to 5.5 V VDD = 1.8 V to 3.0 V Min – – – – Typ 250 – – 250 Max 500 2 2 500 Unit ms s s ms NOTE: Oscillation stabilization time (tST2) is the time required for the oscillator to it’s normal oscillation when stop mode is released by interrupts. The value Typ and Max are measured by buzzer output signal after stop release. For example in voltage range of 4.5 V to 5.5 V of normal mode, we can see the buzzer output signal within 400 ms at our test condition. 19-12 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA fCPU 10 MHz 8 MHZ B A 3 MHZ 1 MHz 1 2 1.8 3 2.7 Supply Voltage (V) Minimum instruction clock = 1/4 x oscillator frequency 4 5 5.5 6 7 Figure 19-8. Operating Voltage Range 19-13 S3C8248/C8245/P8245/C8247/C8249/P8249 MECHANICAL DATA 20 OVERVIEW MECHANICAL DATA The S3C8248/C8245/C8247/C8249 microcontroller is currently available in 80-pin-QFP/TQFP package. 23.90 20.00 ± 0.30 ± 0.20 0-8 0.15 + 0.10 - 0.05 17.90 ± 0.30 14.00 ± 0.20 80-QFP-1420C 0.80 ± 0.20 #1 0.80 0.35 + 0.10 0.10 MAX #80 0.15 MAX 0.05 MIN (0.80) 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 20-1. Package Dimensions (80-QFP-1420C) 20-1 MECHANICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 14.00 BSC 12.00 BSC 0-7 0.09-0.20 14.00 BSC 12.00 BSC 80-TQFP-1212 #80 #1 0.50 0.17-0.27 0.08 MAX M 0.05-0.15 (1.25) 1.00 ± 0.05 1.20 MAX NOTE: Dimensions are in millimeters. Figure 20-2. Package Dimensions (80-TQFP-1212) 20-2 0.60 ± 0.15 S3C8248/C8245/P8245/C8247/C8249/P8249 S3P8245/P8249 OTP 21 OVERVIEW S3P8245/P8249 OTP The S3P8245/P8249 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8248/C8245/C8247/C8249 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P8245/P8249 is fully compatible with the S3C8248/C8245/C8247/C8249, both in function and in pin configuration. Because of its simple programming requirements, the S3P8245/P8249 is ideal as an evaluation chip for the S3C8248/C8245/C8247/C8249. 21-1 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 Figure 21-1. Pin Assignments (80-QFP) 21-2 P0.5/INT5 P0.6/INT6 P0.7/INT7 P1.0/T1CAP P1.1/T1CLK P1.2//T1OUT/T1PWM P1.3 P1.4/BUZ P1.5/SIO P1.6/SCK P1.7/SI P2.0/ADC0 P2.1/ADC1 P2.2/ADC2 P2.3/ADC3 P2.4/ADC4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEF26/P5.2 SEG27/P5.3 SEG28/P5.4 SEG29/P5.5 SEG30/P5.6 SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3.2/TACLK P3.3/TACAP/SDAT P3.4/SCLK VDD VSS XOUT XIN VPP/TEST XTIN XTOUT RESET P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 S3P8245/P8249 80-QFP (Top View) SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 CA CB AVSS AVREF P2.7/ADC7/VVLDREF P2.6/ADC6 P2.5/ADC5 S3C8248/C8245/P8245/C8247/C8249/P8249 S3P8245/P8249 OTP Table 21-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P2.0 Pin Name SDAT Pin No. 10 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip Initialization Logic power supply pin. VDD should be tied to +5 V during programming. P2.1 VPP SCLK TEST 11 16 I I RESET VDD/VSS RESET VDD/VSS 19 12/13 I – Table 21-2. Comparison of S3P8245/P8249 and S3C8248/C8245/C8247/C8249 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P8245/P8249 16K/32K-byte EPROM 1.8 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 80-QFP/80-TQFP User Program 1 time 80-QFP/80-TQFP Programmed at the factory S3C8248/C8245/C8247/C8249 16K/32K-byte mask ROM 1.8 V to 5.5 V 21-3 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P8245/P8249, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 21-3 below. Table 21-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address(A15–A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 Mode EPROM read EPROM program EPROM verify EPROM read protection NOTE: "0" means Low level; "1" means High level. Table 21-4. D.C Electrical Characteristics (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Operating voltage Symbol VDD Conditions f CPU = 10 MHz All input pins except VIH2, 3 Input high voltage VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 Output high voltage Output low voltage VOH VOL Port 4,5 XIN, XTIN All input pins except VIL2 XIN, XTIN VDD = 5 V; IOH = -1 mA All output pins VDD = 5 V; IOL = 2 mA All output pins VDD -1.0 – – – VLCD2 ≥ VDD Min 2.7 1.8 0.8 VDD 0.8 VDD VDD- 0.1 – Typ – – – – – – Max 5.5 5.5 VDD VDD VDD 0.2 VDD 0.1 – 0.4 Unit V 21-4 S3C8248/C8245/P8245/C8247/C8249/P8249 S3P8245/P8249 OTP Table 21-4. D.C. Electrical Characteristics (Continued) (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Input high leakage current Symbol ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Oscillator feed back resistors Pull-up resistor ILOH ILOL Rosc1 RL1 RL2 VLC0 out voltage (Booster run mode) VLC0 Conditions VIN = VDD All input pins except ILIH2 VIN = VDD XIN, XTIN VIN = 0 V All input pins except ILIL2 VIN = 0 V XIN, XTIN, RESET VOUT = VDD All I/O pins and Output pins VOUT = 0 V All I/O pins and Output pins VDD = 5.0 V TA = 25 °C XIN = VDD, XOUT = 0 V Port 0,1,2,3,4,5 TA = 25°C VIN = 0 V; VDD = 5 V ±10 % – – 800 – – 1000 – – Min – Typ – Max 3 20 -3 -20 3 -3 1200 kΩ uA Unit 25 50 100 VIN = 0 V; VDD = 5 V ±10% TA=25 °C, RESET only TA = 25 °C (1/3 bias mode) TA = 25 °C (1/2 bias mode) 110 210 310 0.9 1.0 1.1 V 1.4 2VLC0 - 0.1 3VLC0 - 0.1 – 1.5 – 1.7 2VLC0 + 0.1 3VLC0 + 0.1 ± 120 mV VLC1 out voltage (Booster run mode) VLC2 out voltage (Booster run mode) COM output voltage deviation SEG output voltage deviation VLC1 VLC2 VDC TA = 25 °C TA = 25 °C VDD = VLC2 = 3 V (VLC-COMi) IO = ± 15 µA (1 = 0–3) VDD = VLC2 = 3 V (VLC-COMi) IO = ± 15 µA (1 = 0–3) – ± 60 VDs – ± 60 ± 120 21-5 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 Table 21-4. D.C. Electrical Characteristics (Concluded) (TA = -40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 (2) Conditions VDD = 5 V ± 10 % 10 MHz crystal oscillator 3 MHz crystal oscillator VDD = 3 V ± 10 % 10 MHz crystal oscillator 3 MHz crystal oscillator IDD2 Idle mode: VDD = 5 V ± 10 % 10 MHz crystal oscillator 3 MHz crystal oscillator Idle mode: VDD = 3 V± 10 % 10 MHz crystal oscillator 3 MHz crystal oscillator IDD3 Sub operating: main-osc stop VDD = 3 V ± 10 % 32768 Hz crystal oscillator Sub idle mode: main-osc stop VDD = 3 V ± 10 % 32768 Hz crystal oscillator Main stop mode : sub-osc stop VDD = 5 V ± 10 % VDD = 3 V ± 10 % – Min – Typ 12 4 3 1 3 1.5 1.2 0.5 20 Max 25 10 8 5 10 4 3 1.5 40 uA Unit mA IDD4 – 7 14 IDD5 – 1 0.5 3 2 NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. IDD and IDD2 include a power consumption of subsystem oscillator. 3. IDD3 and IDD4 are the current when the main system clock oscillation stop and the subsystem clock is used. 4. IDD5 is the current when the main and subsystem clock oscillation stop. 21-6 S3C8248/C8245/P8245/C8247/C8249/P8249 S3P8245/P8249 OTP case of S3P8245, the characteristic of VOH and VOL is differ with the characteristic of S3P8249 like as bellow. Other characteristics are same each other. Table 21-5. D.C Electrical Characteristics of S3C8248/C8245 (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Output high voltage Symbol VOH1 VOH2 Output low voltage VOL1 VOL2 Conditions VDD = 5 V; IOH = -1 mA All output pins except VOH2 VDD = 5 V; IOH = -6 mA Port 3.0 only in S3P8245 VDD = 5 V; IOL = 2 Ma All output pins except VOL2 VDD = 5 V; IOH = 12 mA Port 3.0 only in S3P8245 Min VDD-1.0 VDD-0.7 – – 0.4 0.7 Typ – Max – Unit V 21-7 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 fCPU 10 MHz 8 MHZ B A 3 MHZ 1 MHz 1 2 1.8 3 2.7 Supply Voltage (V) Minimum instruction clock = 1/4 x oscillator frequency 4 5 5.5 6 7 Figure 21-2. Operating Voltage Range 21-8