S3C8454

S3C8454/P8454 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM87 RC PRODUCT FAMILY Samsung's new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Timer/counters with selectable operating modes are included to support real-time operations. Many SAM87RC microcontrollers have an external interface that provides access to external memory and other peripheral devices. The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C8454 MICROCONTROLLER The S3C8454 single-chip microcontroller is fabricated using a highly advanced CMOS process. Its design is based on the powerful SAM87RC CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. The size of the internal register file is logically expanded, increasing the addressable on-chip register space to 1040 bytes. A flexible yet sophisticated external interface is used to access up to 64-Kbytes of program and data memory. The S3C8454 is a versatile microcontroller that is ideal for use in a wide range of general-purpose applications such as CD-ROM/DVD-ROM drives. Using the SAM87RC modular design approach, the following peripherals were integrated with the SAM87RC CPU core: — Five configurable 8-bit general I/O ports — One 2-bit general I/O ports — Full-duplex serial data port with one synchronous operating modes — Two 8-bit timers with interval timer — Two 16-bit timers/counters with PWM operating modes or capture modes — One voltage level detector pin — Four embedded chip selection pins (CS0–CS4) or normal I/O ports — Two programmable 8-bit PWM modules with corresponding output pins — A/D converter with 4 selectable input pins OTP The S3C8454 microcontroller is also available in OTP(One Time Programmable) version, S3P8454 The S3P8454 microcontroller has an on-chip 4K-byte one-time-programmable EPROM instead of masked ROM. The S3P8454 is comparable to S3C8454, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW KS88C4504/P4504 FEATURES CPU • SAM87RC CPU core General I/O Ports • • Memory • • 1040-byte internal register file 4-Kbyte internal program memory Interrupts • External Interface • • • 64 Kbyte external data memory 64 Kbyte external program memory area (ROMless) 60 Kbyte external program memory and 4 Kbyte internal program memory • • Six edge-driven external interrupts Two level-driven external interrupts Fast interrupt mode processing • Five 8-bit general I/O ports (port 0, 1, 2, 3, 4) One 2-bit general I/O port (port 5) Port 2 can drive LED directly PWM • • • Four output channels (PWM0, PWM1, TCPWM, TDPWM) 8-bit resolution with a 4-bit prescaler (PWM0, PWM1) From 16-bit counter (Timer C/D) (TCPWM, TDPWM) ADC • • SIO • • • • 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock mode Can be used as a general input/output port 8-bit resolution four channels Embedded chip selection • To reduce interface glue logic, chip selection logic is bold Voltage level detector • To prevent MCU from malfunctioning in an unstable power level, a voltage level detector circuit is inserted 8-bit Timers • Two 8-bit timers with interval timer mode (Timer A and B) Operating Voltage Range • 2.7 V to 5.5 volts (@12 MHz) 16-bit Timer/Counters • • • • Two programmable 16-bit timer/counters Interval, or event counter mode operation 16-bit capture and 16-bit PWM mode Internal or external clock source Operating Temperature Range • – 40 °C to + 85 °C Package Types • 80-pin QFP or TQFP Basic Timer (Watchdog Timer) • • Overflow signal makes a system reset 8-bit timer with interval timer mode Operating frequency • 25 MHz (4.5 V to 5.5 V) 1-2 S3C8454/P8454 PRODUCT OVERVIEW BLOCK DIAGRAM External Address/Data (A8-A15) (A0-A7) (D0-D7) External Interface Block RESET EA P5.1 P5.0(WAIT ) SAM8 BUS Port 0 Port 5 Port I/O & Interrupt Control Watchdog Timer P0.0-P0.3 P0.4-P0.7/ ADC0-ADC3 P4.0-P4.7/ CS0-CS4 Port4/ Chip Selection Logic Port 1 P1.0-P1.4 P1.5-P1.7/ SI, SO, SCK Timers A and B SAM87 RC CPU Port 2 P2.0-P2.7/ INT0-INT7 TCCK TDCK TCOUT TDOUT SO SI SCK Timers C and D 1040-Byte Register File P3.0-P3.7/ TDCK, TCCK TDCAP, TCCAP TCOUT, TDOUT PWM0, PWM1 Serial Port Port 3 SAM8 BUS AVSS (Internal) AVREF VDD1, VSS1 VDD2, VSS2 PWM Module A/D Converter 4-Kbyte ROM ADC0/P0.4ADC3/P0.7 PWM0 PWM1 Figure 1-1. S3C8454 Block Diagram 1-3 PRODUCT OVERVIEW KS88C4504/P4504 PIN ASSIGNMENT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PM DM RD WR VLD P5.1 P5.0/WAIT CS3/P4.7 CS2/P4.6 CS1/P4.5 CS0/P4.4 VDD1 VSS1 XOUT XIN EA P4.3 P4.2 RESET P4.1 P4.0 PWM1/P3.7 PWM0/P3.6 TDOUT/P3.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 KS88C4504 80-QFP (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D7 D6 D5 D4 D3 D2 D1 D0 P0.0 P0.1 P0.2 VDD2 VSS2 P0.3 AVREF P0.4/ADC0 P0.5/ADC1 P0.6/ADC2 P0.7/ADC3 P1.0 P1.1 P1.2 P1.3 P1.4 Figure 1-2. S3C8454 Pin Assignments 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P1.5/SI P1.6/SO P1.7/SCK P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P3.0/TDCK P3.1/TCCK/ P3.2/TDCAP P3.3/TCCAP P3.4/TCOUT 1-4 S3C8454/P8454 PRODUCT OVERVIEW PIN ASSIGNMENTS (Continued) D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PM DM RD WR VLD P5.1 P5.0/WAIT CS3/P4.7 CS2/P4.6 CS1/P4.5 CS0/P4.4 VDD1 VSS1 XOUT XIN EA P4.3 P4.2 RESET P4.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 KS88C4504 80-TQFP (Top View) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D3 D2 D1 D0 P0.0 P0.1 P0.2 VDD2 VSS2 P0.3 AVREF P0.4/ADC0 P0.5/ADC1 P0.6/ADC2 P0.7/ADC3 P1.0 P1.1 P1.2 P1.3 P1.4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.5/SI P1.6/SO P1.7/SCK P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P3.0/TDCK P3.1/TCCK/ P3.2/TDCAP P3.3/TCCAP P3.4/TCOUT TDOUT/P3.5 PWM0/P3.6 PWM1/P3.7 P4.0 Figure 1-3. S3C8454 Pin Assignments 1-5 PRODUCT OVERVIEW KS88C4504/P4504 PIN DESCRIPTIONS Table 1-1. S3C8454/P8454 Pin Descriptions Pin Name P0.0–P0.7 Pin Type I/O Pin Description Bit programmable port; input or output mode selected by software; normal input or push-pull output with software assignable pull-up (P0.0–P0.3) or pull-down (P0.4–P0.7). Alternately, P0.4–P0.7 can be use as a ADC input port with 8-bit resolution. Bit programmable port; input or output mode selected by software; normal input or push-pull output with software assignable pull-up. P1.5–P1.7 can be used as a synchronous SIO port P1.5/SI P1.6/SO P1.7/SCK General I/O port with normal input or push-pull output with software; assignable pull-up. Bit programmable. Alternately, P2.0–P2.7 can be used as inputs for external interrupts, INT0–INT7 (with noise filter and interrupt control). INT0/INT1 is level interrupts. General I/O port with bit programmable pins. Normal input or push-pull output with software assignable pull-up. Input or output mode is selectable by software. Respectively, each pin can serve as (with noise filters): P3.0/timer D clock input (TDCK) P3.1/timer C clock input (TCCK) P3.2/timer D capture input (TDCAP) P3.3/timer C capture input (TCCAP) P3.4/timer C out (TCOUT)/PWM out (TCPWM) P3.5/timer D out (TDOUT)/PWM out (TDPWM) P3.6/PWM0 output port P3.7/PWM1 output port General I/O port with bit programmable pins. Normal input or push-pull output with software assignable pull-up. Input or output mode is selectable by software. P4.0–P4.7 can alternately be used as inputs for embedded chip selection output. P4.4/CS0 P4.5/CS1 P4.6/CS2 P4.7/CS3 Circuit Type 2, 3 Pin Number 56–54, 51, 49–46 Share Pins ADC0– ADC3 P1.0–P1.7 I/O 3 45–38 SI, SO, SCK P2.0–P2.7 I/O 4 37–30 INT0– INT7 P3.0–P3.7 I/O 3, 5 29–22 TDCK TCCK TDCAP TCCAP TDOUT/ TDPWM TCOUT/ TCPWM PWM0 PWM1 P4.0–P4.7 I/O 3, 5 21, 20, 18, 17, 11–8 CS0–CS3 1-6 S3C8454/P8454 PRODUCT OVERVIEW Table 1-1. S3C8454/P8454 Pin Descriptions (Continued) Pin Name P5.0–P5.1 Pin Type I/O Pin Description General I/O port with bit programmable pins. Normal input or push-pull, output mode. Alternately It can use as external interface control signal P5.0/WAIT signal Analog input pins for A/D converter module. Alternatively used as general-purpose I/O A/D converter reference voltage AVSS is connected to ground internally Pulse width modulation output pins External interrupt input pins External clock input for timer C and timer D Timer C/ timer D capture input Input pin for the slow memory timing signal from the external interface System reset pin (pull-up resistor: 240 kΩ) 5V: ROMless operating 0V: internal 4 K and external 60 K addressing mode Power input pins for CPU operation (internal) and Power input for OTP writing Power input pins for port output (external) Main oscillator pins synchronous SIO communication port Address output for external device Data I/O for external device External memory selection output Memory read/write output Embedded chip selection output 16-bit timer PWM mode output Voltage Level Detect Pin 5 4 3 3 5 1 – Circuit Type 5 QFP Pin Number 7 Share Pins WAIT ADC0–ADC3 AVREF PWM0, PWM1 INT0–INT7 TCCK, TDCK TCCAP,TDCAP WAIT RESET I – O I I I I I I 2 49–46 50 23,22 37–30 28,29 26,27 7 19 16 P0.4–P0.7 – P3.6, P3.7 P2.0–P2.7 P3.1/P3.0 P3.3/P3.2 P5.0 – – EA VDD1, VSS1 VDD2, VSS2 XIN, XOUT SI, SO, SCK A0–A15 D0–D7 PM,DM RD,WR CS0–CS3 TCOUT,TDOUT VLD – – – I/O O I/O O O O O – – – – 3 6 7 – – 5 5 – 12,13 53, 52 15, 14 40,39,38 65–80 57–64 1, 2 3, 4 11–8 25, 24 5 – – – P1.5/P1.6 P1.7 – – – – P4.4–P4.7 P3.4, P3.5 – NOTE: VDD1 must be connected to VDD2 in users application circuit, VSS1 & VSS2 also. 1-7 PRODUCT OVERVIEW KS88C4504/P4504 PIN CIRCUITS Table 1-2. Pin Circuit Assignments for the S3C8454/P8454 Circuit Number 1 2 3 4 5 6 7 Circuit Type Input I/O I/O I/O I/O Output I/O RESET pin S3C8454 Assignments A/D converter input pins, ADC0–ADC3, P0.4–P0.7 Port 0, 1, 3, 4, and 5 P2 (INT0–INT7) P3 (TDCK, TCCK, TDCAP, TCCAP, TCOUT, TDOUT, TCPWM, TDPWM, PWM0, PWM1) A0–A15,PM, DM, RD, WR D0–D7 1-8 S3C8454/P8454 PRODUCT OVERVIEW VDD Pull-up Resistor (Typical 240 kΩ) Input Figure 1-4. Pin Circuit Type 1 (RESET) VDD Data I/O Output Disable Vss Normal Input ADC Port Selection ADC In Pull-Down Enable Enable ADC Figure 1-5. Pin Circuit Type 2 (ADC0–ADC3) 1-9 PRODUCT OVERVIEW KS88C4504/P4504 VDD Pull-Up Enable VDD Data I/O Output Disable Normal Input SCK Input Noise Filter Figure 1-6. Pin Circuit Type 3 VDD Pull-Up Resistor Pull-Up Enable VDD Data I/O Output Disable Vss External Interrupt Input Normal Input Noise Filter Figure 1-7. Pin Circuit Type 4 1-10 S3C8454/P8454 PRODUCT OVERVIEW VDD Pull-Up Resistor Pull-Up Enable VDD Selection bits for ports or other function Data Output Disable Vss Input Other Function I/O Figure 1-8. Pin Circuit Type 5 VDD In Out Figure 1-9. Pin Circuit Type 6 1-11 PRODUCT OVERVIEW KS88C4504/P4504 VDD Data I/O Output Disable Normal Input Figure 1-10. Pin Circuit Type 7 1-12 S3C8454/P8454 ELECTRICAL DATA 18 OVERVIEW — I/O capacitance ELECTRICAL DATA In this section, S3C8454 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Oscillation characteristics — Oscillation stabilization time 18-1 ELECTRICAL DATA S3C8454/P8454 Table 18-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply voltage Input voltage Output voltage Output current high Output current low Operating temperature Storage temperature Symbol VDD VI VO I OH I OL TA TSTG All ports (in input mode) All ports (in output mode) One I/O pin active All I/O pins active One I/O pin active Total pin current for port Conditions Rating – 0.3 to + 6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 18 – 60 + 30 + 100 – 40 to +85 – 65 to +150 °C °C Unit V V mA mA 18-2 S3C8454/P8454 ELECTRICAL DATA Table 18-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V) Parameter Operating voltage Symbol VDD Conditions f OSC = 25 MHz (instruction clock = 6.25 MHz) f OSC = 12 MHz (instruction clock = 3 MHz) Input high voltage VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH All input pins except VIH2, VIH3 XIN Test, RESET All input pins except VIL2, VIL3 XIN Test, RESET VDD= 5 V IOH = – 1 mA IOH = – 100 uA Output low voltage VOL1 VDD = 5 V IOL = 2 mA All output pins except port 2 VDD = 5 V IOL = 15 mA, port 2 VIN = VDD All input pins except XIN VIN = VDD XIN VIN = 0 V All input pins except XIN and RESET ILIL2 Output high leakage current Output low leakage current Pull-up and pull-down resistor ILOH ILOL RL1 RL2 VIN = 0 V, XIN, RESET VOUT = VDD All I/O pins and output pins VOUT = 0 V All I/O pins and output pins VIN = 0 V; VDD = 5 V ± 10% Ports 0-5, TA = 25 °C VIN = 0 V; VDD = 5 V ± 10% TA = 25 °C, RESET only – – 30 120 – –0 46 240 5 –5 80 320 kΩ – 20 – – 0.2VDD VDD – 1.0 VDD – 0.5 – – – – Min 4.5 2.7 0.51 VDD VDD – 0.5 0.8VDD – – 0.2 VDD 0.4 – – – 0.4 V V V Typ – – – Max 5.5 5.5 VDD V Unit V VOL2 Input high leakage current ILIH1 ILIH2 Input low leakage current ILIL1 – – 0.5 – 1.0 3 20 –3 µA 18-3 ELECTRICAL DATA S3C8454/P8454 Table 18-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V) Parameter Supply current (note) Symbol IDD1 Conditions VDD = 5 V ± 10 % 20 MHz oscillation VDD = 2.7 V 12 MHz oscillation IDD2 Idle mode; VDD = 5 V ± 10 % 20 MHz oscillation Idle mode; VDD = 2.7 V 12 MHz oscillation IDD3 Stop mode; VDD = 5 V ± 10 % Min Typ 20 7 8 3 110 Max 40 14 16 6 220 µA Unit mA LVD enable, TA = 25 °C NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. Table 18-3. A.C. Electrical Characteristics (TA = -40 °C to + 85 °C) Parameter Interrupt input high, low width (P2.0–P2.7) RESET input low width Symbol tINTH, tINTL tRSL Conditions VDD = 5 V Min 180 Typ – Max – Unit nS VDD = 5 V 1000 – – nS NOTES: 1. The unit tCPU means one CPU clock period. 2. The oscillator frequency is the same as the CPU clock frequency. tINTL tINTH 0.8 VDD 0.2 VDD Figure 18-1. Input Timing for External Interrupts (Ports 2) 18-4 S3C8454/P8454 ELECTRICAL DATA tRSL RESET 0.2 VDD Figure 18-2. Input Timing for RESET RESET Table 18-4. Input/Output Capacitance (TA = – 40 °C to + 85 °C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min – Typ – Max 10 Unit pF Table 18-5. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Stop mode, VDDDR = 2.0 V Conditions Min 2 – Typ – – Max 5.5 50 Unit V µA NOTES: 1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped. 2. Supply current does not include drawn through internal pull–up resistors and external output current loads. 18-5 ELECTRICAL DATA S3C8454/P8454 Reset Occurs Oscillation Stabilization Time Normal Operating Mode ~ ~ ~ ~ Stop Mode Data Retention Mode VDD VDDDR Execution of STOP Instrction RESET 0.2 VDD NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. tWAIT Figure 18-3. Stop Mode Release Timing Initiated by RESET RESET 18-6 S3C8454/P8454 ELECTRICAL DATA Table 18-6. A/D Converter Electrical Characteristics (TA = – 40 °C to + 85 °C) Parameter Resolution Total accuracy Integral linearity error Integral linearity error Offset error of top Offset error of bottom Conversion time (1) Symbol Conditions VDD = 5 V Min – – Typ 8 – – – ±1 ± 0.5 Max – ±2 ±1 ±1 ±2 ±2 Unit bit LSB ILE DLE EOT EOB tCON VIAN RAN AVREF AVSS IADIN IADC Conversion time = 5 us AVREF = 5 V AVSS = 0 V 17 AVss – – – AVREF = VDD = 5 V AVREF = VDD = 5 V AVREF = VDD = 3 V AVREF = VDD = 5 V When power down mode 2 2.5 VSS – – – 1000 – – – 1 0.5 100 170 AVREF – VDD VSS+ 0.3 10 3 1.5 500 µs V MΩ V V uA mA mA nA Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block current (2) NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during A/D conversion. 18-7 ELECTRICAL DATA S3C8454/P8454 VDD Reference Voltage Input R AVREF 10 pF + C 103 VDD Analog Input Voltage C 101 ADC0-ADC3 S3C8454 VSS NOTE: The symbol 'R' signifies an offset resistor with a value of from 50 to 100. If this resistor is omitted, the absolute accuracy will be maximum of 3 LSBs. Figure 18-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy 18-8 S3C8454/P8454 ELECTRICAL DATA Table 18-7. Synchronous SIO Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 4.5 V to 5.5 V, VSS = 0 V, fOSC = 10 MHz oscillator) Parameter SCK cycle time Serial clock high width Serial clock low width Serial output data delay time Serial input data set up time Serial input data hold time Symbol tCYC tSCKH TSCKL TOD TID TIH Conditions – – – – – – Min 200 60 60 – 40 100 Typ – – – – – – Max – – – 50 – – Unit nS tCYC tSCKL SCK 0.8 VDD 0.2 VDD tID tIH 0.8 VDD SI Input Data 0.2 VDD tOD tSCKH SO Output Data Figure 18-5. Serial Data Transfer Timing 18-9 ELECTRICAL DATA S3C8454/P8454 Table 18-8. Main Oscillator Frequency (fOSC1) (TA = – 40 °C + 85 °C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Clock Circuit XIN XOUT Test Condition CPU clock oscillation frequency Min 4 Typ – Max 25 Unit MHz C1 C2 Ceramic XIN XOUT CPU clock oscillation frequency 4 – 25 MHz C1 C2 External clock XIN XOUT XIN input frequency 4 – 25 MHz Table 18-9. Main Oscillator Clock Stabilization Time (tST1) (TA = -40 °C + 85 °C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Ceramic External clock Test Condition VDD = 4.5 V to 5.5 V Stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low level width (tXH, tXL) Min – – 50 Typ – – – Max 10 4 – Unit ms ms ns NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. The RESET should therefore be held at low level until the tST1 time has elapsed. 18-10 S3C8454/P8454 ELECTRICAL DATA 1/fOSC1 tXL tXH XIN VDD - 0.5 V 0.4 V Figure 18-6. Clock Timing Measurement at XIN Table 18-10. Characteristics of Voltage Level Detect circuit (TA = – 40 °C + 85 °C) Parameter Operating Voltage of VLD Detect Voltage Current consumption Symbol VDDVLD VVLD IVLD Conditions – – VDD = 5.5 V Min 2.7 1.15 – Typ – 1.40 100 Max 5.5 1.51 200 Unit V V uA 18-11 ELECTRICAL DATA S3C8454/P8454 fOSC 25 MHz B fCPU 6.25 MHz 18 MHz 16 MHz 14 MHz 12 MHz A 4.5 MHz 4 MHz 3.5 MHz 3 MHz 4 MHz 1 2 3 2.7 4 4.5 5 6 7 1 MHz Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 18-7. Operating Voltage Range 18-12 S3C8454/P8454 MECHANICAL DATA 19 OVERVIEW MECHANICAL DATA The S3C8454 microcontroller is available in a 80-pin QFP package (80-QFP-1420C) and a 80-pin TQFP package (80-TQFP-1212AN). 23.90 ± 0.30 20.00 ± 0.20 0-8 + 0.10 0.15 - 0.05 17.90 ± 0.30 14.00 ± 0.20 80-QFP-1420C 0.80 ± 0.20 #1 0.80 0.35 + 0.10 0.15 MAX 0.10 MAX #80 0.05 MIN (0.80) 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 19-1. 80-QFP-1420C Package Dimensions 19-1 MECHANICAL DATA S3C8454/P8454 14.00 BSC 12.00 BSC 0-7 0.09-0.20 14.00 BSC 12.00 BSC 80-TQFP-1212 #80 #1 0.50 0.17-0.27 0.05-0.15 (1.25) 1.00 ± 0.05 1.20 MAX NOTE: Dimensions are in millimeters. Figure 19-2. 80-TQFP-1212AN Package Dimensions 19-2 0.60 ± 0.15 S3C8454/P8454 S3P8454 OTP 20 OVERVIEW S3P8454 OTP The S3P8454 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8454 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data format. S3P8454 is fully compatible with S3C8454, both in function and in pin configuration. As it has simple programming requirements, S3P8454 is ideal for use as an evaluation chip for the S3C8454. 20-1 S3P8454 OTP S3C8454/P8454 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PM DM RD WR VLD P5.1 P5.0/WAIT CS3/P4.7 CS2/P4.6 SDAT/CS1/P4.5 SCLK/CS0/P4.4 VDD1/VDD1 VSS1/VSS1 XOUT XIN VPP/EA P4.3 P4.2 RESET/RESET P4.1 P4.0 PWM1/P3.7 PWM0/P3.6 TDOUT/P3.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3P8454 80-QFP (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D7 D6 D5 D4 D3 D2 D1 D0 P0.0 P0.1 P0.2 VDD2 VSS2 P0.3 AVREF P0.4/ADC0 P0.5/ADC1 P0.6/ADC2 P0.7/ADC3 P1.0 P1.1 P1.2 P1.3 P1.4 NOTE: Figure 20-1. S3P8454 Pin Assignments (80-QFP Package) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P1.5/SI P1.6/SO P1.7/SCK P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P3.0/TDCK P3.1/TCCK P3.2/TDCAP P3.3/TCCAP P3.4/TCOUT The bolds indicates OTP pin name. 20-2 S3C8454/P8454 S3P8454 OTP D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PM DM RD WR VLD P5.1 P5.0/WAIT CS3/P4.7 CS2/P4.6 SDAT/CS1/P4.5 SCLK/CS0/P4.4 VDD1/VDD1 VSS1/VSS1 XOUT XIN VPP/EA P4.3 P4.2 RESET/RESET P4.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3P8454 80-TQFP (Top View) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D3 D2 D1 D0 P0.0 P0.1 P0.2 VDD2 VSS2 P0.3 AVREF P0.4/ADC0 P0.5/ADC1 P0.6/ADC2 P0.7/ADC3 P1.0 P1.1 P1.2 P1.3 P1.4 Figure 20-2. S3P8454 Pin Assignments (80-TQFP Package) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.5/SI P1.6/SO P1.7/SCK P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P3.0/TDCK P3.1/TCCK P3.2/TDCAP P3.3/TCCAP P3.4/TCOUT TDOUT/P3.5 PWM0/P3.6 PWM1/P3.7 P4.0 20-3 S3P8454 OTP S3C8454/P8454 Table 20-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P4.5 P4.4 EA Pin Name SDAT SCLK VPP Pin No. 10 11 16 I/O I/O I I During Programming Function Serial data pin (Output when reading, Input when writing) Input and push-pull output port can be assigned. Serial clock pin (Input only pin) EPROM cell writing power supply pin (Indicates OTP mode entering) When writing 12.5 V is applied and when reading 5 V is applied (Option). Chip Initialization Logic Power Supply Pin. VDD should be tied to 5 V during programming. RESET VDD1/VSS1 RESET VDD/VSS 19 12/13 I I Table 20-2. Comparison of S3P8454 and S3C8454 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P8454 4 Kbyte EPROM 2.7 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5V 80 QFP, 80 TQFP User Program 1 time 80 QFP, 80 TQFP Programmed at the factory 2.7 V to 5.5V S3C8454 4 Kbytes mask ROM OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of S3P8454, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 20-3 below. Table 20-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG /MEM 0 0 0 1 Address (A15–A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode NOTE: "0" means Low level; "1" means High level. 20-4 S3C8454/P8454 S3P8454 OTP D.C. ELECTRICAL CHARACTERISTICS Table 20-4. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V) Parameter Operating voltage Symbol VDD Conditions f OSC = 25 MHz (instruction clock = 6.25 MHz) f OSC = 12 MHz (instruction clock = 3 MHz) Input high voltage VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH All input pins except VIH2, VIH3 XIN Test, RESET All input pins except VIL2, VIL3 XIN Test, RESET VDD= 5 V IOH = – 1 mA IOH = – 100 uA Output low voltage VOL1 VOL2 Input high leakage current ILIH1 ILIH2 Input low leakage current ILIL1 VDD = 5 V, IOL = 2 mA All output pins except port 2 VDD = 5 V, IOL = 15 mA, port 2 VIN = VDD All input pins except XIN VIN = VDD, XIN VIN = 0 V All input pins except XIN and RESET ILIL2 Output high leakage current Output low leakage current Pull-up and pull-down resistor ILOH ILOL RL1 RL2 VIN = 0 V, XIN, RESET VOUT = VDD All I/O pins and output pins VOUT = 0 V All I/O pins and output pins Ports 0-5, TA = 25 °C VIN = 0 V; VDD = 5 V ± 10% VIN = 0 V; VDD = 5 V ± 10% TA = 25 °C, RESET only – – 30 – –0 46 – 20 5 –5 80 kΩ – – 0.2VDD VDD – 1.0 VDD – 0.5 – – – – – – 0.5 – Min 4.5 2.7 0.51 VDD VDD – 0.5 0.8VDD – – 0.2 VDD 0.4 – – – 0.4 1.0 3 20 –3 µA V V V Typ – – – Max 5.5 5.5 VDD V Unit V 120 240 320 20-5 S3P8454 OTP S3C8454/P8454 Table 20-4. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V) Parameter Output high leakage current Output low leakage current Pull-up and pulldown resistor Symbol ILOH ILOL RL1 RL2 Supply current (note) IDD1 Conditions VOUT = VDD All I/O pins and output pins VOUT = 0 V All I/O pins and output pins Ports 0-5, TA = 25 °C VIN = 0 V; VDD = 5 V ± 10 % VIN = 0 V; VDD = 5 V ± 10 % TA = 25 °C, RESET only VDD = 5 V ± 10 % 20 MHz oscillation VDD = 2.7 V 12 MHz oscillation IDD2 Idle mode; VDD = 5 V ± 10 % 20 MHz oscillation Idle mode; VDD = 2.7 V 12 MHz oscillation IDD3 Stop mode; VDD = 5 V ± 10%, LVD enable – 20 7 8 3 110 40 14 16 6 220 µA mA Min – – 30 Typ – –0 46 Max 5 –5 80 kΩ Unit µA 120 240 320 NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. 20-6