S3C9428

S3C9424/C9428/P9428 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM87RI PRODUCT FAMILY Samsung’s SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. S3C9424/C9428/P9428 MICROCONTROLLER The S3C9424/C9428/P9428 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM87Ri CPU core. The S3C9424/C9428/P9428 is a versatile microcontroller, with its A/D converter, SIO, IIC and a zero-crossing detection capability it can be used in a wide range of general purpose applications. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9424/C9428/P9428 have 4K-byte or 8K-byte of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM. Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core: • • • • • • • Four configurable I/O ports (24 pins) Nine interrupt sources with one vector and one interrupt level Two 8-bit timer/counter with various operating modes Analog to digital converter with 12 input channels and 10-bit resolution One synchronous SIO module One IIC module Two 12-bit PWM output The S3C9424/C9428/P9428 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, PWM, ADC, SIO, IIC, ZCD and capture functions. S3C9424/C9428/P9428 is available in a 28/32-pin SOP and a 30-pin SDIP package. OTP The S3P9428 is an OTP (One Time Programmable) version of the S3C9424/C9428 microcontroller. The S3P9428 has on-chip 8-K-byte one-time-programmable EPROM instead of masked ROM. The S3P9428 is fully compatible with the S3C9424/C9428, in function, in D.C. electrical characteristics and in pin configuration. 1-1 PRODUCT OVERVIEW S3C9424/C9428/P9428 FEATURES CPU • SAM87RI CPU core Timer/Counters • • Memory • • 208-byte general purpose register area (RAM) 4K/8K byte internal program memory (ROM) PWM module Instruction Set • • 41 instructions The SAM87RI core provides all the SAM87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction • • • 12-bit PWM 2-ch (Max: 250KHz) 6-bit base + 6-bit extension frame One 8-bit timer/counter • One 8-bit basic timer for watchdog function One 8-bit timer/counter with three operating mode One 8-bit timer/counter A/D Converter • 12 analog input pins 10-bit conversion resolution • Instruction Execution Time • 375 ns at 16 MHz fosc(minimum) Buzzer Frequency Range Interrupts • • 9 interrupt sources and 1 vector One interrupt level Oscillator Freqeuncy • General I/O • • Four I/O ports (total 24pins) Bit programmable ports • 1-MHz to 16-MHz external crystal oscillator Maximum 16-MHz CPU clock RC: 4MHz(typ) • 200 Hz to 20 kHz signal can be generated Operating Temperature Range • – 40°C to + 85°C Serial I/O • • One synchronous serial I/O module Selectable transmit and receive rates Operating Voltage Range • • 3.0 V to 5.5 V (LVD) 1.8 V to 5.5 V (No LVD) Multi-Master IIC-Bus • Serial peripheral interface OTP Interface Protocol Spec • Serial OTP Zero-Crossing Detection Circuit • Zero crossing detection circuit that generates a digital signal in synchronism with an AC signal input Package Types • S3C9424/C9428 32-pin SOP-450 (3V LVD) 30-pin SDIP-400 (3V LVD) 28-pin SOP-375 Built-in reset Circuit (LVD) • Low voltage detector for safe reset 1-2 S3C9424/C9428/P9428 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7 SCK,SO, SI, AD8-AD11 P1.0-P1.3 T0, BUZ, INT0, INT1 Basic Timer Port 0 Port 1 XIN XOUT T0 (CAP) T0(PWM) OSC Port I/O and Interrupt Control Port 2 P2.0-P2.7 AD0-AD7 Timer 0 Timer 1 Port 3 P3.0-P3.3 AD0-AD11 ADC SAM87RI CPU ZCD ZCD P1.1/BUZ BUZ IIC P2.7/SCLK P2.6/SDAT P0.0/SCK P0.1/SO P0.2/SI P0.7/PWM0 P1.3/PWM1 PWM 4K/8K ROM 208-Byte Register File SIO Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C9424/C9428/P9428 PIN ASSIGNMENTS VSS XIN XOUT TEST P0.1/SO P0.0/SCK RESET P3.0 P3.2 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5 AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3C9424/C9428 32-SOP (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P0.2/SI P0.3/CLO P0.4/AD8 P0.5/AD9 P0.6/AD10 P0.7/AD11/PWM0 P3.1 P3.3 P1.0/T0/ZCD P1.1/BUZ P1.2/INT0 P1.3/INT1/PWM1 P2.7/AD7/SCLK P2.6/AD6/SDAT AVREF Figure 1-2. Pin Assignment Diagram (32-Pin SOP Package) 1-4 S3C9424/C9428/P9428 PRODUCT OVERVIEW PIN ASSIGNMENTS (Continued) VSS XIN XOUT TEST P0.1/SO P0.0/SCK RESET P3.0 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5 AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S3C9424/C9428 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P0.2/SI P0.3/CLO P0.4/AD8 P0.5/AD9 P0.6/AD10 P0.7/AD11/PWM0 P3.1 P1.0/T0/ZCD P1.1/BUZ P1.2/INT0 P1.3/INT1/PWM1 P2.7/AD7/SCLK P2.6/AD6/SDAT AVREF Figure 1-3. Pin Assignment Diagram (30-Pin SDIP Package) VSS XIN XOUT TEST P0.1/SO P0.0/SCK RESET P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5 AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 S3C9424/C9428 28-SOP (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P0.2/SI P0.3/CLO P0.4/AD8 P0.5/AD9 P0.6/AD10 P0.7/AD11/PWM0 P1.0/T0/ZCD P1.1/BUZ P1.2/INT0 P1.3/INT1/PWM1 P2.7/AD7/SCLK P2.6/AD6/SDAT AVREF Figure 1-4. Pin Assignment Diagram (28-Pin SOP Package) 1-5 PRODUCT OVERVIEW S3C9424/C9428/P9428 PIN DESCRIPTIONS Table 1-1. S3C9424/C9428/P9428 Pin Descriptions Pin Names P0.0-P0.7 Pin Type I/O Pin Description Bit-programmable I/O port for Schmitt trigger input or pushpull, open-drain output. Pull-up resistors are assignable by software. Bit-programmable I/O port for Schmitt trigger input or pushpull output. Pull-up resistors are assignable by software. Port 1 pins can also be used as alternative functions. Bit-programmable I/O port for Schmitt trigger input or pushpull, open drain output. Pull up resistors are assignable by software. Port 2 can also be used as external interrupt, A/D input. Push-pull or open-drain output port. Pull-up resistors are assignable by software. Crystal/ceramic, or RC oscillator signal for system clock. System RESET signal input pin. Test signal input pin (for factory use only: must be connected to VSS) A/D converter reference voltage input and ground Voltage input pin and ground Serial interface clock input or output Serial data output Serial data output System clock output port IIC CLOCK IIC DATA 200 Hz-20 kHz frequency output for buzzer sound. Zero crossing detector input Timer 0 capture input or 10-bit PWM output External interrupt input 12-bit PWM output A/D converter input Pin Type E E-1 D Share Pins SCK,SO,SI , CLO, AD8-AD11 T0/ZCD BUZ INT0 INT1 E-1 AD0-AD7 P1.0-P1.3 I/O P2.0-P2.7 I/O P3.0-P3.3 XIN, XOUT RESET TEST AVREF, AVSS VDD, VSS SCK SO SI CLO SCLK SDAT BUZ ZCD T0 INT0 INT1 PWM0 PWM1 AD0-AD11 O – E-2 – B – – – E E E E E-1 D D D D E-1 D E-1 – – – – – – P0.0 P0.1 P0.2 P0.3 P2.7 P2.6 P1.1 P1.0 P1.0 P1.2 P1.3 P0.7 P1.3 P2.0-P2.7 P0.4-P0.7 I I – – I/O O I O I/O O I I/O I O I 1-6 S3C9424/C9428/P9428 PRODUCT OVERVIEW PIN CIRCUITS VDD VDD P-Channel In N-Channel Data P-Channel Out Output DIsable N-Channel Figure 1-5. Pin Circuit Type A Last Developing: 99.02.02 Figure 1-7. Pin Circuit Type C VDD VDD Pull-Up Resistor In Resistor Enable Data Output DIsable Pull-up Resistor P-Channel Circuit Type C I/O Data Figure 1-6. Pin Circuit Type B Figure 1-8. Pin Circuit Type D 1-7 PRODUCT OVERVIEW S3C9424/C9428/P9428 VDD PNE Pull-up Resistor VDD PNE 47K VDD VDD P-CH Data Output Disable N-CH Pull-up Enable I/O Data Output Disable Pull-up Enable Out Input Figure 1-9. Pin Circuit Type E Figure 1-11. Pin Circuit Type E-2 VDD PNE Pull-up Resistor VDD P-CH Data Output Disable N-CH Pull-up Enable I/O Input Analog Input Figure 1-10. Pin Circuit Type E-1 1-8 S3C9424/C9428/P9428 ELECTRICAL DATA 16 OVERVIEW ELECTRICAL DATA In this section, the following S3C9424/C9428/P9428 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Operating Voltage Range — Schmitt trigger input characteristics — Oscillator characteristics — Oscillation stabilization time — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by a RESET — Power-on RESET circuit characteristics — A/D converter electrical characteristics — Zero-crossing detector — Zero Crossing Waveform Diagram 16-1 ELECTRICAL DATA S3C9424/C9428/P9428 Table 16-1. Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Input voltage Output voltage Output current high Output current low Operating temperature Storage temperature TA TSTG I OL Symbol VDD VI VO I OH All input ports All output ports One I/O pin active All I/O pins active One I/O pin active Total pin current for ports 1, 2, 3 Total pin current for ports 0 – – Conditions – Rating – 0.3 to + 6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 25 – 80 + 30 + 100 + 200 – 40 to + 85 – 65 to + 150 °C °C Unit V V V mA mA 16-2 S3C9424/C9428/P9428 ELECTRICAL DATA Table 16-2. D.C. Electrical Characteristics(30SDIP, 32SOP) (TA = – 40°C to + 85°C, VDD = 3.0 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH3 Input low voltage VIL1 VIL2 Output high voltage Output low voltage Input high leakage current VOH VOL ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL RP IDD1 RESET Conditions Ports 0, 1, 2 and XIN and XOUT Ports 0, 1, 2 and RESET Min 0.8 VDD VDD – 0.1 Typ – Max VDD Unit V VDD= 3.0 to 5.5 V VDD= 3.0 to 5.5 V – – 0.2 VDD 0.1 V XIN and XOUT IOH = – 10 mA ports 0-3 IOL = 25 mA port 0-3 VDD= 4.5 to 5.5 V VDD= 4.5 to 5.5 V VDD – 1.5 – – VDD – 0.4 0.4 – – 2.0 1 20 V V µA All input pins except VIN = VDD ILIH2 XIN, XOUT VIN = VDD All input pins except VIN = 0 V ILIL2 and RESET XIN, XOUT All output pins All output pins VIN = 0 V Port 0-2 RESET VIN = 0 V VOUT = VDD VOUT = 0 V VDD = 5 V VDD = 5 V – – –1 – 20 µA – – 30 100 – – – 47 200 11 1.5 2 –2 70 350 20 4 8 2 100 80 µA µA KΩ Supply current RUN mode 16-MHz VDD = 4.5 to 5.5 V CPU clock 4-MHz CPU clock VDD = 3 V VDD = 4.5 to 5.5 V VDD = 3.3 V VDD = 4.5 to 5.5 V VDD = 3.3 V mA IDD2 Idle mode 16-MHz CPU clock 4-MHz CPU clock – 3 0.5 IDD3 Stop mode – 65 45 µA NOTE: D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up resisters, output port drive current, ZCD and ADC. 16-3 ELECTRICAL DATA S3C9424/C9428/P9428 Table 16-3. D.C. Electrical Characteristics (28SOP) (TA = – 40°C to + 85°C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH3 Input low voltage VIL1 VIL2 Output high voltage Output low voltage Input high leakage current VOH VOL ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL RP IDD1 RESET Conditions Ports 0, 1, 2 and XIN and XOUT Ports 0, 1, 2 and RESET Min 0.8 VDD VDD – 0.1 Typ – Max VDD Unit V VDD= 1.8 to 5.5 V VDD= 1.8 to 5.5 V – – 0.2 VDD 0.1 V XIN and XOUT IOH = – 10 mA ports 0-3 IOL = 25 mA port 0-3 VDD= 4.5 to 5.5 V VDD= 4.5 to 5.5 V VDD – 1.0 – – VDD – 0.4 0.4 – – 2.0 1 20 V V µA All input pins except VIN = VDD ILIH2 XIN, XOUT VIN = VDD All input pins except VIN = 0 V ILIL2 and RESET XIN, XOUT All output pins All output pins VIN = 0 V Port 0-2 RESET VIN = 0 V VOUT = VDD VOUT = 0 V VDD = 5 V VDD = 5 V – – –1 – 20 µA – – 30 100 – – – 47 200 11 1 2 –2 70 350 20 3 9 1.0 5 µA µA KΩ Supply current RUN mode 16-MHz VDD = 4.5 to 5.5 V CPU clock 3-MHz CPU clock VDD = 1.8 to 2.2 V VDD = 4.5 to 5.5 V VDD = 1.8 to 2.2 V VDD = 4.5 to 5.5 V VDD = 3 V VDD = 1.8 to 2.2 V mA IDD2 Idle mode 16-MHz CPU clock 3-MHz CPU clock – 3 0.3 IDD3 Stop mode – 0.1 µA NOTE: D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up resisters, output port drive current, ZCD and ADC. 16-4 S3C9424/C9428/P9428 ELECTRICAL DATA Table 16-4. A.C. Electrical Characteristics (TA = –40°C to + 85°C, VDD = 1.8 V to 5.5 V) Parameter Interrupt input high, low width RESET input low width Symbol tINTH, tINTL tRSL – Conditions Port 1v(INT0, INT1) VDD = 5V ± 10% Input VDD = 5V ± 10% Min – – Typ 200 1 Max – – Unit ns us 1/tCPU tINTL tRSL tINTH 0.8 VDD 0.2 VDD NOTE: The unit tcpu means one CPU clock period. Figure 16-1. Input Timing Measurement Points 16-5 ELECTRICAL DATA S3C9424/C9428/P9428 CPU Clock 16MHz 8MHz 4MHz 3MHz 2MHz 1MHz 1 1.8 2 2.7 3 4 4.5 5 5.5 6 7 Supply Voltage (V) Figure 16-2. Operating Voltage Range (KS86C4204/C4208) VOUT VDD A = 0.2 VDD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD VSS A B C D VIN 0.3 VDD 0.7 VDD Figure 16-3. Schimtt Trigger Input Characteristic Diagram 16-6 S3C9424/C9428/P9428 ELECTRICAL DATA Table 16-5. Oscillator Characteristics (30SDIP, 32SOP) (TA = – 40°C to + 85°C) Oscillator Main crystal or ceramic Clock Circuit XIN XOUT Test Condition VDD = 4.5 to 5.5 V VDD = 3.0 to 4.5 V Min 1 1 Typ – – Max 16 8 Unit MHz C1 C2 External clock (Main system) XIN XOUT VDD = 4.5 to 5.5 V VDD = 3.0 to 4.5 V 1 1 – – 16 8 RC oscillator XIN R XOUT VDD = 4.75 to 5.25 V Tolerance: 10% – 4 – Table 16-6. Oscillation Stabilization Time (28SOP) (TA = – 40°C to + 85°C) Oscillator Main crystal or ceramic Clock Circuit XIN XOUT Test Condition VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V VDD = 1.8 to 2.7 V Min 1 1 1 Typ – – – Max 16 8 3 Unit MHz C1 C2 External clock (Main system) XIN XOUT VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V VDD = 1.8 to 2.7 V 1 1 1 – – – 16 8 3 RC oscillator XIN R XOUT VDD = 4.75 to 5.25 V Tolerance: 10% – 4 – 16-7 ELECTRICAL DATA S3C9424/C9428/P9428 Table 16-7. Oscillation Stabilization Time (TA = – 40°C to + 85°C, VDD = 1.8 V to 5.5 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time fosc > 1.0 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low width (tXH, tXL) tWAIT when released by a reset (1) tWAIT when released by an interrupt (2) Test Condition Min – – 25 – – Typ – – – 216/fosc – Max 20 10 500 – – ns ms Unit ms NOTES: 1. fosc is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON. 16-8 S3C9424/C9428/P9428 ELECTRICAL DATA Table 16-8. Data Retention Supply Voltage in Stop Mode (TA = – 40°C to + 85°C, VDD = 1.8 V to 5.5V) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode; VDDDR = 1.8 V Min 1.8 – Typ – 0.1 Max 5.5 5 Unit V µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. Internal RESET Operation Stop Mode Data Retention Mode Oscillation Stabilization Time Normal Operating Mode ~ ~ ~ ~ VDD RESET Execution Of Stop Instrction VDDDR 0.8 VDD 0.2 VDD tWAIT NOTE: tWAIT is the same as 4096 x 16 x 1/fosc Figure 16-4. Stop Mode Release Timing When Initiated by a RESET RESET 16-9 ELECTRICAL DATA S3C9424/C9428/P9428 Table 16-9. Power-on RESET Circuit Characteristics RESET (TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V) Parameter Power-on reset voltage high Power-on reset voltage low Power supply voltage rise time Power supply voltage off time Power-on reset circuit cunsumption current (2) Symbol VDDH VDDL tr toff IDDPR VDD = 5 V ± 10% VDD = 3.3 V Conditions Min 3.0 0 10 0.5 65 45 100 80 Typ – 2.6 Max 5.5 3.0 (1) Unit V V us s µA NOTES: 1. 216/fx (= 6.55 ms at fx = 10 MHz) 2. Current consumed when power-on reset circuit is provided internally. VDD VDDH VDDL toff tr Figure16-5. Power-on RESET Timing RESET 16-10 S3C9424/C9428/P9428 ELECTRICAL DATA Table 16-10. A/D Converter Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 1.8/3.0 V to 5.5 V, VSS = 0 V) Parameter Total accuracy Symbol Test Conditions VDD = 5.12 V CPU clock = 10 MHz AVREF = 5.12 V AVSS = 0 V Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time(1) ILE DLE EOT EOB tCON VIAN RAN AVREF AVSS IADIN IADC “ “ “ “ fosc = 10 MHz – – – – AVREF = VDD = 5 V AVREF = VDD = 5 V AVREF = VDD = 3 V AVREF = VDD = 5 V Power down mode – – – – – 20 AVSS 2 2.5 VSS – – – – ±1 ±1 – – – – – – 1 0.5 100 ±2 ±1 ±3 ±2 – AVREF – VDD VSS + 0.3 10 3 1.5 500 nA µs V MΩ V V µA mA LSB Min – Typ – Max ±3 Unit LSB Analog input voltage Analog input impedance ADC reference voltage ADC reference ground Analog input current ADC block current (2) NOTES: 1. ‘Conversion time’ is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. Digital Output 11 1111 1111 11 1111 1110 11 1111 1101 . . . . . . . 00 0000 0010 00 0000 0001 00 0000 0000 AVSS VEOB Analog Input V2 V(K-1) V(K) VEOT AVREF Figure 16-6. Definition of DLE and ILE 16-11 ELECTRICAL DATA S3C9424/C9428/P9428 Table 16-11. Zero Crossing Detector (TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V, VSS = 0 V) Parameter Zero-crossing detection input voltage Zero-crossing detection accuracy Symbol VZC Test Conditions AC connection c = 0.1 µF f ZC = 60 Hz (sine wave) VDD = 5 V f OSC = 10 MHz f ZC – 40 – 200 Hz Min 1.0 Typ – Max 3.0 Unit Vp-p VAZC – – ± 150 mV Zero-crossing detection input frequency 1/fzc AC input VAZC VAZ(P-P) ZCINT Figure 16-7. Zero Crossing Waveform Diagram 16-12 S3C9424/C9428/P9428 MECHANICAL DATA 17 OVERVIEW MECHANICAL DATA The S3C9424/C9428 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package (32-SOP-450A) and a 28-pin SOP package (28-SOP-375). Package dimensions are shown in Figures 17-1, 17-2, and 17-3 #30 #16 0-15 0.2 8.94 ± #1 #15 27.88MAX 27.48 ± 0.2 0.51 MIN 0.56 ± (1.30) 1.12 ± 0.1 0.1 1.778 NOTE: Dimensions are in millimeters. Figure 17-1. 30-Pin SDIP Package Dimensions 3.30 ± 0.3 5.08 MAX 3.81 ± 0.2 0.2 5 +0 - 0 .1 .05 30-SDIP-400 10.16 17-1 MECHANICAL DATA S3C9424/C9428/P9428 #32 #17 12.00 ± 0.3 8.34 ± 0.2 2.00 ± 0.2 2.40 MAX #1 19.90 ± 0.2 #16 0.20 + 0.1 - 0.05 (0.43) 0.40 ± 0.1 1.27 NOTE: Dimensions are in millimeters Figure 17-2. 32-SOP-450A Package Dimensions 17-2 0.05 MIN 0.78 ± 0.2 32-SOP-450A 11.43 0-8 S3C9424/C9428/P9428 MECHANICAL DATA #28 #15 10.45 ± 0.3 7.70 ± 0.2 #1 18.02 MAX 17.62 ± 0.2 #14 2.15 ± 0.1 2.50 MAX 0.15 + 0.10 - 0.05 (0.56) 0.41 ± 0.1 1.27 NOTE: Dimensions are in millimeters Figure 17-3. 28-SOP-375 Package Dimensions 0.05 MIN 0.60 ± 0.2 28-SOP-375 9.53 8 17-3 S3C9424/C9428/P9428 S3P9428 OTP 18 OVERVIEW S3P9428 OTP The S3P9428 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9424/C9428 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9428 is fully compatible with the S3C9424/C9428, both in function and in pin configuration. Because of its simple programming requirements, the S3P9428 is ideal for use as an evaluation chip for the S3C9424/C9428. VSS XIN XOUT TEST/VPP P0.1/SO P0.0/SCK RESET P3.0 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5 AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S3P9428 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P0.2/SI/SCL P0.3/CLO/SDA P0.4/AD8 P0.5/AD9 P0.6/AD10 P0.7/AD11/PWM0 P3.1 P1.0/T0/ZCD P1.1/BUZ P1.2/INT0 P1.3/INT1/PWM1 P2.7/AD7/SCLK P2.6/AD6/SDAT AVREF NOTE: The bolds indicate an OTP pin name. Figure 18-1. Pin Assignment Diagram (30-Pin SDIP Package) 18-1 S3P9428 OTP S3C9424/C9428/P9428 VSS XIN XOUT TEST/VPP P0.1/SO P0.0/SCK RESET P3.0 P3.2 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5 AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3P9428 32-SOP (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P0.2/SI/SCL P0.3/CLO/SDA P0.4/AD8 P0.5/AD9 P0.6/AD10 P0.7/AD11/PWM0 P3.1 P3.3 P1.0/T0/ZCD P1.1/BUZ P1.2/INT0 P1.3/INT1/PWM1 P2.7/AD7/SCLK P2.6/AD6/SDAT AVREF NOTE: The bolds indicate an OTP pin name. Figure 18-2. Pin Assignment Diagram (32-Pin SOP Package) VSS XIN XOUT TEST/VPP P0.1/SO P0.0/SCK RESET P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5 AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 S3P9428 28-SOP (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P0.2/SI/SCL P0.3/CLO/SDA P0.4/AD8 P0.5/AD9 P0.6/AD10 P0.7/AD11/PWM0 P1.0/T0/ZCD P1.1/BUZ P1.2/INT0 P1.3/INT1/PWM1 P2.7/AD7/SCLK P2.6/AD6/SDAT AVREF NOTE: The bolds indicate an OTP pin name. Figure 18-3. Pin Assignment Diagram (28-Pin SOP Package) 18-2 S3C9424/C9428/P9428 S3P9428 OTP Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P0.3 Pin Name SDAT Pin No. S3P9428 - 30 SDIP: 28 - 32 SOP: 30 S3P9428 - 30 SDIP: 29 - 32 SOP: 31 4 During Programming I/O I/O Function Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned Serial clock pin (input only pin) P0.2 SCLK I TEST VPP (TEST) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET VDD/VSS RESET VDD/VSS 7 S3P9428 - 30 SDIP: 30/1 - 32 SOP: 32/1 I I Chip Initialization Logic power supply pin. Table 18-2. Comparison of S3P9428 and S3C9424/C9428 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P9428 8-Kbyte EPROM 3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5) VDD = 5 V, VPP (TEST) = 12.5 V 30 SDIP/32 SOP/28SOP User Program 1 time Programmed at the factory S3C9424/C9428 4/8-Kbyte mask ROM 3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5) OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P9428, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 18-3 below. Table 18-3. Operating Mode Selection Criteria VDD 5V Vpp (TEST) REG/MEM 0 0 0 1 ADDRESS(A15-A0) R/W 1 0 1 0 MODE EPROM read EPROM program EPROM verify EPROM read protection 5V 12.5 V 12.5 V 12.5 V 0000H 0000H 0000H 0E3FH NOTE: "0" means Low level; "1" means High level. 18-3