S3P72E8

S3C72E8/P72E8 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C72E8/P72E8 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and LCD drivers. The S3P72E8 is especially suited for use in data bank, telephone and LCD general purpose. It is built around the SAM47 core CPU and contains ROM, RAM, 39 I/O lines, programmable timer/counter, buzzer output, enough LCD dot matrix, and segment drive pins. The S3C72E8/P72E8 can be used for dedicated control functions in a variety of applications, and is especially designed for multi data bank, telephone and LCD game. OTP The S3C72E8 microcontroller is also available in OTP (One Time Programmable) version, S3P72E8. S3P72E8 microcontroller has an on-chip 8 K-byte one-time-programable EPROM instead of masked ROM. The S3P72E8 is comparable to S3C72E8, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C72E8/P72E8 FEATURES SUMMARY Memory • • • 8192 × 8 bit program memory 5120 × 4 bit data memory in S3C72E8 108 x 5 bit display memory LCD Display • • • 12 characters dot matrix display (5 x 7) 12 digit display (8 segments) 60 segments and 9 common pins 39 I/O Pins • • • Input: 6 pins I/O: 17 pins Output: maximum 16 pins for 1-bit level output (sharing with segment driver outputs) Power-Down Modes • • Idle mode (only CPU clock stops) Stop mode (Main-System clock and CPU clock stops) Oscillation Sources • • • • Crystal, ceramic, or External RC for system clock Main-system clock frequency: 0.4 MHz - 6MHz Sub-system clock frequency: 32,768kHz CPU clock divider circuit (by 4,8, or 64) 8-Bit Basic Timer • Four internal timer functions 8-Bit Timer/Counter 0 • • • • Programmable 8-bit timer External event counter Arbitrary clock frequency output External clock signal divider Instruction Execution Times • • • 0.67, 1.33, 10.7 µs at 6MHz 0.95, 1.91, 15.3 µs at 4.19 MHz 122 µs at 32.768 kHz Watch Timer • • Time interval generation: 0,5ms, 3,9ms at 32768Hz 4 frequency (2/4/8/16 kHz) outputs to BUZ pin Operating Voltage Range Interrupts • • • Three external vectored interrupts: INT0, INT1, INTP0 Two internal vectored interrupts: INTB, INTT0 Two quasi-interrupts: INTW, INT2 • 1.8 V to 5.5 V Operating Temperature • -45 °C to 85 °C Package Type • 100-pin QFP Package Memory Mapped I/O Structure 1-2 S3C72E8/P72E8 PRODUCT OVERVIEW BLOCK DIAGRAM INTT0, INTB, INTW INT0, INT1, INTP0, INT2 RESET XIN XOUT XTIN XTOUT Input Port 0 P0.0-P0.3/ K0-K3 8-Bit Timer/ Counter 0 Interrupt Control Block Clock Instruction Register Input Port 1 P1.0/INT0 P1.1/INT1 Watch Timer Internal Interrupts Program Counter I/O Port 2 P2.0/BUZ P2.1/CLO P4.0/TCL0 P4.1/TCLO0 P4.2 P5.0-P5.3 I/O Port 4 Basic Timer Instruction Decoder Program Status Word I/O Port 5 COM0-COM8 SEG16-SEG59 SEG0-SEG15 /P8.0-P8.15 LCD Driver/ Controller Arithmetic and Logic Unit Stack Pointer I/O Port 6 I/O Port 7 P6.0-P6.3/ KS0-KS3 P7.0-P7.3/ KS4-KS7 Data and Display Memory 8 K Byte Program Memory Output Port 8 P8.0-P8.15/ SEG0-SEG15 NOTE: Data memory: 5120 x 4 bits in KS57C21408 Figure 1-1. S3C72E8/P72E8 Specified Block Diagram 1-3 PRODUCT OVERVIEW S3C72E8/P72E8 PIN ASSIGNMENTS SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SEG59 COM4 COM5 COM6 COM7 COM8 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 VDD VSS Xout Xin TEST XTin XTout RESET P2.0/BUZ P2.1/CLO P5.0 P5.1 P5.2 P5.3 TCL0/P4.0 TCLO0/P4.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 S3C72E8 100-QFP 1420C 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15/P8.15 SEG14/P8.14 SEG13/P8.13 SEG12/P8.12 SEG11/P8.11 SEG10/P8.10 SEG9/P8.9 Figure 1-2. S3C72E8 Pin Assignment Diagram 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG8/P8.8 SEG7/P8.7 SEG6/P8.6 SEG5/P8.5 SEG4/P8.4 SEG3/P8.3 SEG2/P8.2 SEG1/P8.1 SEG0/P8.0 COM3 COM2 COM1 COM0 INT0/P1.0 INT1/P1.1 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P4.2 1-4 S3C72E8/P72E8 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. Pin Descriptions Pin Description Type I P0.0 - P0.3 4-bit input port. 1 and 4-bit read, and test are possible. Pull-up registers. 2-bit Input port. P1.0 I 1 and 4-bit read, and test are possible, 2-bit pull-up P1.1 resistors are assignable by software. P2.0 I/O 2-bit I/O port. 1 and 4-bit read/write, and test are possible. P2.1 Each individual pin can be specified as input or output. 2-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. P4.0 I/O 4-bit I/O port. 1, 4, and 8-bit read/write, and test are possible. P4.1 4-pin unit can be specified as input or output. P4.2 4-bit pull-up resistors are assignable by software. P5.0 - P5.3 Pull-up resistors are automatically disabled for output pins. Individual pins are software configurable as opendrain or push-pull output. P6.0 - P6.3 4-bit I/O port. 1, 4,and 8-bit read/write, and test are I/O possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. P7.0 - P7.3 4-bit I/O port. 1, 4, and 8-bit read/write, and test are possible. 4-pin unit can be specified as input or output. 4-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. P8.0 - P8.15 O 4-bit controllable output. (Dual function as segment output pins) SEG16-SEG59 LCD segment display signal output. SEG0 - SEG15 COM0 - COM8 INT0 - INT1 KS0 - KS7 K0 - K3 I I/O I LCD segment display signal output. LCD common signal output. External interrupts. The triggering edge for INT0, and INT1 is selectable Quasi-interrupt input for falling edge detection. Vector interrupt input K0 - K3: falling edge detection Pin Name Circuit Pin Type Number A-1 35-32 Share Pin K0-K3 A-3 37 36 23 24 INT0 INT1 BUZ CLO D E E-1 E-1 E-1 29 30 31 25-28 TCL0 TCLO0 D-1 7-10 KS0 - KS3 11-14 KS4 - KS7 H-9 H-10 H-9 H-11 42-57 58-100 ,1 42-57 38-41 2-6 37-36 7-14 35-32 SEG0 SEG15 P8.0 - P8.15 P1.0 -P1.1 P6.0 - P7.3 P0.0 - P0.3 1-5 PRODUCT OVERVIEW S3C72E8/P72E8 Table 1-1. Pin Descriptions (Continued) Pin Name BUZ CLO Xin, Xout XTin, XTout TCL0 TCLO0 RESET VDD VSS TEST Pin Description Type I/O 2,4,8 kHz or 16kHz frequency output for buzzer signal. Clock output I/O I/O I I Crystal, ceramic or RC oscillator pins for main system clock. Crystal oscillator pins for sub-system clock. External clock input for Timer/Counter 0 Timer/Counter 0 clock output Reset input (active low). Power supply. Ground. Test input: it must be connected to VSS Circuit Type B Pin Num. 23 24 18, 17 20, 21 29 30 22 15 16 19 Share Pin P2.0 P2.1 P4.0 P4.1 - 1-6 S3C72E8/P72E8 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD Pull-up Resistor P-channel IN N-channel IN Pull-up Resistor Enable VDD P-channel Schmitt Trigger Vss Figure 1-3. Pin Circuit Type A Figure 1-5. Pin Circuit Type A-3 VDD VDD Pull-up Pull-up Register Pull-up Resistor Enable IN P-channel IN Schmitt Trigger Figure 1-4. Pin Circuit Type A-1 Figure 1-6. Pin Circuit Type B 1-7 PRODUCT OVERVIEW S3C72E8/P72E8 VDD VDD Pull-up Resistor Pull-up Resistor Enable Data P-channel P-channel OUT N-channel Output Disable VSS Data Output Disable Type C IN/OUT Schmitt Trigger Figure 1-7. Pin Circuit Type C Figure 1-9. Pin Circuit Type D-1 VDD Pull-Up Resistor Pull-Up Resistor Enable Data Output Disable Type C PNE VDD VDD Pull-up Resistor P-channel Data P-channel I/O Pull-up Resistor Enable In/Out Output Disable N-channel Schmitt Trigger Figure 1-8. Pin Circuit Type D Figure 1-10. Pin Circuit Type E 1-8 S3C72E8/P72E8 PRODUCT OVERVIEW VDD PNE VDD Pull-up resistor Data P-channel I/O Pull-up Resistor Enable VLC2 Segment Data OUT Output Disable N-channel VLC0 Figure 1-11. Pin Circuit Type E-1 Figure 1-13. Pin Circuit Type H-10 VDD SEG Data/P8.0-P8.15 VLC1 VLC2 VLC0 OUT OUT COM Data Vss Key strobe Vss Polarity Vss Figure 1-12. Pin Circuit Type H-9 Figure 1-14. Pin Circuit Type H-11 1-9 S3C72E8/P72E8 ELECTRICAL DATA 13 OVERVIEW ELECTRICAL DATA In this section, information on S3C72E8/P72E8 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: STANDARD ELECTRICAL CHARACTERISTICS — Absolute maximum ratings — D.C electrical characteristics — Main-system clock oscillator characteristics — Sub-system clock oscillator characteristics — I/O capacitance — A.C electrical characteristics — Operating voltage range MISCELLANEOUS TIMING WAVEFORMS — A.C timing measurement point — Clock timing measurement at Xin — Clock timing measurement at XTin — TCL0 timing — Input timing for RESET — Input timing for external interrupts STOP MODE CHARACTERISTICS AND TIMING WAVEFORMS — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 13–1 ELECTRICAL DATA S3C72E8/P72E8 Table 13-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply Voltage Input Voltage Output Voltage High Level Output current Low Level Output Current All pins TA TSTG IOL Symbol VDD VI VO IOH One pin All output pins One pin Peak value RMS value (note) Peak value RMS value (note) Operating Temperature Storage Temperature NOTE : RMS value = Peak Value × Duty . Conditions – Ports 0, 1, 2, 4, 5, 6, 7 – Rating – 0.3 to + 6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 15 – 30 30 15 100 60 – 40 to + 85 – 65 to + 150 Units V V V mA mA mA mA mA mA °C °C – – Table 13-2. D.C Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage VOH1 Conditions Pins except below Port0, 1, 6, 7, P4.0, RESET XIN, XOUT and XTIN All input pins except below Port0, 1, 6, 7, P4.0, RESET XIN,XOUT and XTIN VDD = 4.5 V to 5.5 V Port2, 4, 5, 6, 7 IOH = – 1mA VDD – 1.0 Min. 0.7 VDD 0.8 VDD VDD – 0.1 – Typ. – – – – – – – Max. VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 – Units V 13–2 S3C72E8/P72E8 ELECTRICAL DATA Table 13-2. D.C Characteristics(continued) (TA = – 40 °C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Output Low Voltage Symbol VOL1 Conditions VDD = 4.5 V to 5.5 V Port2, 4, 5, 6, 7 IOL= 15mA VDD = 1.8 V to 5.5 V IOL=1.6mA Input High Leakage Current ILIH1 ILIH2 Input Low Leakage Current ILIL1 Vin = VDD All input pins except below Vin = VDD XIN, XOUT, XTIN VIN = 0 V All input pins except XIN, XOUT, XTIN and RESET ILIL2 Output High Leakage Current Output Low Leakage Current Pull-up Resistor ILOH1 ILOL1 RL1 VIN = 0 V XIN, XOUT, XTIN VO = VDD Port2, 4, 5, 6, 7 VO = 0 V Port2, 4, 5, 6, 7 All pins except RESET VDD = 3 V RL2 RESET VDD = 5 V, VIN = 0 V 50 100 200 VM1 – 0.2 VM2 – 0.2 VM3 – 0.2 VM4 – 0.2 SEG0-SEG59 COM0-COM8 VO = 0.5V SEG0-SEG59 SEG0-SEG15 (key strobe) COM0-COM8 – – – – – 100 250 500 VM1 VM2 VM3 VM4 – – – – – 200 400 800 VM1 + 0.2 VM2 + 0.2 VM3 + 0.2 VM4 + 0.2 90 25 90 2 25 kΩ KΩ V VDD = 5 V, VIN = 0 V – – – 25 – – – 50 – 20 3 –3 100 KΩ – – Min. – Typ. – Max. 2 Units – – – – 0.4 3 20 –3 µA VDD = 3 V Medium Output Voltage(1) VOM1 VOM2 VOM3 VOM4 High Output Impedance Low Output Resistor ROH1 ROH2 ROL1 ROL2 ROL3 COM0-COM8 COM0-COM8 SEG0-CSEG59 SEG0-CSEG59 VO = VDD–0.5V 13–3 ELECTRICAL DATA S3C72E8/P72E8 Table 13-2. D.C Characteristics (continued) (TA = – 40 °C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (2) (3) Symbol IDD1 Conditions Run mode : VDD = 5 V ± 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V ± 10% 6MHz 4.19MHz 6MHz 4.19MHz Min. – Typ. 5.1 3.8 2.5 1.8 1.3 1.1 0.5 0.4 Max. 8 6 4 3 2.5 1.8 1.5 1.0 45 30 Units mA IDD2 Idle mode : VDD = 5 V ± 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V ± 10% 6MHz 4.19MHz 6MHz 4.19MHz IDD3 IDD4 Run mode: VDD = 3 V ± 10% 32kHz crystal oscillator Idle mode: VDD = 3 V ± 10% 32kHz crystal oscillator VDD = 3 V ± 10% 32kHz crystal oscillator LCD ON (4) – – 30 17 µA LCD OFF – 6 2.4 0.6 15 5 3 IDD5 Stop mode; VDD = 5 V ± 10%, XTIN = 0V Stop mode; VDD = 3 V ± 10%, XTIN = 0V NOTES: 1. VM1=2.75/3.75 VDD, VM2=1/3.75 VDD, VM3=2/3.75 VDD, VM4=1.75/3.75 VDD 2. 3. 4. Supply current does not include current drawn through internal pull-down resistor and LCD driving resistors. For D.C. electrical voltages, PCON register must be set to 0011B. The mode of IDD4 (LCD ON) is normal. 13–4 S3C72E8/P72E8 ELECTRICAL DATA Table 13-3. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT Parameter Oscillation frequency(fx) (1) Test Condition – Min 0.4 Typ – Max 6.0 Units MHz C1 C2 Stabilization time (2) After VDD reaches the minimum level of its variable range – – – 4 ms Crystal Oscillator XIN XOUT Oscillation frequency(fx) (1) 0.4 – 6 MHz C1 C2 Stabilization time (2) External Clock Xin input frequency(fx) (1) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 5.5 V – – – 0.4 – – – 10 60 6 ms XIN XOUT MHz Xin input high and low level width (tXH, tXL) RC Oscillator XIN R XOUT – VDD = 5 V 83.3 – – 2 1250 – ns MHz Frequency VDD = 3 V – 1 – NOTES: 1. Oscillation frequency and input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on or release of STOP mode. 13–5 ELECTRICAL DATA S3C72E8/P72E8 Table 13-4. Recommended Oscillator Constants (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Manufacturer Series Number (1) FCR FCR CCR M5 MC5 MC3 Frequency Range Load Cap (pF) C1 TDK 3.58 MHz–6.0 MHz 3.58 MHz–6.0 MHz 3.58 MHz–6.0 MHz 33 (2) Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5 Remarks C2 33 (2) Leaded Type On-chip C Leaded Type On-chip C SMD Type (3) (3) NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in. 13–6 S3C72E8/P72E8 ELECTRICAL DATA Table 13-5. Subsystem Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration XTIN XTOUT Parameter Oscillation frequency (1) Test Condition – Min 32 Typ 32.768 Max 35 Units kHz C1 C2 Stabilization time (2) VDD = 4.5 V to 5.5 V VDD = 1.8 V to 5.5 V – – 32 1.0 – – 2 10 100 ms External Clock XTIN XTOUT XTin input frequency (1) – kHz XTin input high and low level width (tXTH, tXTL) – 5 – 15 µs NOTES: 1. Oscillation frequency and input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on or release of STOP mode. Table 13-6. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min – – – Typ – – – Max 15 15 15 Units pF pF pF 13–7 ELECTRICAL DATA S3C72E8/P72E8 Table 13-7. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (NOTE) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V With sub-system clock (fxt) TCL0 Input Frequency TCL0 Input High, Low Width f TI VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V tTIH tTIL tINTH, tINTL VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V External Interrupt Input High, Low Width RESET Low Level Width INT0, INT1, KS0 - KS7 0.48 1.8 10 Min 0.67 1.33 114 0 Typ – Max 64 Units µs 122 – 1952 1.5 1 MHz kHz µs – – – – µs KS0 - KS3 tRSL – 10 10 – – µs NOTE: Unless otherwise specified, the values of instruction cycle time condition assume a main-system clock (fx) source. 13–8 S3C72E8/P72E8 ELECTRICAL DATA CPU Clock 1.5 MHz Main Oscillator Frequency 6 MHz 0.75 MHz 3 MHz 15.625 kHz 400 kHz 1 1.8 V 2 3 4 5 6 7 Supply Voltage(V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64) Figure 13-1. Standard Operating Voltage Range Table 13-8. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions – VDDDR = 1.8 V – Released by RESET Released by interrupt Min 1.8 – 0 – – Typ – 0.1 – 217 / fx (2) Max 5.5 10 – – – Unit V µA µs ms NOTES: 1. During oscillator stabilization time, all CPU operations are stopped to avoid unstable operation upon oscillation start. 2. The basic timer mode register (BMOD) interval timer delays execution of CPU instructions during the wait time. 13–9 ELECTRICAL DATA S3C72E8/P72E8 TIMING WAVEFORMS INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE OPERATING MODE VDD EXECUTION OF STOP INSTRUCTION RESET VDDDR t WAIT tSREL Figure 13-2. Stop Mode Release Timing When Initiated By RESET RESET IDLE MODE STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE VDD EXECUTION OF STOP INSTRUCTION VDDDR tSREL POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) t WAIT Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request 13–10 S3C72E8/P72E8 ELECTRICAL DATA 0.8 VDD 0.2 VDD MEASUREMENT POINTS 0.8 VDD 0.2 VDD Figure 13-4. A.C. Timing Measurement Points (Except for Xin and XTin) 1 / fx (1 / fXT) tXL (tXTL) tXH ( tXTH) Xin (XTin) VDD – 0.5 V 0.4 V Figure 13-5. Clock Timing Measurement at Xin and XTin 13–11 ELECTRICAL DATA S3C72E8/P72E8 1 / fTI tTIL TCL0 tTIH 0.8 VDD 0.2 VDD Figure 13-6. TCL0 Timing tRSL RESET 0.2 VDD Figure 13-7. Input Timing for RESET Signal RESET t INTL t INTH INT0, 1 INTP0 KS0 to KS7 0.8 VDD 0.2 VDD Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts 13–12 S3C72E8/P72E8 MECHANICAL DATA 14 OVERVIEW — — — Pad diagram MECHANICAL DATA This section contains the following information about the device package: Package dimensions in millimeters Pad/pin coordinate data table 23.90 ± 0.3 0-8 20.00 ± 0.2 0.15 +0.10 -0.05 17.90 ± 0.3 14.00 ± 0.2 100-QFP-1420C 0.80 ± 0.20 0.10 MAX #100 (0.83) 0.3 ± 0.1 0.10 MAX 0.65 (0.58) #1 0.05 MIN 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 14-1. 100-QFP-1420 Package Dimensions 14-1 S3C72E8/P72E8 KS57P21408 OTP 15 OVERVIEW S3P72E8 OTP The S3P72E8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72E8 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P72E8 is fully compatible with the S3C72E8, both in function and in pin configuration. Because of its simple programming requirements, the S3P72E8 is ideal for use as an evaluation chip for the S3C72E8. 15-1 KS57P21408 OTP S3C72E8/P72E8 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SEG59 COM4 COM5 COM6 COM7 COM8 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 P7.0/KS4 P7.1/KS5 SDAT/P7.2/KS6 SCLK /P7.3/KS7 VDD /V DD VSS/VSS Xout Xin VPP/TEST XTin XTout RESET / RESET R ESET P2.0/BUZ P2.1/CLO P5.0 P5.1 P5.2 P5.3 TCL0/P4.0 TCLO0/P4.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 S3P72E8 100-QFP 1420C 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15/P8.15 SEG14/P8.14 SEG13/P8.13 SEG12/P8.12 SEG11/P8.11 SEG10/P8.10 SEG9/P8.9 Figure 15-1. S3P72E8 Pin Assignments (100-QFP Package) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG8/P8.8 SEG7/P8.7 SEG6/P8.6 SEG5/P8.5 SEG4/P8.4 SEG3/P8.3 SEG2/P8.2 SEG1/P8.1 SEG0/P8.0 COM3 COM2 COM1 COM0 INT0/P1.0 INT1/P1.1 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P4.2 15-2 S3C72E8/P72E8 KS57P21408 OTP Table 15-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P3.1 Pin Name SDAT Pin No. 13 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P3.0 TEST SCLK VPP(TEST) 14 19 I/O I RESET VDD / VSS RESET VDD / VSS 22 15/16 I I Table 15-2. Comparison of S3P72E8 and S3C72E8 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 8 Kbyte EPROM 1.8 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 100 QFP User Program 1 time 100 QFP Programmed at the factory S3P72E8 S3C72E8 8 Kbyte mask ROM 1.8 V to 5.5V OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P72E8, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD 5V Vpp (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode NOTE: "0" means Low level; "1" means High level. 15-3 KS57P21408 OTP S3C72E8/P72E8 Table 15-4. D.C Characteristics (TA = –40 °C to +85C, VDD = 1.8 V to 5.5V) Parameter Supply Current (2)(3) Symbol IDD1 Conditions Run mode : VDD=5V±10% Crystal oscillator C1=C2=22pF VDD=3V±10% 6MHz 4.19MHz 6MHz 4.19MHz Min. – Typ. 5.1 3.8 2.5 1.8 1.3 1.1 0.5 0.4 Max. 8 6 4 3 2.5 1.8 1.5 1.0 45 30 Units mA IDD2 Idle mode : VDD=5V±10% Crystal oscillator C1=C2=22pF VDD=3V±10% 6MHz 4.19MHz 6MHz 4.19MHz IDD3 IDD4 Run mode : VDD=3V±10% 32kHz crystal oscillator Idle mode : VDD=3V±10% 32kHz crystal oscillator VDD=3V±10% 32kHz crystal oscillator LCD ON(4) – – 30 17 µA LCD OFF – 6 2.4 0.6 15 5 3 IDD5 Stop mode; VDD=5V±10% Stop mode; VDD=3V±10% NOTES: 1. VM1=2.75/3.75 VDD, VM2=1/3.75 VDD, VM3=2/3.75 VDD, VM4=1.75/3.75 VDD 2. Supply current does not include current drawn through internal pull-down resistor and LCD driving resistors. 3. For D.C. electrical voltages, PCON register must be set to 0011B. 5. The mode of IDD4 (LCD ON) is normal. 15-4 S3C72E8/P72E8 KS57P21408 OTP CPU Clock 1.5 MHz Main Oscillator Frequency 6 MHz 0.75 MHz 3 MHz 15.625 kHz 400 kHz 1 1.8 V 2 3 4 5 6 7 Supply Voltage(V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64) Figure 15-2. Standard Operating Voltage Range 15-5