SIP-ASRNXS003

TM The Samsung ARTIK 530 Module is a highly-integrated ® ® System-in-Module that combines a quad core ARM Cortex -A9 processor packaged DRAM and Flash memories; a Secure Element; and a wide range of wireless communication options ® such as 802.11a/b/g/n, Bluetooth 4.2 (BLE+Classic), and ® 802.15.4 for ZigBee /Thread; all into one 49x36mm footprint. The many standard digital control interfaces support external sensors and higher-performance peripherals to expand the ® module’s capabilities. With the combination of Wi-Fi , ® Bluetooth and ZigBee or Thread, the ARTIK 530 Module is the perfect choice for home automation and home hub devices, while also supporting a rich UI/UX capability for camera and display requirements. The inclusion of a hardware-based Secure Element provides end-to-end security. ARTIK 530 MODULE MEDIA INTERFACES RADIO SECURITY PROCESSOR POWER MGT. MEMORY SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an “AS IS” basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other-wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. 2 ARTIK 530 Module Table of Contents .................................................................................................................................. 3 List of Figures .......................................................................................................................................................................... 5 List of Tables ........................................................................................................................................................................... 5 Version History ...................................................................................................................................................................................... 7 Block Diagram and Module Features .................................................................................................................................. 8 ARTIK 530 Module Features ................................................................................................................................................................. 9 Module PADs ........................................................................................................................................................................ 17 Ball Table Column Definitions ........................................................................................................................................................... 18 Functional Interfaces ........................................................................................................................................................... 27 ADC ....................................................................................................................................................................................................... 27 Booting ................................................................................................................................................................................................. 27 Bluetooth® PCM ................................................................................................................................................................................. 27 MIPI CSI ................................................................................................................................................................................................ 27 MIPI DSI ................................................................................................................................................................................................ 28 GMAC.................................................................................................................................................................................................... 28 GPIO ..................................................................................................................................................................................................... 29 HDMI .................................................................................................................................................................................................... 29 HSIC ...................................................................................................................................................................................................... 30 2 I C ......................................................................................................................................................................................................... 30 2 I S.......................................................................................................................................................................................................... 30 JTAG ...................................................................................................................................................................................................... 30 Key ........................................................................................................................................................................................................ 31 LVDS ..................................................................................................................................................................................................... 31 Miscellaneous ...................................................................................................................................................................................... 31 Power ................................................................................................................................................................................................... 32 PWM ..................................................................................................................................................................................................... 32 SD/MMC ............................................................................................................................................................................................... 32 SPI ......................................................................................................................................................................................................... 33 UART ..................................................................................................................................................................................................... 33 USB HOST/USB OTG ............................................................................................................................................................................ 33 802.15.4 ............................................................................................................................................................................................... 33 GPIO Alternate Functions .................................................................................................................................................... 34 Booting Sequence ................................................................................................................................................................ 37 Power States ......................................................................................................................................................................... 38 Antenna Connections .......................................................................................................................................................... 39 Electrical Specifications ....................................................................................................................................................... 40 Absolute Maximum Ratings ............................................................................................................................................................... 40 Recommended Operating Conditions .............................................................................................................................................. 41 DC Module Use Case Characteristics ................................................................................................................................................ 42 Power Supply Requirements .............................................................................................................................................................. 42 ESD Ratings .......................................................................................................................................................................................... 44 DC Electrical Characteristics .............................................................................................................................................................. 45 AC Electrical Characteristics .............................................................................................................................................................. 47 RF Electrical Characteristics ............................................................................................................................................................... 52 Mechanical Specifications ................................................................................................................................................... 57 Certifications and Compliance ........................................................................................................................................... 60 Bluetooth® .......................................................................................................................................................................................... 60 CE .......................................................................................................................................................................................................... 60 IC ........................................................................................................................................................................................................... 60 3 FCC........................................................................................................................................................................................................ 60 RoHS Compliance ............................................................................................................................................................................... 60 HDMI Compliance ............................................................................................................................................................................... 60 FCC Regulatory Disclosures................................................................................................................................................................ 61 Industry Canada Regulatory Disclosures ......................................................................................................................................... 62 EU Regulatory Disclosures ................................................................................................................................................................. 63 Ordering Information .......................................................................................................................................................... 64 Legal Information ................................................................................................................................................................. 65 4 Figure 1. ARTIK 530 Module Functional Block Diagram ......................................................................................................8 Figure 2. ARTIK 530 Module Top View BALL Organization .............................................................................................. 17 Figure 3. ARTIK 530 Module Power Management State Diagram .................................................................................. 38 Figure 4. RF Connector for Bluetooth®/Wi-Fi® and 802.15.4 (ZigBee/Thread) ............................................................ 39 Figure 5. ARTIK 530 Module Power Distribution ............................................................................................................... 42 Figure 6. High Speed SDMMC Interface Timing ................................................................................................................ 47 Figure 7. SPI Interface Timing (CPHA = 0, CPOL = 1 (Format A)) ..................................................................................... 48 2 Figure 8. I C Interface Timing............................................................................................................................................... 51 Figure 9. ARTIK 530 Module Top View Mechanical Dimensions and Part Location ..................................................... 57 Figure 10. ARTIK 530 Module Mechanical Dimensions Top View ................................................................................... 58 Figure 11 ARTIK 530 Module Mechanical Dimensions Bottom View ............................................................................. 58 Figure 12. L-Shaped PAD Pins .............................................................................................................................................. 59 Table 1. Ball Table Column Definition ................................................................................................................................ 18 Table 2. NORTH BALL ARRAY ............................................................................................................................................... 19 Table 3. SOUTH BALL ARRAY ............................................................................................................................................... 21 Table 4. EAST BALL ARRAY ................................................................................................................................................... 23 Table 5. RIGHT BALL ARRAY ................................................................................................................................................. 25 Table 6. Center Ball Array ..................................................................................................................................................... 26 Table 7. ADC ........................................................................................................................................................................... 27 Table 8. Booting ..................................................................................................................................................................... 27 Table 9. Bluetooth® PCM ..................................................................................................................................................... 27 Table 10. MIPI CSI .................................................................................................................................................................. 27 Table 11. MIPI DSI.................................................................................................................................................................. 28 Table 12. GMAC ..................................................................................................................................................................... 28 Table 13. GPIO ....................................................................................................................................................................... 29 Table 14. HDMI ...................................................................................................................................................................... 29 Table 15. HSIC ........................................................................................................................................................................ 30 2 Table 16. I C ........................................................................................................................................................................... 30 2 Table 17. I S ............................................................................................................................................................................ 30 Table 18. JTAG ........................................................................................................................................................................ 30 Table 19. Key .......................................................................................................................................................................... 31 Table 20. LVDS ....................................................................................................................................................................... 31 Table 21. Miscellaneous ....................................................................................................................................................... 31 Table 22. Power ..................................................................................................................................................................... 32 Table 23. PWM ....................................................................................................................................................................... 32 5 Table 24. SD/MMC ................................................................................................................................................................. 32 Table 25. SPI ........................................................................................................................................................................... 33 Table 26. UART ....................................................................................................................................................................... 33 Table 27. USB Host/USB OTG ............................................................................................................................................. 33 Table 28. 802.15.4 ................................................................................................................................................................. 33 Table 29. GPIO Alternate Functions NORTH PART ............................................................................................................ 34 Table 30. GPIO Alternate Functions SOUTH PART ............................................................................................................ 35 Table 31. GPIO Alternate Functions EAST PART ................................................................................................................ 36 Table 32. GPIO Alternate Functions WEST PART ............................................................................................................... 36 Table 33. Booting Scenarios ................................................................................................................................................ 37 Table 34. Booting Options.................................................................................................................................................... 37 Table 35. Absolute Maximum Ratings ................................................................................................................................ 40 Table 36. Recommended Operating Conditions ............................................................................................................... 41 Table 37. DC-DC Converter Description ............................................................................................................................. 42 Table 38. PMIC LDOs ............................................................................................................................................................. 43 Table 39. AC/DC Characteristics LDO3 ............................................................................................................................... 43 Table 40. ESD Ratings ........................................................................................................................................................... 44 Table 41. Shock and Vibration Ratings ............................................................................................................................... 44 Table 42. I/O DC Electrical Characteristics GPIO ............................................................................................................... 45 Table 43. I/O DC Electrical Characteristics 802.15.4 ......................................................................................................... 45 Table 44. I/O DC Electrical Characteristics PMIC ............................................................................................................... 46 Table 45. I/O DC Electrical Characteristics GPIO ............................................................................................................... 46 Table 46. GPIO Pull-up Resistor Current ............................................................................................................................ 46 Table 47. Power on Reset Timing Specifications ............................................................................................................... 46 Table 48. High Speed SDMMC Interface Transmit/Receive Timing Constants ............................................................. 47 Table 49. SPI Interface Transmit/ Receive Timing Constants with 15pF Load .............................................................. 49 Table 50. SPI Interface Transmit/ Receive Timing Constants with 30pF Load .............................................................. 50 2 Table 51. I C BUS Controller Module Signal Timing.......................................................................................................... 51 Table 52. Wi-Fi® 2.4GHz Receiver RF Specifications......................................................................................................... 52 Table 53. Wi-Fi® 2.4GHz Transmitter RF Specifications ................................................................................................... 53 Table 54. Wi-Fi® 5GHZ Receiver RF Specifications ........................................................................................................... 54 Table 55. Wi-Fi® 5GHz Transmitter RF Specifications ...................................................................................................... 54 Table 56. Bluetooth® RF Specifications ............................................................................................................................. 55 Table 57. Bluetooth® Transmitter RF Specifications ........................................................................................................ 55 Table 58. BLE RF Specifications ........................................................................................................................................... 55 Table 59. 802.15.4 RF Receive Specifications .................................................................................................................... 56 Table 60. 802.15.4 RF Transmit Specifications .................................................................................................................. 56 Table 61. L-Shaped Ball Locations ...................................................................................................................................... 59 6 Revision Date V1.0 January 20, 2017 Description ARTIK 530 datasheet. Maturity Release 7 ® ® Figure 1 shows the functional block diagram of the ARTIK 530 Module. It consists of a quad-core ARM Cortex -A9 application ® ® processor with 512MB of DDR3 and 4GB eMMC, PMIC power management, Secure Element, Wi-Fi /Bluetooth , 802.15.4 and RF connectors. Warning : Do not apply power to the ARTIK 530 Module before connecting antennas or damage to the Module may result! 8 The sub-sections that will follow describe the functions of the various blocks depicted in Figure 1 that are present on the ARTIK 530 Module. The ARTIK 530 Module provides a GPIO system with up to 107 GPIOs (76 multiplexed, 31 dedicated) to allow for a wide variety of use cases to be supported. The key features of the GPIO system are: Programmable pull-up control Both edge detect and level detect functionality Support for programmable pull-up resistors Support for fast or normal slew operation Support for default Drive Strength or High Drive Strength Support for interrupt generation that can be triggered on:  Rising edge  Falling edge  High level detection  Low level detection  The I/O data is clocked up to 50MHz       2 2 The ARTIK 530 Module provides two 5-line Inter-IC Sound (I S) channel. I S is one of the most popular digital audio interfaces. 2 The I S bus handles audio data and other signals, such as sub-coding and control. It is possible to transmit data between two 2 2 I S buses. The key features of the I S sub-system are: 2  Supports 1-port stereo (1 channel) I S-bus for audio with DMA based operation  Supports serial data transfer of 16/24-bit per channel in Master and Slave mode  Supports a variety of interface modes: 2  I S, Left justified, Right justified, DSP mode The ARTIK 530 Module provides two pulse width modulation (PWM) modules. The key features of the PWM modules are:       Two individual PWM channels with independent duty control and polarity Two 32-bit PWM timers, one per channel Support for static as well as dynamic setup Support for auto-reload and one shot pulse mode Dead zone generator Level interrupt generation The ARTIK 530 Module provides two, Serial Peripheral Interfaces (SPI) that transfers serial data. SPI support includes 8-bit/16-bit shift registers to transmit and receive data. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The SPI implementation adheres to the protocols described by Texas Instruments Synchronous Serial, National Semiconductor’s Microwire and Motorola’s Serial Peripheral Interface. The key features of the SPI sub-system are:        Support for full-duplex 8-bit/16-bit shift register for Tx and Rx Complies with the SPI protocol described by Texas Instruments, National Semiconductor and Motorola Support for independent 16-bit wide transmit and receive FIFOs 8 locations deep Supports for master mode and slave mode Supports for receive-without-transmit operation Max operating frequency :  Master Mode : Support Tx up to 50MHz, Rx up to 20MHz 9  Slave Mode : Support Tx up to 8MHz, Rx up to 8MHz The ARTIK 530 Module provides three 2-pin universal asynchronous receiver transmitters (UARTs). The key features of the UART sub-system are:      Separate 32x8 Tx and 32x12 Rx FIFO memory buffers Support for DMA mode (UART0 : [AP_UART_RX0, AP_UART_TX0] only) and interrupt based mode of operation All independent channels support IrDA 1.0 Support for modem control functions CTS, DCD, DSR, RTS, DTR and RI Each UART channel contains:  Programmable baud-rates  1 or 2 stop bit insertion  5-bit, 6-bit, 7-bit, or 8-bit data width  Parity checking 2 The ARTIK 530 Module provides three generic I C blocks supporting both 100kb/s and 400kb/s speed modes. 2 The key features of the I C sub-system are:        Supporting multi-master and slave mode 7-bit addressing mode only Supports serial, 8-bit oriented and bi-directional data transfer Supports up to 100 kb/s in the standard mode Supports up to 400 kb/s in the fast mode Supports master transmit, master receive, slave transmit, and slave receive operation Supports both interrupt and polling events The ADC interface controls one 28nm low power CMOS 1.8V 12-bit ADC. The key features of the ADC sub-system are:     Up to six channels of analog input can be selected Converts analog input into 12-bit binary code up to 1MSPS Power consumption 1.0mW when running 1MSPS Input frequency up to 100kHz The ARTIK 530 Module power requirements are managed using a power management integrated circuit (PMIC). This PMIC device has four fully-integrated fixed-frequency current-mode synchronous PWM step-down converters that can achieve peak efficiencies of up to 97%. In addition it provides seven low-noise LDOs with currents up to 350mA, one always-on LDO and an integrated backup battery charger that will provide all power requirements for the ARTIK 530 Module. The four DC-DC regulators operate at a fixed high frequency of 2.25MHz, minimizing noise in sensitive applications and allowing the use of small form factor components. These four buck regulators supply up to 3A of output current and can fully satisfy the power and control requirements of the ARTIK 530 Module. Dynamic Voltage Scaling (DVS) of the various core 2 voltages is supported using I C control. For a detailed description see the section on Power Supply Requirements. ® ® The ARTIK 530 Module has a fully-integrated Wi-Fi block covering IEEE 802.11 a/b/g/n Wi-Fi . The most important hardware ® features of the Wi-Fi module are: ®  Wi-Fi 802.11 a/b/g/n dual band SISO, 2.4GHz/5GHz compliant  1T1R 2.4GHz/5GHz band 10  Support for 20 and 40MHz bandwidth (72.2/150Mbps PHY rate) ® ®  Enhanced Wi-Fi /Bluetooth Coexistence control to improve transmission quality in different profiles ® The ARTIK 530 Module has a fully-integrated Bluetooth block 4.2 (BLE+Classic). The most important hardware features of the ® Bluetooth module are: ®  Bluetooth 4.2 (BLE+Classic) ® ®  Enhanced Wi-Fi /Bluetooth Coexistence control to improve transmission quality in different profiles The ARTIK 530 Module carries fully-integrated 802.15.4 functionality. The most important hardware features are:        Fully integrated 2.4 GHz, IEEE 802.15.4 compliant transceiver ® ® Complete system-on-chip using 32-bit ARM Cortex -M4 processor Flash and RAM memory and peripherals. Extremely low power consumption. Excellent RF performance. Single-voltage operation. Supported Protocols:  ZigBee  Thread The ARTIK 530 Module provides one USB2.0 OTG interface supporting both device and host functionality. The key features of the USB2.0 OTG sub-system are: In compliance with the USB 2.0 on-the-go specification revision 1.3a and 2.0 Operates in high speed (480Mbps) mode Operates in full speed (12Mbps) mode Operates in low speed (1.5Mbps, host only) mode Supports session request protocol (SRP) and host negotiation protocol (HNP) One control endpoint 0 for control transfer Supports up to 15 device-programmable endpoints:  Programmable endpoint type: Bulk, Isochronous, Interrupt  Programmable In/Out direction  Supports 16 host channels        The ARTIK 530 Module provides one USB2.0 Host controller that is fully compliant with the USB 2.0 specifications, and the enhanced host controller Interface (EHCI) specification. The key features of the USB2.0 OTG sub-system are:       Detecting the attachment and removal of USB devices Collecting status and activity statistics Controlling power supply to attached USB devices In compliance with the UTMI+ Level 3 revision 1.0 Controlling the association to either the open host controller interface (OHCI) or the EHCI via a port router Root Hub functionality to support up/down stream port The ARTIK 530 Module provides one high speed inter chip (HSIC) version 1.0 module. The key features of the HSIC sub-system are:  Support for ping and split transactions  Up to 30MHz operation for a 16-bit interface  Up to 60MHz operation for a 8-bit interface 11  Support for HSIC version 1.0 The ARTIK 530 Module provides one 4-lane mobile industry processor interface (MIPI) interface that complies with the MIPI camera serial interface (CSI) standard specification V1.01r06 and D-PHY standard specification v1.0. The key features of the MIPI CSI sub-system are:  Supports 1, 2, 3 or 4 data lanes  Supported image formats are:  YUV420, YUV420 (Legacy), YUV420 (CSPS), 8-bit YUV422, 10-bit YUV422  User defined Byte based data packet  Compatible to PPI (Protocol to PHY interface) The ARTIK 530 Module provides one 4-lane MIPI interface that complies with the MIPI DSI standard specification V1.01r11. The key features of the MIPI DSI sub-system are:  Maximum resolution ranges up to 1920x1080  Supports 1, 2, 3 or 4 data lanes  Supports pixel format:  16bpp, 18bpp packed, 18bpp loosely packed (3 byte), 24bpp  Supported interfaces are:  Protocol-to-PHY Interface (PPI) up to 1.5Gbps, in MIPI D-PHY  RGB Interface for video image input from display controller  PMS control interface for PLL to configure byte clock frequency  Pre-scaler to generate escape clock from byte clock The ARTIK 530 Module provides one HDMI v1.4a interface. The key features of the HDMI sub-system are: Support for v1.4a spec Up to 1080p video resolution HDMI Link + HDMI PHY Support for the following video formats:  480p@59.94/60Hz  576p@50Hz  720p@50/59.94/60Hz  1080p@50/59.94/60Hz (No support for interlaced format)  Support for 4:4:4 RGB  Support for up to 8-bits per color     The ARTIK 530 Module provides five low voltage differential signaling (LVDS) output channels with one clock channel. The key features of the LVDS channel system are:     Output clock range 30-125MHz Support for 630 Mbps per channel Up to 393.75MB/s data transport Support for power down mode The ARTIK 530 Module provides one Gigabit EMAC interface. The most important features of the Ethernet MAC module are:  Standard compliance  IEEE 802.3az-2010: energy efficient Ethernet (EEE)  RGMII v2.6 12  MAC supports the following features:  10/100/1000 Mbps data transfer rates with an RGMII interface to communicate with external Gigabit PHY  Full duplex operation  Half duplex operation  Flexible address filtering  Additional frame filtering The ARTIK 530 Module provides one shared SD-card/MMC interface. The Mobile Storage Host is an interface between the system and the SD-card. The key features of mobile storage host sub-system are:       Support for Secure Digital I/O (SDIO – version 3.0) Support for Secure Digital Memory (SDMEM – version 3.0) Support for Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1) Support 4-bit SDR mode up to 50MHz Supports PIO and DMA mode data transfer Supports ¼- bit data bus width The ARTIK 530 Module provides one shared SD-card/MMC interface. The Mobile Storage Host is an interface between the system and MMC card. The key features of mobile storage host sub-system are:      Support for Embedded Multimedia Cards (MMC – version 4.41) Support for Embedded Multimedia Cards (eMMC – version 4.5) Support 4-bit SDR mode up to 50MHz Supports PIO and DMA mode data transfer Supports ¼- bit data bus width The ARTIK 530 Module has DDR memory. The key features of the DDR memory present on the ARTIK 530 Module are:  One 32-bit DDR3 memory interface  Two 256MB DDR3 16-bit memory chips, for a total of 512MB  Up to 800MHz DDR3 speed with a maximum throughput of 6.4GB/s Our JTAG core that is part of the ARTIK 530 Module provides debug capabilities for the developer. The main features of the JTAG module are:  Compliant with the IEEE 1149 standard  Can only be used together with the ARTIK 530 Module. The ARTIK 530 Module has a dedicated Secure Element to assure end-to-end authentication and communication between nodes in an IoT setting. The Secure Element provides an ISO/IEC 7816 14443 compliant interface. The most important hardware features of the Secure Element are:  Dedicated 16-bit SecuCalm CPU core  Crypto co-processor  Modular exponential accelerator  RSA 2080 bits  ECC 512 bits  Data security  Memory encryption for all memory  256B read only and 256B non erasable flash area  Selective reset operation if abnormal voltages/frequencies are detected 13  Embedded tamper-free memory  32KB ROM  264KB FLASH  (6+2.5)KB Static RAM including 2.5KB crypto memory  Serial interfaces:  ISO 7816-3 compliant interface  Asynchronous half-duplex character receive/transmit serial interface The processor system architecture that resides on the ARTIK 530 Module is a system-on-a-chip (SoC) based on a 32-bit RISC architecture. Designed using the 28nm low power process, the processor system architecture provides superior performance using a quad-core CPU. The key features of the ARTIK 530 Module are:       ® ® Quad-core ARM Cortex -A9, 32-bit RISC architecture Maximum core speed 1.2GHz 32KB I-Cache per core 32KB D-Cache per core 1024KB L2-Cache shared between four cores Support for dynamic virtual-address mapping The ARTIK 530 Module has one pulse period measurement (PPM) IP-block that can measure the duration of a high level or low level from a GPIO pin. The most important features of the PPM block are:  One 16-bit counter tied to a clock that can vary between 843.75kHz and 13.50MHz For more details on how to relate a PPM to a GPIO please refer to the ARTIK 530 Module software developer’s guide. The ARTIK 530 Module has four dedicated timer channels. The most important features of the Timer module are:      Timer or watchdog timer modes Four dedicated Timer channels with watchdog timer Normal interval timer mode with interrupt request Reset on timer countdown Level-triggered interrupt mechanism The ARTIK 530 Module has one interrupt module. The most important features of the interrupt module are:  Vectored Interrupt Controller  Support 64x channel interrupt sources  For each interrupt source the following properties are available:  Fixed hardware interrupt priority level  Programmable interrupt priority level  Hardware interrupt priority level masking  IRQ and FIQ generation  Software interrupt generation  Test registers  Raw interrupt status  Interrupt request status The ARTIK 530 Module has one scatter-gather DMA module. The most important features of the DMA module are:  16x channels of dedicated DMA 14  16x DMA request lines  Various operating modes  Single DMA mode  Burst DMA mode  Memory to memory transfer  Memory to peripheral transfer  Peripheral to memory transfer  Peripheral to peripheral transfer  Support for 8/16/32 bit wide transactions  Big endian and little endian (default) support The ARTIK 530 Module has one real time clock (RTC) module. The most important features of the RTC are:     Four spread spectrum PLLs Two external crystals : one 24MHz crystal for PLL, one 32.768KHz crystal for RTC 32-bit RTC counter Support for alarm interrupt using RTC The ARTIK 530 Module provides one video input processor (VIP). The key features of the VIP sub-system are:      Support for external 8-bit and 16-bit MIPI-DSI Support for internal MIPI-CSI Support of images up to 8192x8192 Support for clipping and scale-down Support for YUV420 memory format The ARTIK 530 Module provides one universal scaler. The key features of the scaler are:  Support for different input formats  YUV420, YUV422, YUV444  Flexible size, from 8x8 up to 1920x1080 with a granularity of 8  Upscale ratio from 8x8 to 1920x1080  Downscale ratio from 1920x1080 to 8x8  Low pass filter available after upscale or before downscale  Horizontal 5-tab filter with 64 sets of coefficients  Vertical 3-tab filter with 32 sets of coefficients The ARTIK 530 Module provides one integrated Multi Format Codec (MFC) module. The key features of the MFC sub-system are:  Decoder  H.264 : BP, MP, HP Level 4.2 up to 1920x1080, up to 50MBps  MPEG4 : Advanced Simple Profile (ASP) up to 1920x1080, up to 40Mbps  H.263 : Profile 3 up to 1920x1080, up to 20Mbps  MPEG 1,2 : Main Profile, High Level up to 1920x1080, up to 80MBps  Encoder  H.264 : Baseline profile, Level 4.0 up to 1080p, up to 20Mbps  MPEG4 : Simple profile, Level 5.6 up to 1080p, up to 20Mbps  H.263 : Profile 3, Level 70 up to 1080p, up to 20Mbps 15 The ARTIK 530 Module provides one 2D and 3D graphics pipeline module. The key features of the graphics pipeline are:  Two pixel processors  Tile oriented processing  Alpha blending  Texture support, non-power-of-2  Cube mapping  Fast dynamic branching  Trigonometric acceleration  Full floating point arithmetic  Line, quad, triangle and point sprites  Perspective correct texturing  Point sampling, bilinear and trilinear filtering  8-bit stencil buffering  4-level hierarchical Z and stencil operation  Geometry processor  Programmable vertex shader  Flexible input and output formats  Autonomous operation tile list generation  Indexed and non-indexed geometry input  Primitive constructions with points, lines, triangles and quads  Support for OpenGL ES 1.0 and 2.0 16 The ARTIK 530 Module utilizes 300 signal and ground BALLs providing all the relevant signaling. Figure 2 shows how the BALLs are oriented and how signal coordinates are assigned to the PADs of the ARTIK 530 Module. Table 2, Error! Reference source not found., Table 4 and Table 5 describe the relation between the BALL coordinates and the BALL signal names. Table 2, Error! Reference source not found., Table 4 and Table 5 also provide detailed characteristics for each BALL signal name. 17 The meaning of the various columns used in Table 2 - Table 6 is explained in Table 1. Column Name Ball Loc Ball Name Column Definition Identifier of the Ball on the ARTIK 530 Module Default function of the ARTIK 530 Module Power Voltage level on the Ball Default Internal default function of the main SoC I/O Type S=Signal Ball I/O I=Input, O=Output, IO=Input/Output PU/PD PU=Pull-Up, PD=Pull-Down, N=No Pull-Up or Pull-Down Group Default pin group set to work with the Interposer Board. For more information see ARTIK 530 Module Hardware User Guide. Usually the function of the pin can be reprogrammed Function Explanation on the function of the ball 18 Ball Loc Ball Name Power Default PA1 GMAC_TXEN 3V3 GMAC_TXEN I/O Type I/O PU/PD Group S IO N GMAC GMAC Transmit Enable Function PA2 GMAC_TXD1 3V3 GMAC_TXD1 S IO N GMAC GMAC Transmit Data 1 PA3 GMAC_TXD3 3V3 GMAC_TXD3 S IO N GMAC GMAC Transmit Data 3 NA PA4 NO BALL - - - - - NO BALL PA5 GMAC_GTXCLK 3V3 GMAC_GTXCLK S IO N GMAC GMAC Transmit Clock PA6 GMAC_RXDV 3V3 GMAC_RXDV S IO N GMAC GMAC Receive Enable PA7 GMAC_RXD2 3V3 GMAC_RXD2 S IO N GMAC GMAC Receive Data 2 PA8 GMAC_RXD0 3V3 GMAC_RXD0 S IO N GMAC GMAC Receive Data 0 PA9 GND 0V0 GND NA 0V0 - GND Ground PA10 AP_MIPICSI_DNCLK 1V8 MIPICSI_DNCLK S IO N CSI MIPI CSI Data Negative Clock PA11 AP_MIPICSI_DN0 1V8 MIPICSI_DN0 S IO N CSI MIPI CSI Data Negative 0 PA12 AP_MIPICSI_DN1 1V8 MIPICSI_DN1 S IO N CSI MIPI CSI Data Negative 1 PA13 AP_MIPICSI_DN2 1V8 MIPICSI_DN2 S IO N CSI MIPI CSI Data Negative 2 PA14 AP_MIPICSI_DN3 1V8 MIPICSI_DN3 S IO N CSI MIPI CSI Data Negative 3 PA15 GND 0V0 GND NA 0V0 - GND Ground PA16 AP_MIPIDSI_DNCLK 1V8 MIPIDSI_DNCLK S IO N DSI MIPI DSI Data Negative Clock PA17 AP_MIPIDSI_DN0 1V8 MIPIDSI_DN0 S IO N DSI MIPI DSI Data Negative 0 PA18 AP_MIPIDSI_DN1 1V8 MIPIDSI_DN1 S IO N DSI MIPI DSI Data Negative 1 PA19 AP_MIPIDSI_DN2 1V8 MIPIDSI_DN2 S IO N DSI MIPI DSI Data Negative 2 PA20 AP_MIPIDSI_DN3 1V8 MIPIDSI_DN3 S IO N DSI MIPI DSI Data Negative 3 PA21 GND 0V0 GND NA 0V0 - GND Ground PA22 AP_LVDS_TN0 1V8 LVDS_TN0 S IO N LVDS LVDS Transmit Channel 0 Negative PA23 AP_LVDS_TN1 1V8 LVDS_TN1 S IO N LVDS LVDS Transmit Channel 1 Negative PA24 AP_LVDS_TN2 1V8 LVDS_TN2 S IO N LVDS LVDS Transmit Channel 2 Negative PA25 AP_LVDS_TNCLK 1V8 LVDS_TNCLK S IO N LVDS LVDS Transmit Negative Clock PA26 AP_LVDS_TN3 1V8 LVDS_TN3 S IO N LVDS LVDS Transmit Channel 3 Negative PA27 AP_LVDS_TN4 1V8 LVDS_TN4 S IO N LVDS LVDS Transmit Channel 4 Negative PA28 GND 0V0 GND NA 0V0 - GND Ground PA29 AP_HDMI_CEC 3V3 SA3 S IO N HDMI HDMI Consumer Electronics Control PA30 AP_HDMI_TX2N 1V8 HDMI_TXN2 S O N HDMI HDMI Transmit Channel 1 Negative PA31 AP_HDMI_TX1N 1V8 HDMI_TXN1 S O N HDMI HDMI Transmit Channel 0 Negative PA32 AP_HDMI_TX0N 1V8 HDMI_TXN0 S O N HDMI HDMI Transmit Channel 2 Negative PA33 AP_HDMI_TXCN 1V8 HDMI_TXNCLK S O N HDMI HDMI Transmit Negative Clock PA34 GND 0V0 GND NA 0V0 - GND Ground PA35 AP_OTG_DM 3V3 USB2.0OTG_DM S IO N USB OTG USB OTG Data Minus PA36 AP_USBH_DM 3V3 USB2.0HOST_DM S IO N USB HOST USB HOST Data Plus PA37 AP_GPA13 3V3 DISD12 S IO N GPIO Generic GPIO PA38 AP_HSIC_STROBE 1V2 USBHSIC_STROBE S IO N HSIC HSIC Strobe PA39 AP_GPA14 3V3 DISD13 S IO N GPIO Generic GPIO PA40 AP_GPA9 3V3 DISD8 S IO N GPIO Generic GPIO PA41 AP_GPA15 3V3 DISD14 S IO N GPIO Generic GPIO PA42 AP_GPA12 3V3 DISD11 S IO N GPIO Generic GPIO PB1 GND 0V0 GND NA 0V0 - GND Ground PB2 GMAC_TXD0 3V3 GMAC_TXD0 S IO N GMAC GMAC Transmit Data 0 PB3 GMAC_TXD2 3V3 GMAC_TXD2 S IO N GMAC GMAC Transmit Data 2 19 Ball Loc Ball Name Power Default PB4 GMAC_MDC 3V3 GMAC_MDC I/O Type I/O PU/PD Group S IO N GMAC Function PB5 GMAC_RXCLK 3V3 GMAC_RXCLK S IO N GMAC GMAX Receive Clock PB6 GMAC_RXD3 3V3 GMAC_RXD3 S IO N GMAC GMAC Receive Data 3 PB7 GMAC_RXD1 3V3 GMAC_RXD1 S IO N GMAC GMAC Receive Data 1 PB8 GMAC_MDIO 3V3 GMAC_MDIO S IO N GMAC GMAC MDIO PB9 GND 0V0 GND NA 0V0 - GND Ground PB10 AP_MIPICSI_DPCLK 1V8 MIPICSI_DPCLK S IO N CSI MIPI CSI Data Positive Clock PB11 AP_MIPICSI_DP0 1V8 MIPICSI_DP0 S IO N CSI MIPI CSI Data Positive 0 PB12 AP_MIPICSI_DP1 1V8 MIPICSI_DP1 S IO N CSI MIPI CSI Data Positive 1 PB13 AP_MIPICSI_DP2 1V8 MIPICSI_DP2 S IO N CSI MIPI CSI Data Positive 2 PB14 AP_MIPICSI_DP3 1V8 MIPICSI_DP3 S IO N CSI MIPI CSI Data Positive 3 PB15 GND 0V0 GND NA 0V0 - GND Ground PB16 AP_MIPIDSI_DPCLK 1V8 MIPIDSI_DPCLK S IO N DSI MIPI DSI Data Positive Clock PB17 AP_MIPIDSI_DP0 1V8 MIPIDSI_DP0 S IO N DSI MIPI DSI Data Positive 0 PB18 AP_MIPIDSI_DP1 1V8 MIPIDSI_DP1 S IO N DSI MIPI DSI Data Positive 1 PB19 AP_MIPIDSI_DP2 1V8 MIPIDSI_DP2 S IO N DSI MIPI DSI Data Positive 2 PB20 AP_MIPIDSI_DP3 1V8 MIPIDSI_DP3 S IO N DSI MIPI DSI Data Positive 3 PB21 GND 0V0 GND NA 0V0 - GND Ground PB22 AP_LVDS_TP0 1V8 LVDS_TP0 S IO N LVDS LVDS Transmit Channel 0 Positive PB23 AP_LVDS_TP1 1V8 LVDS_TP1 S IO N LVDS LVDS Transmit Channel 1 Positive PB24 AP_LVDS_TP2 1V8 LVDS_TP2 S IO N LVDS LVDS Transmit Channel 2 Positive PB25 AP_LVDS_TPCLK 1V8 LVDS_TPCLK S IO N LVDS LVDS Transmit Positive Clock PB26 AP_LVDS_TP3 1V8 LVDS_TP3 S IO N LVDS LVDS Transmit Channel 3 Positive PB27 AP_LVDS_TP4 1V8 LVDS_TP4 S IO N LVDS LVDS Transmit Channel 4 Positive PB28 GND 0V0 GND NA 0V0 - GND Ground PB29 AP_HDMI_HPD 3V3 HDMI_HOT5V S I N HDMI HDMI Hot 5V PB30 AP_HDMI_TX2P 1V8 HDMI_TXP2 S O N HDMI HDMI Transmit Channel 1 Positive PB31 AP_HDMI_TX1P 1V8 HDMI_TXP1 S O N HDMI HDMI Transmit Channel 0 Positive PB32 AP_HDMI_TX0P 1V8 HDMI_TXP0 S O N HDMI HDMI Transmit Channel 2 Positive PB33 AP_HDMI_TXCP 1V8 HDMI_TXPCLK S O N HDMI HDMI Transmit Positive Clock PB34 GND 0V0 GND NA 0V0 - GND Ground USB OTG Data Plus GMAC MDC PB35 AP_OTG_DP 3V3 USB2.0OTG_DP S IO N USB OTG PB36 AP_USBH_DP 3V3 USB2.0HOST_DP S IO N USB HOST USB HOST Data Minus PB37 AP_OTG_ID - USB2.0OTG_ID S IO N USB HOST USB HOST ID PB38 AP_HSIC_DATA 1V2 USBHSIC_DATA S IO N HSIC HSIC Data PB39 AP_GPA4 3V3 DISD3 S IO N GPIO Generic GPIO PB40 AP_GPA5 3V3 DISD4 S IO N GPIO Generic GPIO PB41 AP_GPA16 3V3 DISD15 S IO N GPIO Generic GPIO PB42 AP_GPA11 3V3 DISD10 S IO N GPIO Generic GPIO 20 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PAK1 AP_I2S0_DOUT 3V3 I2SDOUT0 S IO N I2S0 I2S 0 Data Out PAK2 AP_I2S0_BCLK 3V3 I2SBCLK0 S IO N I2S0 I2S 0 Bit Clock PAK3 AP_GPC11_SPI2_MISO 3V3 SA11 S IO N SPI2 SPI 2 Receive Data PAK4 AP_GPC9_SPI2_CLK 3V3 SA9 S IO N SPI2 SPI 2 Clock PAK5 AP_SPI0_MISO 3V3 SPIRXD0 S IO N SPI0 SPI 0 Receive Data PAK6 AP_SPI0_CLK 3V3 SPICLK0 S IO N SPI0 SPI 0 Clock PAK7 AP_GPC14_PWM2 3V3 SA14 S IO N PWM PWM 2 PAK8 AP_GPD6_SCL2 3V3 SCL2 S IO N I2C I2C SCL PAK9 AP_GPD4_SCL1 3V3 SCL1 S IO N I2C I2C SCL 1 PAK10 AP_GPD2_SCL0 3V3 SCL0 S IO N I2C I2C SCL 0 PAK11 AP_GPA23_HDMI_I2C_SCL 3V3 DISD22 S IO N I2C HDMI I2C SCL PAK12 ZB_DEBUG_TDO_SWO 3V3 - - - - 802.15.4 802.15.4 JTAG TMS PAK13 ZB_PTI_DATA_FRC_DOUT 3V3 - - - - 802.15.4 802.15.4 JTAG TCK PAK14 ZB_DEBUG_TCK_SWCLK 3V3 - - - - 802.15.4 802.15.4 Control PAK15 COMBO_ZIG_UART_TXD 3V3 - - - - 802.15.4 802.15.4 Control PAK16 GND 0V0 GND NA 0V0 - GND Ground PAK17 VCC3P3_SYS 3V3 - NA 3V3 - POWER 0.9-3.5V, 300mA PAK18 VCC3P3_SYS 3V3 - NA 3V3 - POWER 0.9-3.5V, 300mA PAK19 AP_NBATTF 3V3 AP_nBATTF - NA - MISC Battery PAK20 AP_GPE2 3V3 VID0_6 S IO N MISC Miscellaneous PAK21 AP_GPE1 3V3 VID0_5 S IO N MISC Miscellaneous PAK22 AP_UART_TX3 3V3 UARTTXD3 S IO N UART UART Transmit Data 3 PAK23 AP_UART_TX4 3V3 SD13 S IO N UART UART Transmit Data 4 PAK24 AP_UART_TX0 3V3 UARTTXD0 S IO N UART UART Transmit Data 5 PAK25 AP_GPB0_VID1_1_I2SLRCK1 3V3 VID1_1 S IO N I2S1 I2S 1 Left Right Clock PAK26 AP_GPA28_I2SMCLK1 3V3 VICLK1 S IO N I2S1 I2S 1 Master Clock PAK27 AP_GPA30_VID1_0_I2SBCLK1 3V3 VID1_0 S IO N I2S1 I2S 1 Bit Clock PAK28 AP_SD0_CMD 3V3 SDCMD0 S IO N SD/MMC SD Command PAK29 AP_SD0_D1 3V3 SDDAT0_1 S IO N SD/MMC SD Data 1 PAK30 AP_SD0_CLK 3V3 SDCLK0 S IO N SD/MMC SD Clock PAK31 NC - - - - - NC Not Connected PAK32 AP_GPB13_SD0_BOOT 3V3 SD0 S IO N BOOTING Select Booting Scenario PAK33 AP_GPC17 3V3 SA17 S IO N GPIO Generic GPIO PAK34 AP_GPC0 3V3 SA0 S IO N GPIO Generic GPIO PAK35 AP_GPC26 3V3 RDNWR S IO PU GPIO Generic GPIO PAK36 AP_GPB8 3V3 VID1_5 S IO N GPIO Generic GPIO PAK37 AP_GPB14 3V3 RNB0 S IO N MISC Miscellaneous PAK38 AP_GPA20 3V3 DISD19 S IO N GPIO Generic GPIO PAK39 AP_GPA18 3V3 DISD17 S IO N GPIO Generic GPIO PAK40 AP_GPA21 3V3 DISD20 S IO N GPIO Generic GPIO PAK41 AP_GPA10 3V3 DISD9 S IO N GPIO Generic GPIO PAK42 AP_GPA6 3V3 DISD5 S IO N GPIO Generic GPIO PAL1 AP_I2S0_DIN 3V3 I2SDIN0 S IO N I2S0 I2S 0 Data In PAL2 AP_I2S0_MCLK 3V3 I2SMCLK0 S IO N I2S0 I2S 0 Master Clock PAL3 AP_GPC12_SPI2_MOSI 3V3 SA12 S IO N SPI2 SPI 2 Transmit Data PAL4 AP_GPC10_SPI2_CS 3V3 SA10 S IO PU SPI2 SPI 2 Frame PAL5 AP_SPI0_MOSI 3V3 SPITXD0 S IO N SPI0 SPI 0 Transmit Data 21 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PAL6 AP_SPI0_CS 3V3 SPIFRM0 S IO N SPI0 SPI 0 Frame PAL7 AP_GPD1_PWM0 3V3 PWM0 S IO N PWM PWM 0 PAL8 AP_GPD7_SDA2 3V3 SDA2 S IO N I2C I2C SDA I2C SDA 1 PAL9 AP_GPD5_SDA1 3V3 SDA1 S IO N I2C PAL10 AP_GPD3_SDA0 3V3 SDA0 S IO N I2C I2C SDA 0 PAL11 AP_GPA24_HDMI_I2C_SDA 3V3 DISD23 S IO N I2C HDMI I2C SDA PAL12 ZB_DEBUG_TMS_SWDIO 3V3 - - - - 802.15.4 802.15.4 JTAG TDI PAL13 ZB_PTI_SYNC_FRC_DFRAME 3V3 - - - - 802.15.4 802.15.4 JTAG TDO PAL14 PAD_ZB_RSTN 3V3 - - - - 802.15.4 802.15.4 Reset PAL15 COMBO_ZIG_UART_RXD 3V3 NSCS1 S IO PU 802.15.4 802.15.4 Control PAL16 GND 0V0 GND NA 0V0 - GND Ground PAL17 VCC3P3_SYS 3V3 - NA 3V3 - POWER 0.9-3.5V, 300mA PAL18 VCC3P3_SYS 3V3 - NA 3V3 - POWER 0.9-3.5V, 300mA PAL19 AP_VDDPWRON 3V3 VDDPWRON S O N MISC VDD Power On PAL20 AP_GPE3 3V3 VID0_7 S IO N MISC Miscellaneous PAL21 AP_GPE0 3V3 VID0_4 S IO N MISC Miscellaneous PAL22 AP_UART_RX3 3V3 UARTRXD3 S IO N UART UART Receive Data 3 PAL23 AP_UART_RX4 3V3 SD12 S IO N UART UART Receive Data 4 PAL24 AP_UART_RX0 3V3 UARTRXD0 S IO N UART UART Receive Data 5 PAL25 AP_GPD31 3V3 VID0_3 S IO N MISC Miscellaneous PAL26 AP_GPB9_I2SDIN1 3V3 VID1_6 S IO N I2S1 I2S 1 Data In PAL27 AP_GPB6_VID1_4_I2SDOUT1 3V3 VID1_4 S IO N I2S1 I2S 1 Data Out PAL28 AP_SD0_D3 3V3 SDDAT0_3 S IO N SD/MMC SD Data 3 PAL29 AP_SD0_D2 3V3 SDDAT0_2 S IO N SD/MMC SD Data 2 PAL30 AP_SD0_D0 3V3 SDDAT0_0 S IO N SD/MMC SD Data 0 PAL31 AP_GPB4_VID1_3_BOOT 3V3 VID1_3 S IO N BOOTING Select Booting Scenario PAL32 AP_GPB15_SD1_BOOT 3V3 SD1 S IO N BOOTING Select Booting Scenario PAL33 AP_GPD8 3V3 PPM S IO N GPIO Generic GPIO PAL34 AP_GPE30 3V3 NSOE S IO PU GPIO Generic GPIO PAL35 AP_GPC27 3V3 NSDQM S IO PU GPIO Generic GPIO PAL36 AP_GPB22 3V3 SD6 S IO N GPIO Generic GPIO PAL37 AP_GPB16 3V3 NNFOE0 S IO N MISC Miscellaneous PAL38 AP_GPB23 3V3 SD7 S IO N GPIO Generic GPIO PAL39 AP_GPA22 3V3 DISD21 S IO N GPIO Generic GPIO PAL40 AP_GPA19 3V3 DISD18 S IO N GPIO Generic GPIO PAL41 AP_GPA17 3V3 DISD16 S IO N GPIO Generic GPIO PAL42 AP_GPA3 3V3 DISD2 S IO N GPIO Generic GPIO 22 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PC1 GND 0V0 GND NA 0V0 - GND Ground PC2 NO BALL - - - - - NO BALL NA PD1 GND 0V0 GND NA 0V0 - GND Ground PD2 NO BALL - - - - - NO BALL NA PE1 GND 0V0 GND NA 0V0 - GND Ground PE2 GND 0V0 GND NA 0V0 - GND Ground PF1 GND 0V0 GND NA 0V0 - GND Ground PF2 GND 0V0 GND NA 0V0 - GND Ground PG1 GND 0V0 GND NA 0V0 - GND Ground PG2 NO BALL - - - - - NO BALL NA PH1 GND 0V0 GND NA 0V0 - GND Ground PH2 NO BALL - - - - - NO BALL NA PJ1 GND 0V0 GND NA 0V0 - GND Ground PJ2 GND 0V0 GND NA 0V0 - GND Ground PK1 GND 0V0 GND NA 0V0 - GND Ground PK2 GND 0V0 GND NA 0V0 - GND Ground PL1 GND 0V0 GND NA 0V0 - GND Ground PL2 GND 0V0 GND NA 0V0 - GND Ground PM1 GND 0V0 GND NA 0V0 - GND Ground PM2 GND 0V0 GND NA 0V0 - GND Ground PN1 GND 0V0 GND NA 0V0 - GND Ground PN2 GND 0V0 GND NA 0V0 - GND Ground PP1 GND 0V0 GND NA 0V0 - GND Ground PP2 NO BALL - - - - - NO BALL NA PR1 GND 0V0 GND NA 0V0 - GND Ground PR2 GND 0V0 GND NA 0V0 - GND Ground PT1 GND 0V0 GND NA 0V0 - GND Ground PT2 GND 0V0 GND NA 0V0 - GND Ground PU1 GND 0V0 GND NA 0V0 - GND Ground PU2 NO BALL - - - - - NO BALL NA PV1 GND 0V0 GND NA 0V0 - GND Ground PV2 NO BALL - - - - - NO BALL NA PW1 AP_ADC4 1V8 ADC4 S IO N ADC ADC Channel 4 PW2 AP_ADC5 1V8 ADC5 S IO N ADC ADC Channel 5 PY1 AP_ADC0 1V8 ADC0 S IO N ADC ADC Channel 0 PY2 AP_ADC1 1V8 ADC1 S IO N ADC ADC Channel 1 PAA1 AP_ADC2 1V8 ADC2 S IO N ADC ADC Channel 2 PAA2 AP_ADC3 1V8 ADC3 S IO N ADC ADC Channel 3 PAB1 GND 0V0 GND NA 0V0 - GND Ground PAB2 GND 0V0 GND NA 0V0 - GND Ground PAC1 AP_TCK 3V3 TCLK S IO PD JTAG JTAG TCK PAC2 AP_TMS 3V3 TMS S IO PU JTAG JTAG TMS PAD1 AP_TDO 3V3 TDO S IO N JTAG JTAG TDO PAD2 AP_TDI 3V3 TDI S IO PU JTAG JTAG TDI PAE1 AP_NTRST 3V3 NTRST S IO PU JTAG JTAG NTRST PAE2 AP_AGP2_RTC_INT_N 3V3 ALIVEGPIO2 S IO N KEY/ALIVE Left Key part of AliveGPIO PAF1 AP_PWRKEY 3V3 ALIVEGPIO0 S IO N KEY/ALIVE Power Key part of AliveGPIO PAF2 AP_AGP1_HOMEKEY 3V3 ALIVEGPIO1 S IO N KEY/ALIVE Home Key part of AliveGPIO 23 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group PAG1 AP_NRESET 3V3 NRESET S I PU KEY Function Reset PAG2 AP_GPA25_BACKKEY 3V3 DISVSYNC S IO N KEY Back Key PAH1 AP_GPA26_VOLUP 3V3 DISHSYNC S IO N KEY Volume Up PAH2 AP_GPA0_MENUKEY 3V3 DISCLK S IO N KEY Menu Key PAJ1 AP_I2S0_LRCLK 3V3 I2SLRCLK0 S IO N I2S0 I2S 0 Left Right Clock PAJ2 AP_GPA27_VOLDOWN 3V3 DISDE S IO N KEY Volume Down 24 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PC39 GND 0V0 GND NA 0V0 - GND Ground PC40 GND 0V0 GND NA 0V0 - GND Ground PC41 GND 0V0 GND NA 0V0 - GND Ground PC42 GND 0V0 GND NA 0V0 - GND Ground PD41 VCC5P0_OTGVB US - - NA 5V0 - POWER USB2.0 OTG BUS Power PD42 VCC5P0_OTGVB US - - NA 5V0 - POWER USB2.0 OTG BUS Power PE41 NC - - - - - NC - PE42 NC - - - - - NC - PF41 NC - - - - - NC - PF42 GND 0V0 GND NA 0V0 - GND Ground PG41 GND 0V0 GND NA 0V0 - GND Ground PG42 GND 0V0 GND NA 0V0 - GND Ground PH41 NC - - - - NC - PH42 NC - - - - NC - PJ41 NC - - - - - NC - PJ42 GND 0V0 - - 0V0 - GND Ground PK41 GND 0V0 GND - 0V0 - GND Ground PK42 GND 0V0 GND - 0V0 - GND Ground PL41 GND 0V0 GND NA 0V0 - GND Ground PL42 GND 0V0 GND NA 0V0 - GND Ground PM41 GND 0V0 GND NA 0V0 - GND Ground PM42 GND 0V0 GND NA 0V0 - GND Ground PN41 GND 0V0 GND NA 0V0 - GND Ground PN42 GND 0V0 GND NA 0V0 - GND Ground PP41 MICOM_INT 3V3 SD14 S IO N MISC Micom Interrupt PP42 GND 0V0 GND NA 0V0 - GND Ground PR41 NC - - - - - NC - PR42 NC - - - - - NC - PT41 GND 0V0 GND NA 0V0 - GND Ground PT42 GND 0V0 GND NA 0V0 - GND Ground PU41 GND 0V0 GND NA 0V0 - GND Ground PU42 GND 0V0 GND NA 0V0 - GND Ground PV41 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PV42 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PW41 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PW42 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PY41 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PY42 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PAA41 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PAA42 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PAB41 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PAB42 VBAT_MAIN VBAT - NA - POWER Main Power Supply for Module PAC41 GND 0V0 GND NA 0V0 - GND Ground PAC42 GND 0V0 GND NA 0V0 - GND Ground PAD41 NC - - - - - NC - PAD42 NC - - - - - NC - 25 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PAE41 GND 0V0 GND NA 0V0 - GND Ground PAE42 NC - - - - - NC - PAF41 GND 0V0 GND NA 0V0 - GND Ground PAF42 GND 0V0 GND NA 0V0 - GND Ground PAG41 AP_GPB11 3V3 CLE0 S IO N GPIO Generic GPIO PAG42 AP_GPB18 3V3 NNFWE0 S IO N GPIO Generic GPIO PAH41 AP_GPC25 3V3 NSWAIT S IO PU GPIO Generic GPIO PAH42 AP_GPE31 3V3 NSWE S IO PU GPIO Generic GPIO PAJ39 BT_PCM_CLK 3V3 - - - - BT PCM PCM Clock PAJ40 BT_PCM_D_IN 3V3 - - - - BT PCM PCM Data In PAJ41 BT_PCM_D_OUT 3V3 - - - - BT PCM PCM Data Out PAJ42 BT_PCM_LRCK 3V3 - - - - BT PCM PCM LR Clock Ball Loc Ball Name Power I/O PU/PD Group Function TP282 GND 0V0 Default I/O Type GND NA 0V0 - GND Ground TP283 GND 0V0 GND NA 0V0 - GND Ground TP284 GND 0V0 GND NA 0V0 - GND Ground TP285 GND 0V0 GND NA 0V0 - GND Ground TP286 GND 0V0 GND NA 0V0 - GND Ground TP287 GND 0V0 GND NA 0V0 - GND Ground TP288 GND 0V0 GND NA 0V0 - GND Ground TP289 GND 0V0 GND NA 0V0 - GND Ground TP290 GND 0V0 GND NA 0V0 - GND Ground TP291 GND 0V0 GND NA 0V0 - GND Ground TP292 GND 0V0 GND NA 0V0 - GND Ground TP293 GND 0V0 GND NA 0V0 - GND Ground TP294 GND 0V0 GND NA 0V0 - GND Ground TP295 GND 0V0 GND NA 0V0 - GND Ground TP296 GND 0V0 GND NA 0V0 - GND Ground TP297 GND 0V0 GND NA 0V0 - GND Ground TP298 GND 0V0 GND NA 0V0 - GND Ground TP299 GND 0V0 GND NA 0V0 - GND Ground TP300 GND 0V0 GND NA 0V0 - GND Ground TP301 GND 0V0 GND NA 0V0 - GND Ground 26 This section shows the functional interfaces that are available at the PADs of the ARTIK 530 Module. The functions provided are related to the development environment used. Depending on your project you can always choose to reprogram some of the GPIOs that are currently assigned to the pre-defined functional interfaces. Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PW1 AP_ADC4 1V8 ADC4 S IO N ADC Channel 4 PW2 AP_ADC5 1V8 ADC5 S IO N ADC Channel 5 PY1 AP_ADC0 1V8 ADC0 S IO N ADC Channel 0 PY2 AP_ADC1 1V8 ADC1 S IO N ADC Channel 1 PAA1 AP_ADC2 1V8 ADC2 S IO N ADC Channel 2 PAA2 AP_ADC3 1V8 ADC3 S IO N ADC Channel 3 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK32 AP_GPB13_SD0_BOOT 3V3 SD0 S IO N Select Booting Scenario PAL31 AP_GPB4_VID1_3_BOOT 3V3 VID1_3 S IO N Select Booting Scenario PAL32 AP_GPB15_SD1_BOOT 3V3 SD1 S IO N Select Booting Scenario Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAJ39 BT_PCM_CLK 3V3 - - - - PCM Clock PAJ40 BT_PCM_D_IN 3V3 - - - - PCM Data In PAJ41 BT_PCM_D_OUT 3V3 - - - - PCM Data Out PAJ42 BT_PCM_LRCK 3V3 - - - - PCM LR Clock Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PA10 AP_MIPICSI_DNCLK 1V8 MIPICSI_DNCLK S PA11 AP_MIPICSI_DN0 1V8 MIPICSI_DN0 S IO N MIPI CSI Data Negative Clock IO N PA12 AP_MIPICSI_DN1 1V8 MIPICSI_DN1 MIPI CSI Data Negative 0 S IO N PA13 AP_MIPICSI_DN2 1V8 MIPI CSI Data Negative 1 MIPICSI_DN2 S IO N PA14 AP_MIPICSI_DN3 MIPI CSI Data Negative 2 1V8 MIPICSI_DN3 S IO N MIPI CSI Data Negative 3 PB10 PB11 AP_MIPICSI_DPCLK 1V8 MIPICSI_DPCLK S IO N MIPI CSI Data Positive Clock AP_MIPICSI_DP0 1V8 MIPICSI_DP0 S IO N MIPI CSI Data Positive 0 PB12 AP_MIPICSI_DP1 1V8 MIPICSI_DP1 S IO N MIPI CSI Data Positive 1 PB13 AP_MIPICSI_DP2 1V8 MIPICSI_DP2 S IO N MIPI CSI Data Positive 2 PB14 AP_MIPICSI_DP3 1V8 MIPICSI_DP3 S IO N MIPI CSI Data Positive 3 27 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function S IO N MIPI DSI Data Negative Clock PA16 AP_MIPIDSI_DNCLK 1V8 MIPIDSI_DNCL K PA17 AP_MIPIDSI_DN0 1V8 MIPIDSI_DN0 S IO N MIPI DSI Data Negative 0 PA18 AP_MIPIDSI_DN1 1V8 MIPIDSI_DN1 S IO N MIPI DSI Data Negative 1 PA19 AP_MIPIDSI_DN2 1V8 MIPIDSI_DN2 S IO N MIPI DSI Data Negative 2 PA20 AP_MIPIDSI_DN3 1V8 MIPIDSI_DN3 S IO N MIPI DSI Data Negative 3 S IO N MIPI DSI Data Positive Clock PB16 AP_MIPIDSI_DPCLK 1V8 MIPIDSI_DPCL K PB17 AP_MIPIDSI_DP0 1V8 MIPIDSI_DP0 S IO N MIPI DSI Data Positive 0 PB18 AP_MIPIDSI_DP1 1V8 MIPIDSI_DP1 S IO N MIPI DSI Data Positive 1 PB19 AP_MIPIDSI_DP2 1V8 MIPIDSI_DP2 S IO N MIPI DSI Data Positive 2 PB20 AP_MIPIDSI_DP3 1V8 MIPIDSI_DP3 S IO N MIPI DSI Data Positive 3 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PA1 GMAC_TXEN 3V3 GMAC_TXEN S IO N GMAC Transmit Enable PA2 GMAC_TXD1 3V3 GMAC_TXD1 S IO N GMAC Transmit Data 1 PA3 GMAC_TXD3 3V3 GMAC_TXD3 S IO N GMAC Transmit Data 3 PA5 GMAC_GTXCLK 3V3 GMAC_GTXCLK S IO N GMAC Transmit Clock PA6 GMAC_RXDV 3V3 GMAC_RXDV S IO N GMAC Receive Enable PA7 GMAC_RXD2 3V3 GMAC_RXD2 S IO N GMAC Receive Data 2 PA8 GMAC_RXD0 3V3 GMAC_RXD0 S IO N GMAC Receive Data 0 PB2 GMAC_TXD0 3V3 GMAC_TXD0 S IO N GMAC Transmit Data 0 PB3 GMAC_TXD2 3V3 GMAC_TXD2 S IO N GMAC Transmit Data 2 PB4 GMAC_MDC 3V3 GMAC_MDC S IO N GMAC MDC PB5 GMAC_RXCLK 3V3 GMAC_RXCLK S IO N GMAX Receive Clock PB6 GMAC_RXD3 3V3 GMAC_RXD3 S IO N GMAC Receive Data 3 PB7 GMAC_RXD1 3V3 GMAC_RXD1 S IO N GMAC Receive Data 1 PB8 GMAC_MDIO 3V3 GMAC_MDIO S IO N GMAC MDIO 28 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PA37 AP_GPA13 3V3 DISD12 S IO N Generic GPIO PA39 AP_GPA14 3V3 DISD13 S IO N Generic GPIO PA40 AP_GPA9 3V3 DISD8 S IO N Generic GPIO PA41 AP_GPA15 3V3 DISD14 S IO N Generic GPIO PA42 AP_GPA12 3V3 DISD11 S IO N Generic GPIO PB39 AP_GPA4 3V3 DISD3 S IO N Generic GPIO PB40 AP_GPA5 3V3 DISD4 S IO N Generic GPIO PB41 AP_GPA16 3V3 DISD15 S IO N Generic GPIO PB42 AP_GPA11 3V3 DISD10 S IO N Generic GPIO PAK33 AP_GPC17 3V3 SA17 S IO N Generic GPIO PAK34 AP_GPC0 3V3 SA0 S IO N Generic GPIO PAK35 AP_GPC26 3V3 RDNWR S IO PU Generic GPIO PAK36 AP_GPB8 3V3 VID1_5 S IO N Generic GPIO PAK38 AP_GPA20 3V3 DISD19 S IO N Generic GPIO PAK39 AP_GPA18 3V3 DISD17 S IO N Generic GPIO PAK40 AP_GPA21 3V3 DISD20 S IO N Generic GPIO PAK41 AP_GPA10 3V3 DISD9 S IO N Generic GPIO PAK42 AP_GPA6 3V3 DISD5 S IO N Generic GPIO PAL33 AP_GPD8 3V3 SD8 S IO N Generic GPIO PAL34 AP_GPE30 3V3 NSOE S IO PU Generic GPIO PAL35 AP_GPC27 3V3 NSDQM S IO PU Generic GPIO PAL36 AP_GPB22 3V3 SD6 S IO N Generic GPIO PAL38 AP_GPB23 3V3 SD7 S IO N Generic GPIO PAL39 AP_GPA22 3V3 DISD21 S IO N Generic GPIO PAL40 AP_GPA19 3V3 DISD18 S IO N Generic GPIO PAL41 AP_GPA17 3V3 DISD16 S IO N Generic GPIO PAL42 AP_GPA3 3V3 DISD2 S IO N Generic GPIO PAG41 AP_GPB11 3V3 CLE0 S IO N Generic GPIO PAG42 AP_GPB18 3V3 NNFWE0 S IO N Generic GPIO PAH41 AP_GPC25 3V3 NSWAIT S IO PU Generic GPIO PAH42 AP_GPE31 3V3 NSWE S IO PU Generic GPIO Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PA29 AP_HDMI_CEC 3V3 SA3 S IO N HDMI Consumer Electronics Control PA30 AP_HDMI_TX2N 1V8 HDMI_TXN2 S O N HDMI Transmit Channel 1 Negative PA31 AP_HDMI_TX1N 1V8 HDMI_TXN1 S O N HDMI Transmit Channel 0 Negative PA32 AP_HDMI_TX0N 1V8 HDMI_TXN0 S O N HDMI Transmit Channel 2 Negative PA33 AP_HDMI_TXCN 1V8 HDMI_TXNCLK S O N HDMI Transmit Negative Clock PB29 AP_HDMI_HPD 3V3 HDMI_HOT5V S I N HDMI Hot 5V PB30 AP_HDMI_TX2P 1V8 HDMI_TXP2 S O N HDMI Transmit Channel 1 Positive PB31 AP_HDMI_TX1P 1V8 HDMI_TXP1 S O N HDMI Transmit Channel 0 Positive PB32 AP_HDMI_TX0P 1V8 HDMI_TXP0 S O N HDMI Transmit Channel 2 Positive PB33 AP_HDMI_TXCP 1V8 HDMI_TXPCLK S O N HDMI Transmit Positive Clock 29 Ball Loc Ball Name Power Default PU/PD Function PA38 AP_HSIC_STROBE 1V2 USBHSIC_STROBE I/O Type I/O S IO N HSIC Strobe PB38 AP_HSIC_DATA 1V2 USBHSIC_DATA S IO N HSIC Data Ball Loc Ball Name Power Default I/O Type I/O PU/PD PAK8 AP_GPD6_SCL2 3V3 SCL2 S IO N Function I2C SCL PAK9 AP_GPD4_SCL1 3V3 SCL1 S IO N I2C SCL 1 PAK10 AP_GPD2_SCL0 3V3 SCL0 S IO N I2C SCL 0 PAK11 AP_GPA23_HDMI_I2C_SCL 3V3 DISD22 S IO N HDMI I2C SCL PAL8 AP_GPD7_SDA2 3V3 SDA2 S IO N I2C SDA PAL9 AP_GPD5_SDA1 3V3 SDA1 S IO N I2C SDA 1 PAL10 AP_GPD3_SDA0 3V3 SDA0 S IO N I2C SDA 0 PAL11 AP_GPA24_HDMI_I2C_SDA 3V3 DISD23 S IO N HDMI I2C SDA Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK1 AP_I2S0_DOUT 3V3 I2SDOUT0 S IO N I2S 0 Data Out PAK2 AP_I2S0_BCLK 3V3 I2SBCLK0 S IO N I2S 0 Bit Clock PAK25 AP_GPB0_VID1_1_I2SLRCK1 3V3 VID1_1 S IO N I2S 1 Left Right Clock PAK26 AP_GPA28_I2SMCLK1 3V3 VICLK1 S IO N I2S 1 Master Clock PAK27 AP_GPA30_VID1_0_I2SBCLK1 3V3 VID1_0 S IO N I2S 1 Bit Clock PAL1 AP_I2S0_DIN 3V3 I2SDIN0 S IO N I2S 0 Data In PAL2 AP_I2S0_MCLK 3V3 I2SMCLK0 S IO N I2S 0 Master Clock PAL26 AP_GPB9_I2SDIN1 3V3 VID1_6 S IO N I2S 1 Data In PAL27 AP_GPB6_VID1_4_I2SDOUT1 3V3 VID1_4 S IO N I2S 1 Data Out PAJ1 AP_I2S0_LRCLK 3V3 I2SLRCLK0 S IO N I2S 0 Left Right Clock Ball Loc Ball Name Power Default I/O Type I/O PU/PD PAC1 AP_TCK 3V3 TCLK S IO PD Function JTAG TCK PAC2 AP_TMS 3V3 TMS S IO PU JTAG TMS PAD1 AP_TDO 3V3 TDO S IO N JTAG TDO PAD2 AP_TDI 3V3 TDI S IO PU JTAG TDI PAE1 AP_NTRST 3V3 NTRST S IO PU JTAG NTRST 30 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAE2 AP_AGP2_RTC_INT_N 3V3 ALIVEGPIO2 S IO N Left Key part of AliveGPIO PAF1 AP_PWRKEY 3V3 ALIVEGPIO0 S IO N Power Key part of AliveGPIO PAF2 AP_AGP1_HOMEKEY 3V3 ALIVEGPIO1 S IO N Home Key part of AliveGPIO PAG1 AP_NRESET 3V3 NRESET S I PU Reset PAG2 AP_GPA25_BACKKEY 3V3 DISVSYNC S IO N Back Key PAH1 AP_GPA26_VOLUP 3V3 DISHSYNC S IO N Volume Up PAH2 AP_GPA0_MENUKEY 3V3 DISCLK S IO N Menu Key PAJ2 AP_GPA27_VOLDOWN 3V3 DISDE S IO N Volume Down Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PA22 AP_LVDS_TN0 1V8 LVDS_TN0 S IO N LVDS Transmit Channel 0 Negative PA23 AP_LVDS_TN1 1V8 LVDS_TN1 S IO N LVDS Transmit Channel 1 Negative PA24 AP_LVDS_TN2 1V8 LVDS_TN2 S IO N LVDS Transmit Channel 2 Negative PA25 AP_LVDS_TNCLK 1V8 LVDS_TNCLK S IO N LVDS Transmit Negative Clock PA26 AP_LVDS_TN3 1V8 LVDS_TN3 S IO N LVDS Transmit Channel 3 Negative PA27 AP_LVDS_TN4 1V8 LVDS_TN4 S IO N LVDS Transmit Channel 4 Negative PB22 AP_LVDS_TP0 1V8 LVDS_TP0 S IO N LVDS Transmit Channel 0 Positive PB23 AP_LVDS_TP1 1V8 LVDS_TP1 S IO N LVDS Transmit Channel 1 Positive PB24 AP_LVDS_TP2 1V8 LVDS_TP2 S IO N LVDS Transmit Channel 2 Positive PB25 AP_LVDS_TPCLK 1V8 LVDS_TPCLK S IO N LVDS Transmit Positive Clock PB26 AP_LVDS_TP3 1V8 LVDS_TP3 S IO N LVDS Transmit Channel 3 Positive PB27 AP_LVDS_TP4 1V8 LVDS_TP4 S IO N LVDS Transmit Channel 4 Positive Ball Loc Ball Name Power Default I/O Type I/O PU/PD PAK19 AP_nBATTF 3V3 AP_nBATTF - NA - Battery PAK20 AP_GPE2 3V3 VID0_6 S IO N Miscellaneous PAK21 AP_GPE1 3V3 VID0_5 S IO N Miscellaneous PAK37 AP_GPB14 3V3 RNB0 S IO N Miscellaneous PAL19 AP_VDDPWRON 3V3 VDDPWRON S O N VDD Power On PAL20 AP_GPE3 3V3 VID0_7 S IO N Miscellaneous PAL21 AP_GPE0 3V3 VID0_4 S IO N Miscellaneous PAL25 AP_GPD31 3V3 VID0_3 S IO N Miscellaneous PAL37 AP_GPB16 3V3 NNFOE0 S IO N Miscellaneous PP41 MICOM_INT 3V3 SD14 S IO N Miscellaneous Function 31 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK17 VCC3P3_SYS* 3V3 - NA 3V3 - POWER PAK18 VCC3P3_SYS* 3V3 - NA 3V3 - POWER PAL17 VCC3P3_SYS* 3V3 - NA 3V3 - POWER PAL18 VCC3P3_SYS* 3V3 - NA 3V3 - POWER PD41 VCC5P0_OTGVBUS - - NA 5V0 - POWER PD42 VCC5P0_OTGVBUS - - NA 5V0 - POWER PV41 VBAT_MAIN VBAT - NA - POWER PV42 VBAT_MAIN VBAT - NA - POWER PW41 VBAT_MAIN VBAT - NA - POWER PW42 VBAT_MAIN VBAT - NA - POWER PY41 VBAT_MAIN VBAT - NA - POWER PY42 VBAT_MAIN VBAT - NA - POWER PAA41 VBAT_MAIN VBAT - NA - POWER PAA42 VBAT_MAIN VBAT - NA - POWER PAB41 VBAT_MAIN VBAT - NA - POWER PAB42 VBAT_MAIN VBAT - NA - POWER *Note: VCC3P3_SYS pads are not recommended as a current source, do not drive external Ics with these pads. VCC3P3_SYS pads turn off when the ARTIK 530 Module goes sleep mode. Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK7 AP_GPC14_PWM2 3V3 SA14 S IO N PWM 2 PAL7 AP_GPD1_PWM0 3V3 PWM0 S IO N PWM 0 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK28 AP_SD0_CMD 3V3 SDCMD0 S IO N SD Command PAK29 AP_SD0_D1 3V3 SDDAT0_1 S IO N SD Data 1 PAK30 AP_SD0_CLK 3V3 SDCLK0 S IO N SD Clock PAL28 AP_SD0_D3 3V3 SDDAT0_3 S IO N SD Data 3 PAL29 AP_SD0_D2 3V3 SDDAT0_2 S IO N SD Data 2 PAL30 AP_SD0_D0 3V3 SDDAT0_0 S IO N SD Data 0 32 Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK3 AP_GPC11_SPI2_MISO 3V3 SA11 S IO N SPI 2 Receive Data PAK4 AP_GPC9_SPI2_CLK 3V3 SA9 S IO N SPI 2 Clock PAK5 AP_SPI0_MISO 3V3 SPIRXD0 S IO N SPI 0 Receive Data PAK6 AP_SPI0_CLK 3V3 SPICLK0 S IO N SPI 0 Clock PAL3 AP_GPC12_SPI2_MOSI 3V3 SA12 S IO N SPI 2 Transmit Data PAL4 AP_GPC10_SPI2_CS 3V3 SA10 S IO PU SPI 2 Frame PAL5 AP_SPI0_MOSI 3V3 SPITXD0 S IO N SPI 0 Transmit Data PAL6 AP_SPI0_CS 3V3 SPIFRM0 S IO N SPI 0 Frame Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK22 AP_UART_TX3 3V3 UARTTXD3 S IO N UART Transmit Data 3 PAK23 AP_UART_TX4 3V3 SD13 S IO N UART Transmit Data 4 PAK24 AP_UART_TX0 3V3 SD15 S IO N UART Transmit Data 5 PAL22 AP_UART_RX3 3V3 UARTRXD3 S IO N UART Receive Data 3 PAL23 AP_UART_RX4 3V3 SD12 S IO N UART Receive Data 4 PAL24 AP_UART_RX0 3V3 SD14 S IO N UART Receive Data 5 Ball Loc Ball Name Power Default PU/PD Function PA35 AP_OTG_DM 3V3 USB2.0OTG_DM S IO N USB OTG Data Minus I/O Type I/O PA36 AP_USBH_DM 3V3 USB2.0HOST_DM S IO N USB HOST Data Plus PB35 AP_OTG_DP 3V3 USB2.0OTG_DP S IO N USB OTG Data Plus PB36 AP_USBH_DP 3V3 USB2.0HOST_DP S IO N USB HOST Data Minus PB37 AP_OTG_ID - USB2.0OTG_ID S IO N USB HOST ID Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK12 ZB_DEBUG_TDO_SWO 3V3 - - - - 802.15.4 JTAG TMS PAK13 ZB_PTI_DATA_FRC_DOUT 3V3 - - - - 802.15.4 JTAG TCK PAK14 ZB_DEBUG_TCK_SWCLK 3V3 - - - - 802.15.4 Control PAK15 COMBO_ZIG_UART_TXD 3V3 - - - - 802.15.4 Control PAL12 ZB_DEBUG_TMS_SWDIO 3V3 - - - - 802.15.4 JTAG TDI PAL13 ZB_PTI_SYNC_FRC_DFRAME 3V3 - - - - 802.15.4 JTAG TDO PAL14 PAD_ZB_RSTn 3V3 - - - - 802.15.4 Reset PAL15 COMBO_ZIG_UART_RXD 3V3 NSCS1 S IO PU 802.15.4 Control 33 A number of the GPIOs can be programmed to have alternate functions beyond their default behavior using the GPIO API provided in the SW development environment. Table 29, Table 30, Table 31 and Table 32 provide the alternate functions of all the GPIOs that are available on the PADs of the ARTIK 530 Module that can be user programmed. GPIO Alternate Functions NORTH PART Ball Loc Ball Name Default Function PA1 GMAC_TXEN GMAC_TXEN IO GPIOE11 GMAC_TXEN - - GMAC PA2 GMAC_TXD1 GMAC_TXD1 IO GPIOE8 GMAC_TXD1 - - GMAC PA3 GMAC_TXD3 GMAC_TXD3 IO GPIOE10 GMAC_TXD3 - - GMAC PA5 GMAC_GTXCLK GMAC_GTXCLK IO GPIOE24 GMAC_GTXCLK - - GMAC PA6 GMAC_RXDV GMAC_RXDV IO GPIOE19 GMAC_RXDV SPITXD1 - GMAC PA7 GMAC_RXD2 GMAC_RXD2 IO GPIOE16 GMAC_RXD2 - - GMAC PA8 GMAC_RXD0 GMAC_RXD0 IO GPIOE14 GMAC_RXD0 SPICLK1 - GMAC PA29 AP_HDMI_CEC SA3 IO SA3 GPIOC3 HDMI_CEC SDnRST0 HDMI PA37 AP_GPA13 DISD12 IO GPIOA13 DISD12 - - GPIO PA39 AP_GPA14 DISD13 IO GPIOA14 DISD13 - - GPIO I/O Function 0 Function 1 Function 2 Function 3 Group PA40 AP_GPA9 DISD8 IO GPIOA9 DISD8 - - GPIO PA41 AP_GPA15 DISD14 IO GPIOA15 DISD14 - - GPIO PA42 AP_GPA12 DISD11 IO GPIOA12 DISD11 - - GPIO PB2 GMAC_TXD0 GMAC_TXD0 IO GPIOE7 GMAC_TXD0 VIVSYNC1 - GMAC PB3 GMAC_TXD2 GMAC_TXD2 IO GPIOE9 GMAC_TXD2 - - GMAC PB4 GMAC_MDC GMAC_MDC IO GPIOE20 GMAC_MDC - - GMAC PB5 GMAC_RXCLK GMAC_RXCLK IO GPIOE18 GMAC_RXCLK SPIRXD1 - GMAC PB6 GMAC_RXD3 GMAC_RXD3 IO GPIOE17 GMAC_RXD3 - - GMAC PB7 GMAC_RXD1 GMAC_RXD1 IO GPIOE15 GMAC_RXD1 SPIFRM1 - GMAC PB8 GMAC_MDIO GMAC_MDIO IO GPIOE21 GMAC_MDIO - - GMAC PB39 AP_GPA4 DISD3 IO GPIOA4 DISD3 - - GPIO PB40 AP_GPA5 DISD4 IO GPIOA5 DISD4 - - GPIO PB41 AP_GPA16 DISD15 IO GPIOA16 DISD15 - - GPIO PB42 AP_GPA11 DISD10 IO GPIOA11 DISD10 - - GPIO 34 GPIO Alternate Functions SOUTH PART Ball Loc Ball Name Default Function PAK1 AP_I2S0_DOUT I2SDOUT0 PAK2 AP_I2S0_BCLK I2SBCLK0 PAK3 AP_GPC11_SPI2_MISO PAK4 PAK5 I/O Function 0 Function 1 Function 2 Function 3 Group IO GPIOD9 I2SDOUT0 AC97_DOUT - I2S0 IO GPIOD10 I2SBCLK0 AC97_BCLK - I2S0 GPIOC11 SPIRXD2 USB2.0OTG_DrvV BUS SPI2 SA11 IO SA11 AP_GPC9_SPI2_CLK SA9 IO SA9 GPIOC9 SPICLK2 - SPI2 AP_SPI0_MISO SPIRXD0 IO GPIOD0 SPIRXD0 PWM3 - SPI0 PAK6 AP_SPI0_CLK SPICLK0 IO GPIOC29 SPICLK0 - - SPI0 PAK7 AP_GPC14_PWM2 SA14 IO SA14 GPIOC14 PWM2 VICLK2 PWM PAK8 AP_GPD6_SCL2 SCL2 IO GPIOD6 SCL2 - - I2C PAK9 AP_GPD4_SCL1 SCL1 IO GPIOD4 SCL1 - - I2C PAK10 AP_GPD2_SCL0 SCL0 IO GPIOD2 SCL0 ISO7816 - I2C PAK11 AP_GPA23_HDMI_I2C_SCL DISD22 IO GPIOA23 DISD22 - - I2C PAK19 AP_NBATTF VID0_0 IO GPIOD28 VID0_0 TSIDATA1_0 SA24 MISC PAK20 AP_GPE2 VID0_6 IO GPIOE2 VID0_6 TSIDATA1_6 - MISC PAK21 AP_GPE1 VID0_5 IO GPIOE1 VID0_5 TSIDATA1_5 - MISC PAK22 AP_UART_TX3 UARTTXD3 IO GPIOD21 UARTTXD3 SDnCD1 - UART PAK23 AP_UART_TX4 SD13 IO SD13 GPIOB29 TSIDATA0_5 UARTTXD4 UART PAK24 AP_UART_TX0 UARTTXD0 IO GPIOD18 UARTTXD0 ISO7816 SDWP2 UART PAK25 AP_GPB0_VID1_1_I2SLRCK1 VID1_1 IO GPIOB0 VID1_1 SDEX1 I2SLRCLK1 I2S1 PAK26 AP_GPA28_I2SMCLK1 VICLK1 IO GPIOA28 VICLK1 I2SMCLK2 I2SMCLK1 I2S1 PAK27 AP_GPA30_VID1_0_I2SBCLK1 VID1_0 IO GPIOA30 VID1_0 SDEX0 I2SBCLK1 I2S1 PAK28 AP_SD0_CMD SDCMD0 IO GPIOA31 SDCMD0 - - SD/MMC PAK29 AP_SD0_D1 SDDAT0_1 IO GPIOB3 SDDAT0_1 - - SD/MMC PAK30 AP_SD0_CLK SDCLK0 IO GPIOA29 SDCLK0 - - SD/MMC PAK32 AP_GPB13_SD0_BOOT SD0 IO SD0 GPIOB13 - - BOOTING PAK33 AP_GPC17 SA17 IO SA17 GPIOC17 TSIDP0 VID2_0 GPIO PAK34 AP_GPC0 SA0 IO SA0 GPIOC0 TSERR0 - GPIO PAK35 AP_GPC26 RDNWR IO RDNWR GPIOC26 - - GPIO PAK36 AP_GPB8 VID1_5 IO GPIOB8 VID1_5 SDEX5 I2SDOUT2 GPIO PAK37 AP_GPB14 RNB0 IO RnB0 RnB1 GPIOB14 - MISC PAK38 AP_GPA20 DISD19 IO GPIOA20 DISD19 - - GPIO PAK39 AP_GPA18 DISD17 IO GPIOA18 DISD17 - - GPIO PAK40 AP_GPA21 DISD20 IO GPIOA21 DISD20 - - GPIO PAK41 AP_GPA10 DISD9 IO GPIOA10 DISD9 - - GPIO PAK42 AP_GPA6 DISD5 IO GPIOA6 DISD5 - - GPIO PAL1 AP_I2S0_DIN I2SDIN0 IO GPIOD11 I2SDIN0 AC97_DIN - I2S0 PAL2 AP_I2S0_MCLK I2SMCLK0 IO GPIOD13 I2SMCLK0 AC97_nRST - I2S0 PAL3 AP_GPC12_SPI2_MOSI SA12 IO SA12 GPIOC12 SPITXD2 SDnRST2 SPI2 PAL4 AP_GPC10_SPI2_CS SA10 IO SA10 GPIOC10 SPIFRM2 - SPI2 PAL5 AP_SPI0_MOSI SPITXD0 IO GPIOC31 SPITXD0 - - SPI0 PAL6 AP_SPI0_CS SPIFRM0 IO GPIOC30 SPIFRM0 - - SPI0 PAL7 AP_GPD1_PWM0 PWM0 IO GPIOD1 PWM0 SA25 - PWM PAL8 AP_GPD7_SDA2 SDA2 IO GPIOD7 SDA2 - - I2C PAL9 AP_GPD5_SDA1 SDA1 IO GPIOD5 SDA1 - - I2C PAL10 AP_GPD3_SDA0 SDA0 IO GPIOD3 SDA0 ISO7816 - I2C PAL11 AP_GPA24_HDMI_I2C_SDA DISD23 IO GPIOA24 DISD23 - - I2C PAL15 COMBO_ZIG_UART_RXD NSCS1 IO GPIOC28 NSCS1 UARTnRI1 - 802.15.4 PAL20 AP_GPE3 VID0_7 IO GPIOE3 VID0_7 TSIDATA1_7 - MISC 35 GPIO Alternate Functions SOUTH PART Ball Loc Ball Name Default Function I/O Function 0 Function 1 Function 2 Function 3 Group PAL21 AP_GPE0 VID0_4 IO GPIOE0 VID0_4 TSIDATA1_4 - MISC PAL22 AP_UART_RX3 UARTRXD3 IO GPIOD17 UARTRXD3 - - UART PAL23 AP_UART_RX4 SD12 IO SD12 GPIOB28 TSIDATA0_4 UARTRXD4 UART PAL24 AP_UART_RX0 UARTRXD0 IO GPIOD14 UARTRXD0 ISO7816 - UART PAL25 AP_GPD31 VID0_3 IO GPIOD31 VID0_3 TSIDATA1_3 - MISC PAL26 AP_GPB9_I2SDIN1 VID1_6 IO GPIOB9 VID1_6 SDEX6 I2SDIN1 I2S1 PAL27 AP_GPB6_VID1_4_I2SDOUT1 VID1_4 IO GPIOB6 VID1_4 SDEX4 I2SDOUT1 I2S1 PAL28 AP_SD0_D3 SDDAT0_3 IO GPIOB7 SDDAT0_3 - - SD/MMC PAL29 AP_SD0_D2 SDDAT0_2 IO GPIOB5 SDDAT0_2 - - SD/MMC PAL30 AP_SD0_D0 SDDAT0_0 IO GPIOB1 SDDAT0_0 - - SD/MMC PAL31 AP_GPB4_VID1_3_BOOT VID1_3 IO GPIOB4 VID1_3 SDEX3 I2SLRCLK2 BOOTING PAL32 AP_GPB15_SD1_BOOT SD1 IO SD1 GPIOB15 - - BOOTING PAL33 AP_GPD8 PPM IO GPIOD8 PPM - - GPIO PAL34 AP_GPE30 NSOE IO NSOE GPIOE30 - - GPIO PAL35 AP_GPC27 NSDQM IO NSDQM GPIOC27 - - GPIO PAL36 AP_GPB22 SD6 IO SD6 GPIOB22 - - GPIO PAL37 AP_GPB16 NNFOE0 IO NNFOE0 NNFOE1 GPIOB16 - MISC PAL38 AP_GPB23 SD7 IO SD7 GPIOB23 - - GPIO PAL39 AP_GPA22 DISD21 IO GPIOA22 DISD21 - - GPIO PAL40 AP_GPA19 DISD18 IO GPIOA19 DISD18 - - GPIO PAL41 AP_GPA17 DISD16 IO GPIOA17 DISD16 - - GPIO PAL42 AP_GPA3 DISD2 IO GPIOA3 DISD2 - - GPIO GPIO Alternate Functions EAST PART Ball Name Default Function I/O Function 0 Function 1 Function 2 Function 3 Group PAC1 AP_TCK TCLK IO TCLK GPIOE28 - - JTAG PAC2 AP_TMS TMS IO TMS GPIOE26 - - JTAG PAD1 AP_TDO TDO IO TDO GPIOE29 - - JTAG Ball Loc PAD2 AP_TDI TDI IO TDI GPIOE27 - - JTAG PAE1 AP_NTRST NTRST IO NTRST GPIOE25 - - JTAG PAG2 AP_GPA25_BACKKEY DISVSYNC IO GPIOA25 DISVSYNC - - KEY PAH1 AP_GPA26_VOLUP DISHSYNC IO GPIOA26 DISHSYNC - - KEY PAH2 AP_GPA0_MENUKEY DISCLK IO GPIOA0 DISCLK - - KEY PAJ1 AP_I2S0_LRCLK I2SLRCLK0 IO GPIOD12 I2SLRCLK0 AC97_SYNC - I2S0 PAJ2 AP_GPA27_VOLDOWN DISDE IO GPIOA27 DISDE - - KEY GPIO Alternate Functions WEST PART Ball Loc Ball Name Default Function I/O Function 0 Function 1 Function 2 Function 3 Group PP41 MICOM_INT SD14 IO SD14 GPIOB30 TSIDATA0_6 - MISC PAG41 AP_GPB11 CLE0 IO CLE0 CLE1 GPIOB11 - GPIO PAG42 AP_GPB18 NNFWE0 IO NNFWE0 nNFWE1 GPIOB18 - GPIO PAH41 AP_GPC25 NSWAIT IO NSWAIT GPIOC25 SPDIFTX - GPIO PAH42 AP_GPE31 NSWE IO NSWE GPIOE31 - - GPIO 36 The ARTIK 530 Module supports a variety of booting scenarios as depicted in Table 33. Table 34 describes the values of the PAD signals needed to initiate the various booting scenarios. When nothing is done default booting will take place. (AP_GPB13_SD0_BOOT is High, AP_GPB15_SD1_BOOT is Low and AP_GPB4_VID1_3_BOOT is High) In this case the ARTIK 530 Module will try to boot from eMMc, if this fails it will continue to initiate a boot from SD0 and if this fails it will continue booting from the USB device. The other booting options perform in a similar manner. Changing the PAD signals according to the values in Table 34 will allow for different booting options to be executed. Booting Scenario Primary Booting Device Secondary Booting Device Tertiary Booting Device 1 Boot from eMMc Boot from SD0 Boot from USB device 2 – Boot from SD0 Boot from USB device 3 – – Boot from USB device Signal Name Booting Scenario 1 (default) Booting Scenario 2 Booting Scenario 3 AP_GPB13_SD0_BOOT High High Low AP_GPB15_SD1_BOOT Low Low High AP_GPB4_VID1_3_BOOT High Low X 37 Figure 3 shows the Power Management state diagram. In this diagram the entry and WAKEUP conditions for each power down mode are given. POWER ON RESET AP_nBATTF 1 AP_nBATTF HOLD 600µs STABLE PLL0 & PLL1 CPU REQUEST IDLE 1 1 600µs NORMAL WAKEUP CPU REQUEST STABLE PLL0 & PLL1 STOP STABLE X-TAL WAKEUP AP_nBATTF 60ms The following Modes of operation can be distinguished:  NORMAL Mode  Everything is running, this is the normal mode of operation when applications are executed on the ARM cores  IDLE Mode  CPU clocks are turned off  IDLE state can be initiated by CPU using Software API  The following WAKEUP sources can be used to return to NORMAL Mode:  GPIO Interrupt, RTC Interrupt, AliveGPIO Interrupt (see PAE2, PAF:[1,2]), External IRQ  STOP Mode  PLL’s are turned off, DRAM goes into self-refresh  STOP state can be initiated by CPU using Software API  Certain WAKEUP sources or the ARTIK 530 Module AP_nBATTF signal can be used to transition to NORMAL Mode  The following WAKEUP sources can be used to return to NORMAL Mode:  RTC Interrupt, AliveGPIO Interrupt For more information on how to access discussed WAKEUP mechanisms like AliveGPIO interrupts, GPIO Interrupts, RTC Interrupts and External Interrupts, please refer to the Software User Guide. 38 Two antennas are required to use the full set of radio communication links on the ARTIK 530 Module. One supports the ® ® combination of Wi-Fi /Bluetooth , and the other is dedicated to 802.15.4. Caution: Do not apply power (enable) the radio chips before connecting antennas or damage to the chip may result. All Dimensions are in mm ® ® The U.FL-R-SMT Hirose connector is used for both the Bluetooth /Wi-Fi and the 802.15.4 (ZigBee/Thread) antenna connectors on the ARTIK 530 Module. The mechanical size of the connector (receptacle) is described in Figure 4. For suggestions on mating plug and more details on the connector, please contact Hirose Electric Co., LTD. 39 The ratings given in this section are associated only with stress. It does not imply any functional operation of the device. Exposure to the absolute-maximum rated conditions for long duration affects the reliability of the device. Absolute Maximum Ratings Parameter Symbol Condition Min Max Main battery supply VBAT_MAIN – -0.3 6.0 3.3V Buffer -0.5 3.8 5V Tolerant buffer -0.3 5.3 PAK:[15] PAL:[15] Non 5V Tolerant Buffer -0.3 3.6 PAL:[19] PAF:[1] PAG:[1] – -0.3 3.8 PAL:[14] Voltage at Pin -0.5 3.8 V – -20 20 mA – -50 50 mA PA:[1,2,3,5,6,7,8,29,37,39,40,41,42] PB:[2,3,4,5,6,7,8,39,40,41,42] PAK:[1,2,3,4,5,6,7,8,9,10,11,19,20,21,22,23,24,25,26,27,28,29,30,32,3 3,34,35,36,37,38,39,40,41,42] PAL:[1,2,3,4,5,6,7,8,9,10,11,20,21,22,23,24,25,26,27,28,29,30,31,32,3 3,34,35,36,37,38,39,40,41,42] PP:[41] PAC:[1,2] PAD:[1,2] PAE:[1] DC input/output voltage PAG:[2,41,42] PAH:[1,2,41,42] PAJ:[1,2] PAK:[12,13,14] PAL:[12,13] PA:[1,2,3,5,6,7,8,29,37,39,40,41,42] PB:[2,3,4,5,6,7,8,39,40,41,42] PAK:[1,2,3,4,5,6,7,8,9,10,11,19,20,21,22,23,24,25,26,27,28,29,30,32,3 3,34,35,36,37,38,39,40,41,42] PAL:[1,2,3,4,5,6,7,8,9,10,11,20,21,22,23,24,25,26,27,28,29,30,31,32,3 3,34,35,36,37,38,39,40,41,42] PP:[41] PAC:[1,2] DC Input/output current PAD:[1,2] PAE:[1] PAG:[2,41,42] PAH:[1,2,41,42] PAJ:[1,2] PAK:[12,13,14,15] PAL:[12,13] PAL:[14] Storage Temperature TA Units V Current at Pin -1 1 mA – -40 85 °C 40 The recommended operation of the ARTIK 530 Module is based on the operating conditions listed in Table 36. Table 36. Recommended Operating Conditions Parameter Symbol Min Typ Max Units Main Battery Supply VBAT_MAIN PV:[41,42],PW:[41,42],PY:[41,42],PAA:[4 1,42],PAB:[41,42] 3.7 4.20 5.0 V Operating Temperature TO -25 – 85 °C 41 The power management of the ARTIK 530 Module as described in Figure 5 is controlled by a PMIC. This PMIC contains four high efficiency DC-DC converters and five LDO regulators. See Table 37 and Table 38 for details on voltage and amperage ranges and how they are used in the ARTIK 530 Module. Buck Powers Header Max Current [mA] Range [V] Default [V] DCDC1 ARM of Main SoC – 3000 0.60-3.50 DCDC2 Core of Main SoC – 3000 0.60-3.50 1.0 DCDC3 DDR3 IO Memory – 2000 0.60-3.50 1.50 DCDC4 DDR3 Core Memory – 2000 0.60-3.50 1.50 1.0 42 LDO Powers Header Current [mA] Range [V] Step [mV] Default [V] LDO1 Main SoC :[IO,USB,USBHOST,VIDEO,GMAC] – 300 0.90-3.50 50 – LDO2 Wi-Fi®/Bluetooth®, Main SoC:[ADC,PLL] – 300 0.90-3.50 50 – LDO3 FLASH, Wi-Fi®/Bluetooth®, 802.15.4, Main SoC:[USB OTG] PAK:[17,18],PAL:[17,18] 300 0.90-3.50 50 3.30 LDO4 Main SoC:[HSIC] – 200 0.90-3.50 50 1.20 LDO5 Not Used – – – – – PAK:[17,18],PAL:[17,18] Operating Conditions VIN=3.6V, COUT=1µF, TA=25°C unless otherwise specified Symbol Parameter Condition Min Typ Max Unit VIN Input Voltage Range – 1.70 3.60 5.5 V Output Voltage Range 50µA < IOUT < IOUTMAX 0.60 – 3.50 V mV VOUT Voltage Setting Step Width – – 50 – VACCU Output Voltage Accuracy VOUT = All Output Range, IOUT=1mA -1.50 – 1.50 % IOUTMAX Output Current – – – 300 mA mA ILIM Limit Current – 350 – – VDIFF Dropout Voltage VOUT Setting=VIN, IOUT=IOUTMAX – – 0.30 V VLINE Line Regulation 2.7 < VIN 0.6V – 60 – dB ONOISE Output Noise IOUT=IOUTMAX/2, BW=10Hz-100kHz, VOUT=1.2V – 60 – uVrms ISS Supply Current IOUT=0mA – 20 – µA IOFF Standby Current IOUT=0mA – – 1 µA TR Rising Time VOUTx0.9, IOUT=0mA – – 500 µs TF Falling Time VOUTx0.1, IOUT=0mA – – 500 µs COUT Output Capacitor – 1.0 – µF 43 Symbol Min. Max. Units ESD stress voltage Human Body Model – TBD kV ESD stress voltage Charged Device Model – TBD V Shock and Vibration Range Shock Vibration Operating TBD Non Operating TBD Operating TBD Non Operating TBD 44 The DC characteristics for the GPIO pins of the ARTIK 530 Module are listed in Table 42. Use the parameters from Table 42 to determine maximum DC loading and to determine maximum transition times for a given load. VDD = 3.3V, Vext = 3.0 to 3.6 V, TJ = -25 to 85 °C (TJ = Junction Temperature), 3.30V Tolerant GPIO BALL Coordinates Parameter VTOL PA:[1,2,3,5,6,7,8,29,37,39 ,40,41,42] PB:[2,3,4,5,6,7,8,39,40,41 ,42] PAK:[1,2,3,4,5,6,7,8,9,10, 11,19,20,21,22,23,24,25, 26,27,28,29,30,32,33,34, 35,36,37,38,39,40,41,42] PAL:[1,2,3,4,5,6,7,8,9,10, 11,20,21,22,23,24,25,26, 27,28,29,30,31,32,33,34, 35,36,37,38,39,40,41,42] PP:[41] PAC:[1,2] PAD:[1,2] PAE:[1] PAG:[2,41,42] PAH:[1,2,41,42] PAJ:[1,2] 802.15.4 BALL Coordinates VIH VIL V Tolerant external voltage Condition Min Typ Max Units VDD Power Off & On – – 3.60 V – 2.31 – 3.60 V 0.70 V High Level Input Voltage CMOS Interface Low Level Input Voltage CMOS Interface VDD = 3.3V ± 10 % -0.3 – Hysteresis Voltage – 0.15 – -3 – V High Level Input Current IIH Input Buffer VIN = VDD Input Buffer with pull-down VIN = VDD VDD Power On 3 VDD Power Off & SNS = 0 -5 – 5 VDD = 3.3V ± 10 % 15 40 80 µA Low Level Input Current IIL Input Buffer VIN = VSS VDD Power On & Off -3 – 3 Input Buffer with pull-up VIN = VSS VDD = 3.3V ± 10 % -15 -40 -110 VOH Output High Voltage IOH = -1.8mA, -3.6mA, -7.2mA, -10.8mA 2.64 – 3.30 VOL Output Low Voltage IOH = -1.8mA, -3.6mA, -7.2mA, -10.8mA 0 – 0.66 µA V IOZ Output Hi-Z current – -5 – 5 µA CIN Input capacitance Any input and bi-directional buffers – – 5 pF COUT Ouput capacitance Any output buffer – – 5 pF Symbol Description VIL VIL input logic level low VDD=3.3V VIH VIH input logic level high VDD=3.3V Condition Min Typ Max Units – – 0.70 V 2.31 – – V Output Voltage Levels PAK:[12,13,14,15] PAL:[12,13,15] PAL:[14] VOL[3mA] VOL output logic level low VDD=3.3V, IOL=3ma, weak driver – – 0.66 V VOH[-3mA] VOH output logic level high VDD=3.3V, IOH=-3ma, weak driver 2.64 – – V VOH[20mA] VOH output logic level high VDD=3.3V, IOL=20ma, strong driver – – 0.66 V VOH[-20mA] VOH output logic level high VDD=3.3V, IOL=-20ma, strong driver 2.64 – – V µA IQ Quiescent Current Static Inputs and Outputs – 1.00 – VO Maximal voltage applied to PIN in High-Impedance State – – – 3.30 VIH High Level Input Voltage Logic input at VDD=3.3V 1.84 – 3.30 VIL Low Level Input Voltage Logic input at VDD=3.3V – – 1.255 IIH High Level Input Current Logic input VIN=VDD=3.3V -1.00 – 1.00 IIL Low Level Input Current Logic input VIN=0V -1.00 – 1.00 VOH High Level Output Voltage Push-Pull & PMOS OD, IOL=3mA, 1x Driver at VDD=3.3V 2.721 3.108 – VOL Low Level Output Voltage Push-Pull, IOL=3mA, 1x Driver at VDD=3.3V 0.175 0.257 V µA V 45 802.15.4 BALL Coordinates Symbol Description Condition Min Typ Max IOH High Level Output Current Push-Pull & PMOS OD, VOH=2.4V, 1x Driver at VDD=3.3V 5.774 11.066 – IOL Low Level Output Current Push-Pull, VOL=0.4V, 1x Driver at VDD=3.3V 4.491 6.438 – PMIC BALL Coordinates PAG:[1] PAF:[1],PAL:[19] Parameter Symbol Open drain, IOUT=2mA VOL Open drain, IOUT=2mA VOH Input only : Low level input voltage VIL Input only : High level input voltage VIH Wi-Fi®/Bluetooth® BALL Coordinates PAJ:[39,40,41,42] Test Condition Parameter Symbol Condition High level input voltage VIH Low level input voltage VIL Output High voltage Output Low voltage BALL Coordinates PA:[1,2,3,5,6,7,8,29,37,39,40,41,42] PB:[2,3,4,5,6,7,8,39,40,41,42] PAK:[1,2,3,4,5,6,7,8,9,10,11,19,20,21,22,23,24,25,26,27,28,29, 30,32,33,34,35,36,37,38,39,40,41,42] PAL:[1,2,3,4,5,6,7,8,9,10,11,20,21,22,23,24,25,26,27,28,29,30, 31,32,33,34,35,36,37,38,39,40,41,42] PP:[41] PAC:[1,2] PAD:[1,2] PAE:[1] PAG:[2,41,42] PAH:[1,2,41,42] PAJ:[1,2] mA Min Typ Max Units – – 0.40 V – – VBAT_MAIN V – – 0.40 V 1.40 – VBAT_MAIN V – – Units Min Typ Max – 2.31 – 3.70 – -0.40 – 0.99 VOH – 2.90 – – VOL – – – 0.40 Condition Every GPIO has a 100kΩ internal pull-up resistor Unit V V Pull Up Min Typ Max Unit Enable 10 33 72 µA Disable – – 0.1 µA *Based on 100kΩ internal pull-up resistor Symbol Parameter Min. Typ. Max. Unit tRESW Reset assert time after clock stabilization TBD – – ns 46 AC characteristics covered in this section are preliminary and are likely to change. HS_SDCLK tHSDCD HS_SDCMD (out) tHSDCS tHSDCH HS_SDCMD (in) tHSDDD HS_SDDATA[7:0] (out) tHSDDS tHSDDH HS_SDDATA[7:0] (in) (VDDINT = 1.0V  5%, TJ = -25 to 85C, VDDmmc = 3.3V  5 %, 2.5V  5%, 1.8V  5%) BOT:[59,60,61,62,63,64] Symbol Parameter Min Typ Max tSDCD SD command output delay time – – 4.0 tSDCS SD command input setup time 4.0 – – tSDCH SD command input hold time 0 – – tSDDD SD data output delay time – – 4.0 tSDDS SD data input setup time 4.0 – – tSDDH SD data input hold time 0 – – Unit ns 47 SPICLK XspiMOSI (MO) tSPIMIH tSPIMOD XspiMISO (MI) tSPIMIS XspiMISO (SO) tSPISOD tSPISIH XspiMOSI (SI) tSPISIS XspiCS tSPICSSD tSPICSSS 48 (VDDINT = 1.0 V  5 %, TJ = -25 to 85 C, VDDext = 1.8 V  10 %, load = 15 pF) Parameter SPI MOSI Master Output Delay time Symbol – – 5 – – SPI MISO Master Input Setup time (FB_CLK_SEL = 01) 7 – – 2 – – -3 – – tSPIMIS SPI MISO Master Input Hold time tSPIMIH 5 – – SPI MOSI Slave Input Setup time tSPISIS 2 – – SPI MOSI Slave Input Hold time tSPISIH 5 – – SPI MISO Slave Output Delay time tSPISOD – – 17 SPI nSS Master Output Delay time tSPICSSD 7 – – SPI nSS Slave Input Setup time tSPICSSS 5 – – SPI MOSI Master Output Delay time tSPIMOD – – 4 SPI MISO Master Input Setup time (FB_CLK_SEL = 00) 13 – – SPI MISO Master Input Setup time (FB_CLK_SEL = 01) 8 – – 3 – – -2 – – SPI MISO Master Input Setup time (FB_CLK_SEL = 10) Ch 1 Max. 12 SPI MISO Master Input Setup time (FB_CLK_SEL = 11) Ch 0 Typ. SPI MISO Master Input Setup time (FB_CLK_SEL = 00) SPI MISO Master Input Setup time (FB_CLK_SEL = 10) tSPIMOD Min. tSPIMIS SPI MISO Master Input Setup time (FB_CLK_SEL = 11) SPI MISO Master Input Hold time tSPIMIH 5 – – SPI MOSI Slave Input Setup time tSPISIS 3 – – SPI MOSI Slave Input Hold time tSPISIH 5 – – SPI MISO Slave Output Delay time tSPISOD – – 18 SPI nSS Master Output Delay time tSPICSSD 7 – – SPI nSS Slave Input Setup time tSPICSSS 5 – – Unit ns ns ns ns Note: SPICLKout = 50 MHz  tSPIMIS,CH0 = 12 – (cycle period/4) x FB_CLK_SEL  tSPIMIS,CH1 = 13 – (cycle period/4) x FB_CLK_SEL 49 (VDDINT = 1.0 V  5 %, TJ = –25 to 85C, VDDext = 3.3 V  10 %, load = 30 pF) Parameter SPI MOSI Master Output Delay time Symbol – – 6 – – SPI MISO Master Input Setup time (FB_CLK_SEL = 01) 8 – – 3 – – -2 – – tSPIMIS SPI MISO Master Input Hold time tSPIMIH 5 – – SPI MOSI Slave Input Setup time tSPISIS 4 – – SPI MOSI Slave Input Hold time tSPISIH 5 – – SPI MISO Slave Output Delay time tSPISOD – – 18 SPI nSS Master Output Delay time tSPICSSD 8 – – SPI nSS Slave Input Setup time tSPICSSS 6 – – SPI MOSI Master Output Delay time tSPIMOD – – 5 SPI MISO Master Input Setup time (FB_CLK_SEL = 00) 14 – – SPI MISO Master Input Setup time (FB_CLK_SEL = 01) 9 – – 4 – – -1 – – SPI MISO Master Input Setup time (FB_CLK_SEL = 10) tSPIMIS SPI MISO Master Input Setup time (FB_CLK_SEL = 11) Ch 1 Max. 13 SPI MISO Master Input Setup time (FB_CLK_SEL = 11) Ch 0 Typ. SPI MISO Master Input Setup time (FB_CLK_SEL = 00) SPI MISO Master Input Setup time (FB_CLK_SEL = 10) tSPIMOD Min. SPI MISO Master Input Hold time tSPIMIH 5 – – SPI MOSI Slave Input Setup time tSPISIS 4 – – SPI MOSI Slave Input Hold time tSPISIH 5 – – SPI MISO Slave Output Delay time tSPISOD – – 19 SPI nSS Master Output Delay time tSPICSSD 8 – – SPI nSS Slave Input Setup time tSPICSSS 6 – – Unit ns ns ns ns Note: SPICLKout = 50 MHz  tSPIMIS,CH0 = 12 – (cycle period/4) x FB_CLK_SEL  tSPIMIS,CH1 = 13 – (cycle period/4) x FB_CLK_SEL 50 FSCL TSCLHIGH TSCLLOW IICSCL TSTOPH TBUF TSDAS TSDAH TSTARTS IICSDA 2 I C BUS Controller Module Signal Timing (VDDINT, VDDarm = 1.1 V ± 5 %, TJ = -25 to 85°C, VDDext = 3.3 V ± 10 %) Parameter Symbol SCL clock frequency SCL high level pulse width SCL low level pulse width Bus free time between STOP and START START hold time SDA hold time SDA setup time STOP setup time Min. Typ. Max. Unit kHz FSCL – – std. 100 fast 400 TSCLHIGH std. 4.0 fast 0.6 – – TSCLLOW std. 4.7 fast 1.3 – – TBUF std 4.7 fast 1.3 – – TSTARTS std. 4.0 fast 0.6 – – TSDAH std. 0 fast 0 – std. fast 0.9 TSDAS std. 250 fast 100 – – ns TSTOPH std. 4.0 fast 0.6 – – s s Note: std. refers to Standard Mode and fast refers to Fast Mode. 2 1. The I C data hold time (tSDAH) is minimum 0ns. 2 2 (I C data hold time is minimum 0ns for standard/fast bus mode I C specification v2.1) 2 Check whether the data hold time of your I C device is 0 ns or not. 2. The I C controller supports I C bus device only (standard/fast bus mode), and does not support C bus device. 2 2 51 ® ® All performance numbers related to Wi-Fi /Bluetooth and 802.15.4 mentioned in this section are preliminary and likely to change once module characterization has taken place. Parameter Frequency Range Conditions – Min Typ. Max Unit 2400 – 2500 MHz Minimum receiver sensitivity in 802.11b mode (2.4GHz) 1Mbps 2Mbps 5.5Mbps PER < 8%, Packet size = 1024 bytes 11Mbps – -97 – dBm – -95 – dBm – -94 – dBm – -90 – dBm Minimum receiver sensitivity in 802.11g mode (2.4GHz) 6Mbps – -91 – dBm 9Mbps – -90 – dBm 12Mbps – -89 – dBm – -87 – dBm – -84 – dBm 36Mbps – -81 – dBm 48Mbps – -76 – dBm 54Mbps – -75 – dBm 18Mbps 24Mbps PER < 10%, Packet size= 1024 bytes Minimum receiver sensitivity in 802.11n mode (2.4GHz) MCS 0 – -89 – dBm MCS 1 – -88 – dBm – -86 – dBm – -83 – dBm – -79 – dBm – -75 – dBm MCS 6 – -73 – dBm MCS 7 – -72 – dBm MCS 2 MCS 3 MCS 4 MCS 5 PER