SSC1S312A

Quasi-Resonant Off-Line Switching Control ICs SSC1S310A Series Data Sheet C5 Description D1 L1 D4 T1 VOUT VAC SSC1S310A series is the controller ICs of a quasiresonant mode for a switching power supplies. The IC incorporates a startup circuit and a standby function to reduce a power consumption and standby power. In normal operation, the quasi-resonant mode operation achieves high efficiency and low noise. In addition, in medium to low load conditions, the operation mode is automatically changes the quasi-resonant mode to the bottom-skip mode to improve efficiency. The IC is provided in the SOIC8 package. The power supply that is a low component counts and a high performance-tocost can be achieved by the rich set of protection features. Features ● Multi-Mode Control (High efficiency operation in all range of loads) ● Automatic Standby Function (Standby power is inproved by burst oscillation mode) ● Input Power at No Load: VBD(TH2) SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 3 SSC1S310A Series Parameter Symbol Conditions Pins Min. Typ. Max. Unit Quasi-Resonant Operation Threshold Voltage 2(2) VBD(TH2) 2−8 0.07 0.17 0.27 V Maximum Feedback Current IFB(MAX) 1−8 −320 −205 −120 μA VFB(STBOP) 1−8 0.45 0.80 1.15 V tON(MAX) 5−8 30.0 40.0 50.0 µs tBW 5−8 ― 495 ― ns VOCP(H) 6−8 0.820 0.910 1.000 V Standby Operation Standby Operation Threshold Voltage Protection Operation Maximum On-time Leading Edge Blanking Time Overcurrent Detection Threshold Voltage (Normal Operation) Overcurrent Detection Threshold Voltage (Input Compensation in Operation) VOCP(L) VBD = −3 V 6−8 0.560 0.660 0.760 V IBD(O) VBD = −3 V 2−8 −250 −83 −30 μA OLP Bias Current IFB(OLP) VFB/OLP = 5V 1−8 −15 −10 −5 μA OLP Threshold Voltage VFB(OLP) 1−8 5.50 5.96 6.40 V Circuit Current after OLP ICC(OLP) 7−8 ― 575 ― μA VCC Pin OVP Threshold Voltage VCC(OVP) 7−8 28.5 31.5 34.0 V FB Pin Maximum Voltage in Feedback Operation VFB(MAX) 1−8 3.70 4.05 4.40 V Tj(TSD) ― 135 ― ― °C VDRV 5−8 7.5 8.1 8.7 V DRV Pin Source Current (Peak) IDRV(SO) 5−8 ― −150 ― mA DRV Pin Sink Current (Peak) IDRV(SI) 5−8 ― 608 ― mA θj-A ― ― ― 180 °C /W BD Pin Current Thermal Shutdown Temperature IFB = −12 µA Drive Circuit DRV Pin Output Voltage Thermal Characteristics Thermal Resistance SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 4 SSC1S310A Series 3. Block Diagram VCC 7 Startup 3 1 DRV UVLO 2 4 ST 5 DRV Reg/Iconst OCP/BS 2 6 OCP Logic FB/STB OLP OSC GND 8 4. BD 4 5 6 1 FB/OLP 2 BD Pin Configuration Definitions Number Name 1 FB/OLP 2 BD OCP 3 ― Function Constant voltage control, standby control, and Overload detection signal input Bottom detection and input compensation signal input (Pin removed) DRV 4 ST Startup current input 5 DRV Gate drive output 6 OCP 7 VCC 8 GND Overcurrent detection signal input Supply voltage input and overvoltage detection signal input Ground FB/OLP 1 8 GND BD 2 7 VCC 3 6 4 5 ST SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 5 SSC1S310A Series 5. Typical Applications The startup voltage of Figure 5-1 is about 21 V which is Startup Circuit Operation Voltage, VSTART(ON). When the startup voltage increases more than this, Figure 5-2 is available, adding DZST in series with the ST pin. The startup voltage after adding DZST, VSTART(ON)’ is calculated as follows: VSTART(ON) ′ = VSTART(ON) + VZST (1) where: VSTART(ON) is the Startup Circuit Operation Voltage, about 21 V, and VZST is the zener voltage of DZST. C5 D1 L1 D4 T1 VOUT VAC P R9 C1 R7 S RST R4 R3 D2 GND VCC R8 U2 C9 7 C8 C7 R12 8 R10 C6 R5 D3 Q1 CV R6 PC1 6 OCP D C2 DRV R11 R2 5 GND U1 SSC1S310A FB/OLP BD ST 2 1 DZBD RBD1 4 ROCP R1 CBD C3 C4 RBD2 PC1 Figure 5-1. Application Circuit Example 1 C5 D1 L1 D4 T1 VOUT VAC P R9 DZST C1 PC1 S RST R4 R3 U2 C9 D2 7 GND VCC R7 C7 R12 8 R10 C6 R5 D3 Q1 CV 6 OCP R2 5 DRV R6 C8 R8 R11 D C2 GND U1 SSC1S310A FB/OLP BD 1 DZBD ST 2 RBD1 4 ROCP R1 CBD C4 Figure 5-2. C3 RBD2 PC1 Application Circuit Example 2 (Adjustable Startup Voltage) SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 6 SSC1S310A Series 6. Physical Dimensions NOTES: - Dimensions in millimeters - Pb-free 7. Marking Diagram 8 SC1S31x SKYMD A 1 Part Number Lot Number: Y is the last digit of the year of manufacture (0 to 9) M is the month of the year (1 to 9, O, N, or D) D is the period of days represented by: 1: the first 10 days of the month (1st to 10th) 2: the second 10 days of the month (11th to 20th) 3: the last 10–11 days of the month (21st to 31st) Control Number SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 7 SSC1S310A Series Operational Description All the characteristic values given in this section are typical values, unless they are specified as minimum or maximum. Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming out of the IC (sourcing) is negative current (−). Startup Operation VCC(BIAS) (max. ) < VCC < VCC(OVP) (min. ) 8.1.1. Startup Period Figure 8-1 shows VCC pin peripheral circuit. The built-in startup circuit is connected to the ST pin, and it generates a constant current, ICC(STARTUP) = –3.1 mA, to charge capacitor C2 connected to the VCC pin. During this process, when the VCC pin voltage reaches VCC(ON) = 15.1 V, the control circuit starts operation. After that, the startup circuit stops automatically, in order to eliminate its own power consumption. The approximate startup time, tSTART, is calculated as follows: t START = C2 × VCC(ON) − VCC(INT) →12.5 V < VCC < 28.5𝑉 (3) Circuit current, ICC Start 8.1. ICC, increases. In operation, when the VCC pin voltage decreases to VCC(OFF) = 9.4 V, the control circuit stops operation, by the UVLO (Undervoltage Lockout) circuit, and reverts to the state before startup. The voltage rectified the auxiliary winding voltage, VD, in Figure 8-1 becomes a power source to the control circuit after the operation start. The VCC pin voltage should become as follows within the specification of input voltage range and the output load range of power supply, taking account of the winding turns of the D winging. The target voltage of the VCC pin voltage is about 20 V. Stop 8. (2) |ICC(STARTUP) | VCC pin voltage VCC（OFF） where: tSTART is the startup time in s, and VCC(INT) is the initial voltage of the VCC pin in V. D1 Figure 8-2. VCC（ON） VCC vs. ICC T1 8.1.3. Bias Assist Function VAC C1 P RST 4 ST VCC 7 D2 R2 U1 C2 GND Figure 8-1. 8 VD D VCC Pin Periheral Circuit 8.1.2. Undervoltage Lockout (UVLO) Circuit Figure 8-2 shows the relationship of VCC and ICC. When the VCC pin voltage increases to VCC(ON) = 15.1 V, the control circuit starts operation and the circuit current, Figure 8-3 shows the VCC pin voltage behavior during the startup period. When the VCC pin voltage reaches VCC(ON) = 15.1 V, the control circuit starts operation, the circuit current, ICC, increases, and thus the VCC pin voltage begins dropping. At the same time, the auxiliary winding voltage, VD, increases in proportion to the output voltage rise. Thus, the VCC pin voltage is set by the balance between dropping by the increase of ICC and rising by the increase of the auxiliary winding voltage, VD. Just at the turning-off of the power MOSFET, a surge voltage occurs at the output winding. If the feedback control is activated by the surge voltage under light load condition at startup, and the VCC pin voltage decreases to VCC(OFF) = 9.4 V, a startup failure can occur, because the output power is restricted and the output voltage decreases. In order to prevent this, during a state of operating feedback control (that is, the FB/OLP pin voltage is VFB(STBOP) = 0.8 V or less), when the VCC pin voltage falls to the Startup Current Supply Threshold Voltage, VCC(BIAS) = 11.0 V, the bias assist function is activated. While the bias assist function is operating, the SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 8 SSC1S310A Series decrease of the VCC pin voltage is suppressed by providing the startup current, ICC(STARTUP), from the Startup circuit. By the bias assist function, the use of a small value C2 capacitor is allowed, resulting in shortening startup time. Also, because the increase of VCC pin voltage becomes faster when the output runs with excess voltage, the response time of the overvoltage protection can also be shortened. It is required to check and adjust the process so that poor starting conditions may be avoided. VCC pin voltage IC startup Startup success Target operating voltage VCC(ON)= 15.1V VCC(BIAS)= 11.0V D2 R2 7 VCC Added D C2 U1 GND 8 Figure 8-5. VCC pin peripheral circuit with R2 Increasing by output voltage rising Bias Assist period VCC(OFF)= 9.4V Startup failure Time Figure 8-3. VCC during Startup Period 8.1.4. Auxiliary Winding In actual switch-mode power supply (SMPS) circuits, there are cases in which the VCC pin voltage fluctuates in proportion to the output of the SMPS (see Figure 8-4), and the Overvoltage Protection (OVP) on VCC pin may be activated. This happens because C2 is charged to a peak voltage on the auxiliary winding D, which is caused by the transient surge voltage coupled from the primary winding when the power MOSFET turns off. For alleviating C2 peak charging, it is effective to add some value R2, of several tenths of ohms to several ohms, in series with D2 (see Figure 8-5). The optimal value of R2 should be determined using a transformer matching what will be used in the actual application, because the variation of the auxiliary winding voltage is affected by the transformer structural design. VCC pin voltage Without R2 The variation of VCC pin voltage becomes worse if: ● The coupling between the primary and secondary windings of the transformer gets worse and the surge voltage increases (low output voltage, large current load specification, for example). ● The coupling of the auxiliary winding, D, and the secondary side stabilization output winding (winding of the output line which is controlling constant voltage) gets worse and it is subject to surge voltage. In order to reduce the influence of surge voltages on the VCC pin, alternative structures of the auxiliary winding, D, can be used as examples of transformer structural designs see Figure 8-6. ● Winding structural example (a) - Separating the auxiliary winding D from the primary side windings P1 and P2. - The primary side winding is divided into two windings, P1 and P2. ● Winding structural example (b) - Placing the auxiliary winding D within the secondary winding S1 in order to improve the coupling of those windings. - The output winding S1 is a stabilized output winding controlled to constant voltage. With R2 Output current, IOUT Figure 8-4. VCC versus IOUT with/without resistor R2 SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 9 SSC1S310A Series Core Bobbin Core Bobbin Barrier tape Barrier tape P1 S1 P2 S2 D P1 S1 D S2 S1 P2 Barrier tape Barrier tape Pin side Pin side Winding Structure Example (B) Winding Structure Example (a) P1, P2: Primary winding S1: Secondary winding of which the output voltage is controlled constant S2: Secondary winding D: Auxiliary winding for VCC Figure 8-6. Winding Structure Example 8.1.5. Soft-Start Function 8.1.6. Operational Mode at Startup Figure 8-7 shows the behavior of VCC pin voltage and the drain current during the startup period. The IC activates the soft-start function during the startup period. The soft-start operation period, tSS, is internally set to 6.05 ms, and the overcurrent protection (OCP) threshold voltage steps up in four steps during this period. This reduces the voltage and current stress on the power MOSFET and on the secondary-side rectifier. During the soft-start operation period, the operation is in PWM operation with PWM operation frequency of fOSC = 21.0 kHz. In addition, because the soft-start operation period is fixed internally, it is necessary to confirm and adjust the VCC pin voltage and the overload protection (OLP) delay time during startup, based on actual operation in the application. As shown in Figure 8-7 because the auxiliary winding voltage is low at startup, there is a certain period when the quasi-resonant signal has not yet reached a regulated level (Quasi-Resonant Operation Threshold Voltage 1, VBD(TH1), is 0.24 V or more, and the effective pulse width for the quasi-resonant signal is 1.0μs or more). During this period, the operation is in PWM operation with PWM operation frequency of fOSC = 21.0 kHz. Then, when the output voltage rises, the auxiliary winding voltage will rise, and when a quasi-resonant signal reaches the regulated level, quasi-resonant operation will begin. In addition, during the soft-start operation period, tSS, the operation is in PWM operation, even if the quasiresonant signal reaches the regulated level. VCC pin voltage Startup Steady operation VCC(ON) VCC(OFF) BD pin voltage Time A PWM operation Quasi-resonant operation VBD(TH1) Time Drain current, ID Pulse width 1.0µs(MIN) BD pin waveform expanded at point A Time Soft-Start Operation Period, tSS=6.05ms Operation mode Quasi-resonant operation PWM operation （fOSC=21.0kHz） Figure 8-7. Operational Mode in Startup SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 10 SSC1S310A Series 8.2. Constant Voltage Control Operation The constant output voltage control function uses the current mode control (peak current mode), which enhances response speed and provides stable operation. This IC compares the voltage, VROCP, of a current detection resistor with the target voltage, VSC, by the internal FB comparator, and controls the peak value of VROCP so that it gets close to VSC. VSC is internally generated from the FB/OLP pin voltage (see Figure 8-8 and Figure 8-9). ● Light Load Conditions When load conditions become lighter, the output voltage, VOUT, rises, and the feedback current from the error amplifier on the secondary side also increases. The feedback current is sunk at the FB/OLP pin, transferred through a photo-coupler, PC1, and the FB/OLP pin voltage decreases. Thus, VSC decreases and the peak value of VROCP are controlled to be low, and the peak drain current of ID decreases. This control prevents the output voltage from increasing. ● Heavy Load Conditions When load conditions become greater, the control circuit performs the inverse operation to that described above. Thus, VSC increases and the peak drain current of ID increases. This control prevents the output voltage from decreasing. U1 Q1 OCP 8 ● For the PCB trace layout of the current detection resistor, ROCP, See Section 9.5. ● Match the turn-on timing to a VDS bottom point. ● Lower the value of the voltage resonant capacitor, CV, and the value of the capacitor in the secondary side snubber circuit. ● Add a CR filter with R12 and C9 to the OCP pin as shown in Figure 8-8. The CR filter should be determined according to the surge voltage level. It is necessary to check and adjust the CR filter values because they change the OCP detection level and the load condition switched to burst oscillation mode at standby. When the CR filter is unnecessary, make R12 short and C9 open. When it is added, the target value of R12 is 100 to 330Ω, and that of C9 is 470pF to 680pF. VOCP(H)' of Figure 8-10 is the overcurrent detection threshold voltage after input compensation in Section 8.8. GND FB/OLP R12 6 In the current-mode control method, the FB comparator and/or the OCP comparator may respond to the surge voltage resulting from the drain surge current in turning-on the power MOSFET, and may turn off the power MOSFET irregularly. Leading Edge Blanking, tBW = 495 ns, is built-in to prevent these comparators from malfunction caused by the surge voltage resulting from turning-on the power MOSFET. As shown in Figure 8-10, when the power MOSFET turns on, if the drain current surge pulse width is large, the following adjustments are required so that the surge pulse width falls within tBW. 1 tBW PC1 ROCP C9 Figure 8-8. VROCP C3 VOCP(H)' IFB FB/OLP Peripheral Circuit Target voltage + VSC - VROCP FB comparator Surge voltage width in turning-on Figure 8-10. OCP Pin Voltage Waveform OCP pin voltage Drain current, ID Figure 8-9. Drain Current, ID, and FB Comparator Operation in Normal Operation SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 11 SSC1S310A Series 8.3. Quasi-Resonant Operation and Bottom-On Timing tONDLY : Half cycle of free oscillation 8.3.1. Quasi-Resonant Operation Figure 8-11 shows the circuit of a flyback converter. A flyback converter is a system which transfers the energy stored in the transformer to the secondary side when the primary side power MOSFET is turned off. After the energy is completely transferred to the secondary, when the MOSFET keeps turning off, the MOSFET drain node begins free oscillation based on the LP of the transformer and CV across the drain and source pins. The quasi-resonant operation is the VDS bottom-on operation that turns-on the MOSFET at the bottom point of VDS free oscillation. Figure 8-12 shows an ideal VDS waveform during bottom-on operation. Using bottom-on operation, switching loss and switching noise are reduced and it is possible to obtain converters with high efficiency and low noise. This IC performs bottom-on operation not only during normal quasi-resonant operation, but also during bottom-skip quasi-resonant operation. This allows reduction of the operation frequency during light load conditions, to improve efficiency across the full range of loads. EFLY EIN VDS 0 Bottom point IOFF 0 ID 0 tON Figure 8-12. Ideal bottom-on operation waveform (Power MOSFET turn-on at a bottom point of a VDS waveform) 8.3.2. Bottom-On Timing VF NP T1 EIN EFLY ID NS D4 LP P S IOFF VOUT C6 C1 CV Figure 8-11. Basic Flyback Converter Circuit In Figure 8-11, symbols means as follows: EIN is input voltage, EFLY is flyback voltage, NP EFLY = × (VOUT + VF ), NS NP is primary side number of turns, NS is secondary side number of turns, VOUT is output voltage, VF is forward voltage drop of the secondary side rectifier, ID is drain current of power MOSFET, IOFF is secondary side rectifier flowing current while the power MOSFET is off, CV is voltage resonant capacitor, and LP is primary side inductance. Figure 8-13 shows the voltage waveform of the BD pin peripheral circuit and auxiliary winding, D. The following setup is required with the BD pin. ● Bottom-on timing setup (described here, below) ● OCP input compensation value setup (see Section 8.8) The components DZBD, RBD1, RBD2, and CBD, are connected to the BD pin peripheral circuit as shown in Figure 8-13, with values that are determined with the above-mentioned steps 1) and 2). This delay time, tONDLY, for bottom-on, from the start of VDS free oscillation to the timing of turning-on the power MOSFET, is created by exploiting the auxiliary winding voltage, which synchronizes to the drain voltage VDS waveform. The voltage on either end of RBD1 and RBD2 is the voltage subtracted the forward voltage drop, VF, of DZBD from the flyback voltage, Erev1, of the auxiliary winding, D. The quasi-resonant signal, Erev2, on the BD pin, is the voltage divided the former voltage by RBD1 and RBD2. The delay time, tONDLY, is adjusted by Erev2 and CBD. After the power MOSFET turns off, while the quasiresonant signal increases to the Quasi-Resonant Operation Threshold Voltage 1, VBD(TH1) = 0.24 V, the power MOSFET remains off. After that, when Erev2 decreases enough to cross the Quasi-Resonant Operation Threshold Voltage 2, VBD(TH2) = 0.17 V, the power MOSFET turns on again. In addition, at this point, the threshold voltage SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 12 SSC1S310A Series automatically increases to VBD(TH1) to prevent malfunction of the quasi-resonant operation from noise interference. drain voltage, VDS, the drain current, ID, and the quasiresonant signal, under the maximum input voltage and the maximum output power. An initial reference value for CBD is about 1000pF. The following show how to adjust the turn-on point: ● RBD1 and RBD2 Setup RBD1 and RBD2 must set the range for the quasiresonant signal, VBD(TH1) = 0.34 V(max.) or more under input and output conditions where VCC becomes lowest, but less than the absolute maximum rating of the BD pin, 6.0 V, under conditions where VCC becomes highest. The target voltage of Erev2 is about 3.0 V, and the effective pulse width must be 1.0 µs or more between the two points VBD(TH1) = 0.34 V (max.) and VBD(TH2) = 0.27 V (max.) ● If the turn-on point precedes the bottom of the VDS signal (see Figure 8-14), it causes higher switching losses. In that situation, after confirming the initial turn-on point, delay the turn-on point by increasing the CBD value gradually, so that the turn-on will match the bottom point of VDS. ● In the converse situation, if the turn-on point lags behind the VDS bottom point (see Figure 8-15), it causes higher switching losses also. After confirming the initial turn-on point, advance the turn-on point by decreasing the CBD value gradually, so that the turn-on will match the bottom point of VDS. ● CBD Setup The delay time, tONDLY, after which the power MOSFET turns on, is adjusted by the value of CBD, so that the power MOSFET turns on at the bottom-on of VDS as shown in Figure 8-12, while the power MOSFET Clamping Snubber T1 EIN P C1 D2 4 Q1 CV R2 D Erev1 Flyback voltage 0 Efw1 C2 7 VCC ST Auxiliary Winding Voltage Waveform EIN EFLY RST Forward voltage ｔON DZBD U1 R12 6 RBD1 OCP BD ROCP C9 BD pin Voltage Waveform About 3.0 V recommended, but less than 6.0 V acceptable GND 8 2 CBD RBD2 Erev2 VBD(TH2) VBD(TH1) Erev2 0 Figure 8-13. BD Pin Peripheral Circuit (Left) and Auxiliary Winding Voltage (Right) SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 13 SSC1S310A Series Free oscillation, fR Early turn-on point VDS 0 Delayed turn-on point VDS 0 Bottom point Bottom point IOFF 0 ID 0 IOFF 0 ID 0 ｔON VBD(TH1) VBD 0 Auxiliary Winding voltage VD 0 ｔON VBD(TH1) VBD(TH2) VBD 0 Auxiliary Winding voltage VBD(TH2) VD 0 Figure 8-14. When the Turn-on of a VDS Waveform Occurs before a Bottom Point 8.3.3. BD Pin Blanking Time Figure 8-16 shows two different BD pin waveforms, comparing transformer coupling conditions between the primary and secondary winding. The poor coupling tends to happen in a low output voltage transformer design with high NP/NS turns ratio (NP and NS indicate the number of turns of the primary winding and secondary winding, respectively), and it results in high leakage inductance. The poor coupling causes high surge voltage ringing at the power MOSFET drain pin when it turns off. That high surge voltage ringing is coupled to the auxiliary winding and then the inappropriate quasiresonant signal occurs. The BD pin has a blanking period of 250ns(max.) to avoid the IC reacting to it, but if the surge voltage period continues that value or more, the IC responds to it and repeatedly turns the power MOSFET on and off at high frequency. This result in an increase of the MOSFET power dissipation and temperature, and the power MOSFET can be damaged. The following adjustments are required when such high frequency operation occurs. ● CBD must be connected near the BD pin and the GND pin. ● The circuit trace loop between the BD pin and the GND pin must be separated from any traces carrying high current. Figure 8-15. When the Turn-on of a VDS Waveform Occurs after a Bottom Point ● The coupling of the primary winding and the auxiliary winding must be good. ● The clamping snubber circuit (see Figure 8-13) must be adjusted properly. VBD(TH1)= 0.24V VBD(TH2)= 0.17V Erev2 Normal Waveform (Good Coupling) VBD(TH1)= 0.24V VBD(TH2)= 0.17V Erev2 BD pin blanking time 250 ns (max.) Inappropriate Waveform (Poor Coupling) Figure 8-16. The Difference of BD Pin Voltage Waveform by the Coupling Condition of the Transformer; Good Coupling Versus Inappropriate Coupling SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 14 SSC1S310A Series 8.3.4. Bottom Skip Quasi-Resonant Operation In order to reduce switching losses during light to medium load conditions, in addition to quasi-resonant operation, the bottom skip function is built in, to limit the rise of the power MOSFET operation frequency. This function monitors the power MOSFET drain current (in fact, the OCP pin voltage), it automatically changes to normal quasi-resonant operation during heavy load conditions, and it also changes to bottom skip quasi-resonant operation during light to medium loads. Figure 8-17 shows the operation state transition diagram of the output load from light load to heavy load. Figure 8-18 shows that from heavy load to light load. As these are state change diagrams without input compensation of OCP, the overcurrent detection threshold voltage shows just a VOCP(H) = 0.910 V. This IC has a built-in automatic multi-mode control which changes among the following three operational modes according to the output loading state: auto standby mode, one bottom-skip quasi-resonant operation, and normal quasi-resonant operation. (Light load) One Bottom-Skip Quasi-Resonant ● The mode is changed from one bottom-skip quasiresonant operation to normal quasi-resonant operation (Figure 8-17), when load is increased from one bottom-skip operation, the MOSFET peak drain current value increases, the on-time widens, and thus the peak value of the OCP pin voltage increases. When the load is increased further and the OCP pin voltage increases to VOCP(BS1), the mode is changed to normal quasi-resonant operation. ● The mode is changed from normal quasi-resonant operation to one bottom-skip quasi-resonant operation (Figure 8-18), when load is reduced from normal quasi-resonant operation, the MOSFET peak drain current value decreases, the on-time shortens, and thus the peak value of the OCP pin voltage decreases. When the load is reduced further and the OCP pin voltage decreases to VOCP(BS2), the mode is changed to one bottom-skip quasi-resonant operation. This suppresses the rise of the operation frequency. Normal Quasi-Resonant (Heavy load) VDS OCP pin voltage VOCP(H)= 0.910V VOCP(BS1)= 0.572V Figure 8-17. (Heavy load) Operation State Transition Diagram from Light Load to Heavy Load Conditions Normal Quasi-Resonant One Bottom-Skip Quasi-Resonant (Light load) VDS OCP pin voltage VOCP(H)= 0.910V VOCP(BS2)= 0.289V Figure 8-18. Operation State Transition Diagram from Heavy Load to Light Load Conditions SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 15 SSC1S310A Series As shown in Figure 8-19, in the process of the increase and decrease of load current, hysteresis is imposed at the time of each operational mode change. For this reason, the switching waveform does not become unstable near the threshold voltage of a change, and this enables the IC to switch in a stable operation. One Bottom-Skip Quasi-Resonant VOCP(H) VOCP(BS1) Normal Quasi-Resonant VOCP(BS2) Load current Figure 8-19. Hysteresis at the Time of an Operational Mode Change Figure 8-20 shows the effective pulse width of quasiresonant signal waveform under light load condition. In order to perform stable normal quasi-resonant operation and one bottom-skip operation, it is necessary to ensure that the pulse width of the quasi-resonant signal is 1.0 μs or more under the conditions of minimum input voltage and minimum output power. The pulse width of the quasi-resonant signal, Erev2, is defined as the interval between VBD(TH1) = 0.34 V(max.) on the rising edge, and VBD(TH2) = 0.27 V(max.) on the falling edge of the pulse. Erev2 VBD(TH1)= 0.34V(max.) VBD(TH2)= 0.27V(max.) OCP pin voltage Pulse width 1.0µs or more (a) Normal Quasi-Resonant Operation Resonant Signal 8.4. Auto Standby Function The auto standby function automatically changes the IC operation mode to standby mode with burst oscillation, when the MOSFET drain current, I D, decreases during light loads. The OCP pin circuit monitors ID. When the OCP pin voltage decreases to the standby state threshold voltage (about 9% compared to VOCP(H) = 0.910 V), the auto standby function changes switching mode to standby mode (see Figure 8-21). The burst oscillation mode is controlled, so that when the FB/OLP pin voltage decreases to VFB(STBOP), the IC stops switching operation, and when it increases to that value or more, the IC starts switching operation. Because the burst oscillation mode has a certain interval of off-time, switching losses are reduced and efficiency is improved under light load conditions. Generally, a burst interval is set to several kilohertz or less, in order to improve the efficiency during light loads. In this low frequency, audible noise may occur from the transformer. However, this IC keeps the peak drain current low during burst oscillation mode, and suppresses the audible noise of the transformer further by enabling the step-on burst oscillation function, which expands the pulse width gradually. During the transition stage to burst oscillation mode, if the VCC pin voltage decreases to the Startup Current Supply Threshold Voltage, VCC(BIAS) = 11.0 V, the bias assist function is activated. Because this function provides the startup current, ICC(STARTUP) to the VCC pin, in order to prevent the fall of the VCC pin voltage, it enables stable standby operation. If the bias assist function operates during normal operation (which includes burst oscillation mode periods), the power consumption of the IC increases. Therefore, in order to always keep the VCC pin voltage more than VCC(BIAS), it is necessary to adjust the turn ratio between the auxiliary winding and secondary winding of the transformer, and/or minimize the value of R2 shown in Figure 8-5. Erev2 VBD(TH1)= 0.34V(max.) VBD(TH2)= 0.27V(max.) OCP pin voltage Pulse width 1.0µs or more (b) One Bottom-Skip Quasi-Resonant Operation Figure 8-20. Effective Pulse Width of a Quasi- SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 16 SSC1S310A Series Burst oscillation Output current, IOUT Below several kHz Drain current, ID Normal operation Figure 8-21. 8.5. Standby operation Normal operation Auto Standby Mode Timing minimized because switching period is shorter than oscillation stop period. When the fault condition is removed, the IC returns to normal operation automatically. Overvoltage Protection (OVP) When the voltage between the VCC pin and GND pin increases to the OVP Operation Threshold Voltage, VCC(OVP) = 31.5 V, the overvoltage protection (OVP) is activated, and switching operation is stopped. The IC has two operation types of the OVP. One is the auto restart. The other is latched shutdown. When the auxiliary winding supplies the VCC pin voltage, the VCC pin voltage is proportional to the output voltage. Thus, an excessive output voltage of the secondary side when the output control circuit is open can be detected by the OVP. The output voltage of the secondary side at the OVP activation, VOUT(OVP), is calculated approximately as follows: ● Latched Shutdown Type: SSC1S312A When the OVP is activated, the IC stops switching operation in the latched state. For keeping the latched state, the bias assist function is activated when VCC pin voltage decreases to VCC(BIAS). As a result, the VCC pin voltage is kept to over the VCC(OFF). Releasing the latched state is done by turning off the input voltage and by dropping the VCC pin voltage below VCC(OFF). 8.6. Overload Protection (OLP) Figure 8-22 shows the FB/OLP pin peripheral circuit. VOUT(OVP) VOUT(NORMAL) = × 31.5 (V) VCC(NORMAL) (4) Where, VOUT(NORMAL) is output voltage in normal operation, and VCC(NORMAL) is VCC pin voltage in normal operation ● Auto-restart Type: SSC1S311A When the OVP is activated, the IC stops switching operation. The VCC pin voltage decreases to VCC(OFF) = 9.4 V, because the bias assist function is disabled during the OVP operation. Then, the control circuit stops operation by the UVLO (undervoltage lockout) circuit, and the IC reverts to the state before startup. When the VCC pin voltage is increased to VCC(ON) = 15.1 V by the startup current, the control circuit returns to normal operation again. In this way, the intermittent oscillation is repeated by the UVLO circuit during the excess voltage condition. The intermittent oscillation reduces the stresses of a component such as the power MOSFET and the secondary rectifier diode. Also, power consumption in the intermittent operation is U1 GND FB/OLP 8 1 IFB PC1 R1 C4 Figure 8-22. C3 FB/OLP Pin Peripheral Circuit When the drain peak current is limited by the OCP operation, the output voltage, VOUT, decreases, and then the feedback current from the secondary photo-coupler, IFB, becomes zero. As a result, the capacitor, C4, is charged, and the FB/OLP pin voltage increases. When SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 17 SSC1S310A Series the FB/OLP pin voltage increase to VFB(MAX) = 4.05 V, the capacitor C4 is charged by IFB(OLP) = −10 µA. When the FB/OLP pin voltage increases to VFB(OLP) = 5.96 V, the overload protection (OLP) is activated, and switching operation is stopped. The time of the FB/OLP pin voltage from VFB(MAX) = 4.05 V to VFB(OLP) = 5.96 V is defined as the OLP Delay Time, tDLY. Because the capacitor C3 for phase compensation is small compared to C4, the approximate value of tDLY is determined as follows: t DLY ≈ VFB(OLP) − VFB(MAX) |IFB(OLP) | × C4 latched state, the bias assist function is activated when VCC pin voltage decreases to VCC(BIAS). As a result, the VCC pin voltage is kept to over the VCC(OFF). Releasing the latched state is done by turning off the input voltage and by dropping the VCC pin voltage below VCC(OFF). VCC Pin Voltage VFB(OLP) = 5.96 V, VFB(MAX) = 4.05 V, IFB(OLP) = −10μA, and C4 = 4.7μF, the value of tDLY is approximately 0.9s. The recommended value of R1 is 47 kΩ. FB/OLP Pin Voltage VFB(OLP) VFB(MAX) Drain Current, ID The IC has two operation types of the OLP. One is the auto restart. The other is latched shutdown. ● Auto-restart Type: SSC1S311A Figure 8-23 shows the auto-restart OLP operation waveforms. When the OLP is activated, the switching operation is stopped, and the bias assist function is disabled. Then an intermittent oscillation is repeated by the UVLO circuit (for more details, see Section 8.5). When the fault condition is removed, the IC returns to normal operation automatically. VCC Pin Voltage VCC(ON) VCC(OFF) Charged by IFB(OLP) VFB(OLP) VFB(MAX) tDLY Drain Current, ID Figure 8-23. Latch release VCC(BIAS) VCC(OFF) (5) If FB/OLP Pin Voltage Off-line voltage is cut off Auto-restart Type OLP Operation Waveforms ● Latched Shutdown Type: SSC1S312A Figure 8-24 shows the auto-restart OLP operation waveforms. When the OLP is activated, the IC stops switching operation in the latched state. For keeping the Figure 8-24. 8.7. Charged by IFB(OLP) tDLY Latched Shutdown Type OLP Operation Waveforms Thermal Shutdown (TSD) If the temperature of the IC reaches more than the Thermal Shutdown Temperature Tj(TSD) = 135°C(min.), the Thermal Shutdown (TSD) is activated, and the IC stops switching operation. The IC has two operation types of the TSD. One is the auto restart. The other is latched shutdown. ● Auto-restart Type: SSC1S311A When the OLP is activated, the switching operation is stopped, and the bias assist function is disabled. Then an intermittent oscillation is repeated by the UVLO circuit (for more details, see Section 8.5). When the fault condition is removed and the temperature of the internal control circuit is decreases to Tj(TSD) or less, the IC returns to normal operation automatically. ● Latched Shutdown Type: SSC1S312A When the TSD is activated, the IC stops switching operation in the latched state. For keeping the latched state, the bias assist function is activated when VCC pin voltage decreases to VCC(BIAS). As a result, the VCC pin voltage is kept to over the VCC(OFF). Releasing the latched state is done by turning off the input voltage and by dropping the VCC pin voltage below VCC(OFF). SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 18 SSC1S310A Series 8.8. Overcurrent Protection (OCP) The overcurrent protection circuit (OCP) detects each peak drain current of the power MOSFET on pulse-bypulse basis, by the current detection resistor, ROCP. When the OCP pin voltage reaches the OCP threshold, the IC turns off the power MOSFET and limits the output power. through DZBD from Efw1 is biased by either end of RBD1 and RBD2, and thus the BD pin voltage is provided the voltage on RDB2 divided by the divider of RBD1 and RBD2. Flyback voltage, Erev1 D2 R2 C2 7 VCC D DZBD 8.8.1. Overcurrent Input Compensation Function Output current at OCP, IOUT(OCP) （A） When using a quasi-resonant converter with universal input (85 to 265 VAC), if the output power is set constant, then because higher input voltages have higher frequency, the MOSFET peak drain current becomes low. Because ROCP is fixed, the OCP point in the higher input voltage will shift further into the overload area. Thus, the output current at OCP point in the maximum input voltage, IOUT(OCP), approximately doubles relative to that in the minimum input voltage (see the curve of IOUT without input compensation of Figure 8-25). In order to suppress this phenomenon, this IC has the overcurrent input compensation function. As for determining an input compensation value, it is necessary to avoid excessive input compensation for the output current specification, IOUT. When excessive input compensation is applied, IOUT(OCP) may be below IOUT in the situation where the input voltage is high. Therefore, it is necessary to ensure that IOUT(OCP) remains more than IOUT across the full range of input voltage, such as the curve of IOUT with appropriate input compensation in Figure 8-25. IOUT IOUT target output level IOUT with excessive input compensation AC input voltage（V） 85VAC Figure 8-25. 265VAC OCP Circuit Input Compensation Figure 8-26 shows an overcurrent input compensation circuit, and Figure 8-27 shows Efw1 and Efw2 relative to the input voltage. Also, Figure 8-28 shows the relationship between the overcurrent threshold voltages after input compensation, VOCP(H)', and the BD pin voltage, Efw2. The overcurrent input compensation function compensates the overcurrent detection threshold voltage (normal operation), VOCP(H), according to the input voltage. The forward voltage, Efw1, is proportional to the input voltage, the voltage passed Forward voltage, VDZBD Efw1 U1 R12 ROCP RBD1 6 C9 Figure 8-26. BD OCP GND 8 2 CBD The voltage divided the forward voltage by resistors, Efw2 RBD2 Overcurrent Input Compensation Circuit 100V 230V 0 AC VZ Efw1 0 Efw2 Figure 8-27. IOUT without input compensation IOUT with appropriate input compensation T1 AC OCP input compensation starting point: the point matching, Efw1−VZ= 0V Efw1 and Efw2 Voltage Relative to AC Input Voltage Figure 8-28 shows the relationship between the overcurrent detection threshold voltage after input voltage compensation, VOCP(H)', and Efw2. Read the value of VOCP(H)' according to Efw2 in Figure 8-28. ● DZBD setting: The starting voltage for input compensation is set by the Zener voltage, VZ, of DZBD. According to the input voltage specification or transformer specification, it is required to be VZ = 6.8 to 30 V. ● RBD1 setting: see Section 8.3.2 ● The recommended value of RBD2: 1.0 kΩ Overcurrent input compensation should be adjusted so that the variance of the output current, I OUT(OCP), at an OCP point, is minimized at the high and low input voltage. In addition, the input compensation must be adjusted so that IOUT(OCP) remains more than the output current specification, IOUT, across the full range of input voltage, such as the curve of IOUT with appropriate input compensation in Figure 8-25. If VOCP(H)' is compensated to the Bottom-Skip SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 19 SSC1S310A Series Operation Threshold Voltage, VOCP(BS1), or less, the IC will change from one bottom-skip operation to normal quasi-resonant operation, and thus will raise the operation frequency and will provide output power. Therefore, switching losses in normal quasi-resonant operation is higher than that in bottom-skip operation. In this case, when the input compensation is compensated to VOCP(BS1) or less, the temperature of the power MOSFET should be checked in normal quasi-resonant operation switched from bottom-skip operation, by changing load condition. Efw2, which includes surge voltage, must be within the absolute maximum rating of the BD pin voltage (–6.0 V to 6.0 V) at the maximum input voltage. Figure 8-29 shows each voltage waveform for the input voltage in normal quasi-resonant operation. operation), VOCP(H). ● Point B to Point D: VDZBD < Efw1 When the input voltage increases and Efw1 exceeds the Zener voltage, VZ, of DZBD, Efw2 will be produced as a negative voltage to compensate the Overcurrent Detection Threshold Voltage (normal operation), VOCP(H). Efw2 is generally adjusted to the BD pin voltage of Efw2 = –3.0 V at the maximum input voltage. Adjustment of Efw2 will change the overcurrent detection threshold voltage by an overcurrent input compensation function. Therefore, Efw2 must be adjusted while checking the input compensation starting point and the amount of input compensation. Also, the variations of the overcurrent detection threshold voltage after input compensation, VOCP(H)', can be calculated by the minimum and maximum values shown in Figure 8-28. ● Point A: VDZBD ≥ Efw1 Efw2 will be produced negative voltage, and the detection voltage for an overcurrent event is the Overcurrent Detection Threshold Voltage (normal 1 VOCP(H)=0.910 : Recommended use range VOCP(H)' (V) 0.8 0.6 Max. 0.4 Typ. Min. 0.2 0 −1 -1 0 0 Figure 8-28. −2 −3 −4 -2 -3 -4 BD Pin Voltage, Efw2 (V) −5 -5 −6 -6 Overcurrent Threshold Voltage after Input Compensation, VOCP(H)' (Reference for Design Target Values) Auxiliary winding voltage Erev1 0 tON Efw1 tON tON tON 0 VDZBD A B 100V C Input voltage DZBD Zener voltage, Vz D 230V 0 Input voltage Efw2 At the input voltage where Efw1 reaches VZ or more, Efw2 goes negative. Figure 8-29. Each Voltage Waveform for the Input Voltage in Normal Quasi-Resonant Operation SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 20 SSC1S310A Series When RBD2 = 1 kΩ, RBD1 = 7.5 kΩ, VF = 0.7 V, and Erev1 = 20 V, Erev2 of Figure 8-13 can be calculated as follows: 8.8.2. Reference BD Pin Peripheral Components Setting This example demonstrates the determination of external component values for the BD pin peripheral circuit. It assumes universal input (85 VAC to 265 VAC) is being used, and input compensation begins from the input voltage of 120 VAC. The transformer is assumed to have primary winding with NP = 40T, and an auxiliary winding with ND = 5 (turn). To determine the Zener voltage, VZ, of DZBD, Efw1 at 120 VAC is calculated as follows: Efw1 = ND × VIN(AC) × √2 NP (6) The Zener diode rating, VZ, is chosen to be 22 V, a standard value. RBD1 results in Efw2 = –3.0 V at the maximum input voltage of 265 VAC, as follows: R BD2 ND × ( × VIN(AC) × √2 − ZBD − |Efw2 |) |Efw1 | NP (7) = 1 kΩ 5 turn ×( × 265 VAC × √2 − 22 V − |−3V|) |−3V| 40 turn = 7.28 kΩ . The RBD1 rating is chosen to be 7.5 kΩ of the E series. Choosing RBD2 = 1.0kΩ, the |Efw2| value at 265 VAC can be calculated as follows: Efw2 = = R BD2 × (|Efw1 | − ZBD ) R BD1 + R BD2 = R BD2 × (Erev1 − VF ) R BD1 + R BD2 (9) 1 kΩ × (20 V − 0.7 V) = 2.27 V. 7.5 kΩ + 1 kΩ In this case, the quasi-resonant voltage Erev2 meets the design guidelines: it is Quasi-Resonant Operation Threshold Voltage 1, VBD(TH1) = 0.24 V or more, and Efw2 and Erev2 are kept within the limits of the Absolute Maximum Rating (–6.0 V to 6.0 V) of the BD pin. 8.8.3. Reference Example of No Overcurrent Input Compensation Required 5 turn = × 120 VAC × √2 = 21.2 V . 40 turn R BD1 = Efw2 = (8) 1 kΩ 5 turn ×( × 265 VAC × √2 − 22 V) 7.5 kΩ + 1 kΩ 40 turn = 2.92 V. Referring to Figure 8-28, when compensated by Efw2 = –2.92 V, the overcurrent threshold voltage after input compensation, VOCP(H)' , is set to about 0.66 V (typ.). When the input voltage is narrow range, or provided from a pre-regulator such as PFC of active filter, the variation of the input voltage is small. Thus, the variation of OCP point may become less than that of the universal input voltage specification. When overcurrent input compensation is not required, the input compensation function can be disabled by substituting a high-speed diode for the Zener diode (DZBD), and by keeping the BD pin voltage from being negative voltage. In addition, the following formula shows the reverse voltage of a high-speed diode. The high-speed selection should take account of its derating. Efw1 = 8.9. ND × Maximum input voltage NP (10) Maximum On-Time Limitation Function When the input voltage is low or in a transient state such that the input voltage turns on or off, the on-time of the power MOSFET is limited to the Maximum OnTime, tON(MAX) = 40.0 μs (see Figure 8-30). Thus, the peak drain current is limited, and the audible noise of the transformer is suppressed. In designing a power supply, the on-time must be less than tON(MAX). If such a transformer is used that the ontime is tON(MAX) or more, under the condition with the minimum input voltage and the maximum output power, the output power would become low. In that case, the transformer should be redesigned taking into consideration the following: SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 21 SSC1S310A Series ● Inductance, LP, of the transformer should be lowered in order to raise the operation frequency. ● Lower the primary and the secondary turns ratio, NP/NS, to lower the duty cycle. ID VDS t Confirmation of Maximum On-time 8.10. DRV Pin Peripheral Components Figure 8-31 shows the peripheral circuit around DRV pin. The DRV pin is the gate drive pin for driving the external power MOSFET. The output voltage, VDRV, is 7.5 V (min.), the peak source current and peak sink current are −150 mA and 608 mA, respectively. It is necessary to choose the external power MOSFET of which the gate threshold voltage, VGS(th) is less than VDRV enough across the full temperature range in the application. R4, R5, and D3 should be adjusted considering power losses of the power MOSFET, gate waveform (reduction of ringing caused by pattern layout, and others), and EMI noise, based on actual operation in the application. R3 prevents malfunctions caused by steep dv/dt at turning off the power MOSFET. It is recommended to place a resistor of 10kΩ to 100kΩ close to Gate and Source of the power MOSFET. R5 D3 9.1. Design Notes Peripheral Components Take care to use properly rated and proper type of components. Maximum on time t Figure 8-30. 9. ● Input and output electrolytic capacitor Apply proper design margin to ripple current, voltage, and temperature rise. Use of high ripple current and low impedance types, designed for switch-mode power supplies, is recommended, depending on their purposes. ● Transformer Apply proper design margin to core temperature rise by core loss and copper loss. Because switching currents contain high frequency currents, the skin effect may become a consideration. In consideration of the skin effect, choose a suitable wire gauge in consideration of rms current and a current density of about 3 to 4A/mm2. If measures to further reduce temperature are still necessary, the following should be considered to increase the total surface area of the wiring: - Increase the number of wires in parallel. - Use litz wires. - Thicken the wire gauge. ● Current detection resistor, ROCP A high frequency switching current flows to ROCP, and may cause poor operation if a high inductance resistor is used. Choose a low inductance and high surgetolerant type. 9.2. Transformer Design The design of the transformer is fundamentally the same as the power transformer of a Ringing Choke Converter (RCC) system: a self-excitation type flyback converter. However, because the duty cycle will change due to the quasi-resonant operations delaying the turn-on, the duty cycle needs to be compensated. 5 DRV VF NP T1 R4 R3 U1 EFLY ID NS D4 LP P S IOFF VO C6 EIN ROCP Figure 8-31. GND C1 CV 8 DRV Pin Peripheral Circuit Figure 9-1. SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 Quasi-resonant Circuit 22 SSC1S310A Series When the duty cycle, DON, is calculated by the ratio of the primary turns, NP, and the secondary turns, NS, the inductance, LP' on the primary side, taking into consideration the delay time, can be calculated by Equation(11). (EIN(MIN) × DON ) = 2 (11) where: PO is the maximum output power, fO is the minimum operation frequency of quasiresonant operation, CV is the voltage resonance capacitor connected between the drain and source of the power MOSFET, η1 is the transformer efficiency, DON is the duty cycle at the minimum input voltage: DON = EFRY . EIN(MIN) + EFRY EIN(MIN) is the C1 voltage of Figure 9-1 at the minimum input voltage, EFLY is the flyback voltage: EFRY = (17) where: tONDLY is the delay time of quasi-resonant operation, IIN is the average input current, η2 is the conversion efficiency of the power supply, IDP is the peak drain current DON' is the duty cycle after compensation, and VO is the secondary side output voltage 2 2 × PO × f0 (√ + EIN(MIN) × DON × f0 × π × √CV ) η1 NP × (VO + VF ) EFRY The minimum operation frequency of quasi-resonant operation, fO, can be calculated by Equation (18) In transformer design, AL-value and NP must be set in a way that the ferrite core does not saturate. Here, use ampere turn value (AT), the result of IDP × NP and the graph of NI-Limit (AT) versus AL-value (Figure 9-2 is an example of it). NI-Limit is the limit that the ampere turn value should not exceed; otherwise the core saturates. When choosing a ferrite core to match the relationship of NI-Limit (AT) versus AL-value, it is recommended to set the calculated NI-Limit value below about 30% from the NI-Limit curve of ferrite core data, as shown in the hatched area containing the design point in Figure 9-2, to provide a design margin in consideration of temperature effects and other variations. f0 ND × (VO + VF ) , and NP 2P 2P −√ O + √ O + η1 η1 VF is the forward voltage drop of D4. = Each parameter, such as the peak drain current, I DP, is calculated as follows: t ONDLY = π√LP ′ × CV (12) DON ′ = DON (1 − f0 × t ONDLY ) (13) 2 2 4π(EIN(MIN) × DON ) × √CV √LP ′ 2π√CV × EIN(MIN) × DON ( ) (18) IIN = PO 1 × η2 EIN(MIN) (14) IDP = 2 × IIN DON ′ (15) Saturation region lower boundary NI-limit (AT) LP ′ NS = Saturation margin= below about 30% NI-Limit design point as example Al-value (nH/T2) NP = √ LP ′ AL − value (16) Figure 9-2. SSC1S310A-DSE Rev.2.3 SANKEN ELECTRIC CO., LTD. Jul. 03, 2023 https://www.sanken-ele.co.jp/en © SANKEN ELECTRIC CO., LTD. 2012 Example of NI-limit vs. AL-value Characteristics 23 SSC1S310A Series 9.3. Protection against Negative Input Voltage at Start-up Pin 9.4. If the ST pin voltage is applied more negative voltage than −0.3 V, the IC may be out of normal operation, and thus either a diode or a resistor must be added, as shown in Figure 9-3. The diode or resistor should be chosen in the following specification. In addition, it is necessary to check the operation based on actual operation across the full range of input voltage in the application. Add a resistor or a diode Phase Compensation A typical phase compensation circuit with a secondary shunt regulator (U2) is shown in Figure 9-4. The value of C7 is recommended to be about 0.047 µF to 0.47μF, and should be chosen based on actual operation in the application. Place C3 between the FB/OLP pin and the GND pin, as shown in Figure 9-5, to perform high frequency noise reduction and phase compensation. The value of C3 is recommended to be about 470pF to 0.01μF, and should be chosen based on actual operation in the application. T1 EIN C1 L1 D4 T1 VOUT P RST R9 R6 PC1 DRV 4 ST VCC 7 R7 D2 R2 C8 C7 U2 U1 C2 GND Figure 9-3. R10 C6 S R11 D 8 R8 GND ST Pin Countermeasure against Negative Applied Voltage Figure 9-4. Peripheral Circuit around Secondary Shunt Regulator (U2) ● The recommended specification of additional diode or resistor U1 - The case of resistor, RST GND type of resistors, such as metal oxide film. The minimum value: 5.6 kΩ The maximum value: Meet Equation (19). 8 FB/OLP 1 PC1 |ICC(STARTUP) (min. )| × R ST + VSTART(ON) (max. ) C3 (19) IFB ≪ EIN (min. ) Where: ICC(STARTUP)(min.) is −4.5 mA, VSTART(ON)(max.) is 24 V, and EIN(min.) is the C1 voltage at the minimum input voltage. The value of RST in universal input range (85 VAC to 265 VAC) is 5.6 kΩ to 15 kΩ. - Diode characteristics Peak reverse voltage, VRM: >35 V Forward current, IF: >4.5 mA Reverse recovery time, trr: