Off-Line PRC Controllers with Integrated Power MOSFET
STR-A6100 Series
Description
Packageｓ
The STR-A6100 series are power ICs for switching
power supplies, incorporating a MOSFET and a current
mode PRC controller IC.
PRC (Pulse Ratio Control) controls on-time with
fixed off-time.
The IC includes a startup circuit and a standby
function to achieve the low standby power. The rich set
of protection features helps to realize low component
counts, and high performance-to-cost power supply.
DIP8
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
DIP7
Not to Scale
Selection Guide
Features
• Package
• Current Mode Type Pulse Ratio Control
• Auto Standby Function
•
•
•
•
Part Number
Normal Operation ------------------------------ PRC Mode
Standby ---------------------------- Burst Oscillation Mode
No Load Power Consumption < 40mW
Leading Edge Blanking Function
Auto Bias Function
Protections
Overcurrent Protection (OCP); pulse-by-pulse
Overload Protection (OLP); auto-restart
Overvoltage Protection (OVP); latched shutdown
Thermal Shutdown Protection (TSD); latched
shutdown
−
Yes
STR-A6131M
−
Yes
STR-A6153E
Yes
Yes
STR-A6151
Yes
Yes
STR-A6151M
Yes
Yes
STR-A6159
Yes
Yes
STR-A6159M
Yes
−
STR-A6169
Yes
Yes
• Specifications
Typical Application
VAC
L51
D51
T1
C1
VOUT
(+)
R1
C5
PC1
P
D1
S
R54
R51
R55
C51
DST
R52
STR-A61××
Fixed
off-time
8 μs
Auto bias
function
Yes
Startup
resistance
−
STR-A61××M
11.5 μs
−
−
−
Yes*
D
C6
U2
5
7
D
D2
ST
NC
R2
STR-A61××E
11.5 μs
* ST pin does not need Diode.
• Power MOSFET Electrical Characteristics and output
C53
power, POUT(1)
C52 R53
8
R56
(-)
U1
STR-A6100
C2
Part Number
D
S/OCP VCC GND FB/OLP
2
3
4
ot
1
DZ1
N
ROCP
C4
C3
PC1
Applications
• White goods
• Auxiliary SMPS
• Low power SMPS, etc.
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
CY
DIP8
STR-A6131
Part Number
BR1
DIP7
VDSS
(min.)
RDS(ON)
(max.)
POUT
(Open frame)
AC85
AC220V
~265V
STR-A6131
500 V
3.95 Ω
13 W(2)
15 W(3)
STR-A6131M
STR-A6153E
1.9 Ω
22 W
18 W
STR-A6151
3.95 Ω
15 W
13 W
STR-A6151M
650 V
STR-A6159
6Ω
13 W
10 W
STR-A6159M
STR-A6169
800 V
19.2 Ω
8W
5W
(1)
The output power is actual continues power that is measured
at 50 °C ambient. The peak output power can be 120 to
140 % of the value stated here. Core size, ON Duty, and
thermal design affect the output power. It may be less than
the value stated here.
(2)
AC100V
(3)
AC120V
SANKEN ELECTRIC CO.,LTD.
http://www.sanken-ele.co.jp/en/
1
STR-A6100 Series
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Absolute Maximum Ratings --------------------------------------------------------------------------- 3
2.
Electrical Characteristics ------------------------------------------------------------------------------ 3
3.
Performance Curves ------------------------------------------------------------------------------------ 5
3.1
Derating Curves ------------------------------------------------------------------------------- 5
3.2
MOSFET Safe Operating Area Curves --------------------------------------------------- 6
3.3
Ambient Temperature versus Power Dissipation, PD1 Curves------------------------ 7
3.4
Internal Frame Temperature versus Power Dissipation, PD2 Curves --------------- 7
3.5
Transient Thermal Resistance Curves ---------------------------------------------------- 8
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
1.
4.
Block Diagram------------------------------------------------------------------------------------------ 10
5.
Pin Configuration Definitions ----------------------------------------------------------------------- 11
6.
Typical Application------------------------------------------------------------------------------------ 12
7.
Physical Dimensions ----------------------------------------------------------------------------------- 13
8.
Marking Diagram-------------------------------------------------------------------------------------- 14
9.
Operational Description -----------------------------------------------------------------------------9.1
Startup Operation --------------------------------------------------------------------------9.2
Undervoltage Lockout (UVLO)----------------------------------------------------------9.3
Constant Output Voltage Control -------------------------------------------------------9.4
Leading Edge Blanking Function -------------------------------------------------------9.5
Auto Standby Function --------------------------------------------------------------------9.6
Auto Bias Function (STR-A61xx) -------------------------------------------------------9.7
Overcurrent Protection Function (OCP) ----------------------------------------------9.8
Overload Protection (OLP) ---------------------------------------------------------------9.9
Overvoltage Protection (OVP) -----------------------------------------------------------9.10
Thermal Shutdown Function (TSD) -----------------------------------------------------
15
15
15
15
16
16
17
17
17
18
18
10. Design Notes -------------------------------------------------------------------------------------------- 19
10.1
External Components----------------------------------------------------------------------- 19
10.2
PCB Trace Layout and Component Placement --------------------------------------- 21
11. Pattern Layout Example ----------------------------------------------------------------------------- 23
12. Reference Design of Power Supply ----------------------------------------------------------------- 24
N
ot
Important Notes ---------------------------------------------------------------------------------------------- 26
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
2
STR-A6100 Series
1. Absolute Maximum Ratings
• The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.
• Unless otherwise specified, TA is 25 °C, 7 pin = 8 pin
Parameter
(1)
Test Conditions
IDPEAK
Single pulse
Pins
Units
1–3
2–3
4–3
5−3
Rating
3.2
2.5
3.4
1.8
1.2
3.2
2.5
3.4
1.8
1.2
32
72
136
24
7
− 0.5 to 6
35
− 0.5 to 10
− 0.3 to 600
1.35
W
8–1
Notes
A6131/31M
A6151/51M
A
A6153E
A6159/59M
A6169
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Drain Peak Current
Symbol
Maximum Switching
Current
(2)
IDMAX
(3)
8–1
ILPEAK = 2.1 A
ILPEAK = 2.5 A
(4)
Avalanche Energy
(5)
EAS
ILPEAK = 3.4 A
8–1
ILPEAK = 1.8 A
ILPEAK = 1.2 A
S/OCP Pin Voltage
VCC Pin Voltage
FB/OLP Pin Voltage
ST Pin Voltage
MOSFET Power
Dissipation
Control Part Power
Dissipation
VOCP
VCC
VFB/OLP
VST
(6)
PD1
(7)
8–1
(8)
PD2
VCC × ICC
2–3
TF
A6153E
A6159/59M
A6169
A6131/31M
A6151/51M
mJ
A6153E
A6159/59M
A6169
V
V
V
V
W
− 20 to 125
°C
TOP
―
− 20 to 125
°C
Tstg
Tch
―
―
− 40 to 125
150
°C
°C
A61××
A61××M
A6153E
Recommended
operation
temperature
TF = 115 °C (max.)
N
ot
A6151/51M
A
0.46
Frame Temperature in
operation
Operating Ambient
Temperature
Storage Temperature
Junction Temperature
0.15
A6131/31M
2. Electrical Characteristics
• The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.
(1)
Refer to Figure 3-1 SOA Temperature Derating Coefficient Curve
Maximum Switching Current is Drain current that is limited by the VGS(th) of internal MOSFET and the gate drive
voltage of internal control IC setting. TA = −20 to 125 °C
(3)
STR-A61×× : V1-3 = 0.86 V, STR-A61××M/E : V1-3 = 1.28 V
(4)
Refer to Figure 3-2 Avalanche Energy Derating Coefficient Curve
(5)
Single pulse, VDD = 99 V, L = 20 mH
(6)
Refer to Section 3.3 Ta-PD1 curve
(7)
When embedding this hybrid IC onto the printed circuit board (cupper area in a 15 mm × 15 mm)
(8)
Refer to Section 3.4 Ta-PD2 curve
(2)
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
3
STR-A6100 Series
• Unless otherwise specified, TA = 25 °C, VCC = 20 V, 7 pin = 8 pin
Parameter
Symbol
Test
Conditions
Pins
Min.
Typ.
Max.
Units
VCC(ON)
2−3
16
17.5
19.2
V
VCC(OFF)
2−3
9
10
11
V
ICC(ON)
2−3
−
−
4
mA
2−3
−
−
50
µA
Notes
Power Supply Startup Operation
Operation Start Voltage
ICC(OFF)
VCC = 14 V
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Operation Stop Voltage
Circuit Current in
Operation
Circuit Current in Non
Operation
Auto Bias Threshold
Voltage
VCC(BIAS)－VCC(OFF)
(1)
(1)
(2)
VCC(BIAS)
2−3
9.6
10.6
11.6
V
A61××
(2)
−
−
0.2
−
−
V
A61××
2−3
− 1230
− 790
− 340
µA
ISTART(leak)
5−3
−
−
30
µA
8−3
7.3
8
8.7
tOFF(MAX)
Burst Threshold Voltage
VBURST
4−3
Protection Operation
Leading Edge Blanking
Time
tBW
−
OCP Threshold Voltage
VOCP(TH)
1−3
OLP Threshold Voltage
VOLP
4−3
FB/OLP Pin Source
Current in OLP Operation
IOLP
4−3
IFB(MAX)
4−3
Startup Current
ST Pin Leakage Current
ISTARTUP
VCC = 15 V
PRC Operation
Maximum OFF Time
10.5
11.5
12.5
0.70
0.79
0.88
A61××
µs
A61××M
A6153E
Standby Operation
FB/OLP Pin Maximum
Source Current
0.66
0.75
0.84
200
320
480
0.69
0.77
0.86
0.96
1.13
1.28
6.5
7.2
7.9
−35
−26
−18
−34.1
−26
−18.2
−388
−300
−227
−390
−300
−220
A61××
V
A61××M
A6153E
ns
A61××
V
A61××M
A6153E
V
A61××
µA
A61××M
A6153E
A61××
µA
A61××M
A6153E
N
ot
VCC Pin OVP Threshold
VCC(OVP)
2−3
28.7
31.2
34.1
V
Voltage
Latched Shutdown Keep
ICC(H)
2−3
−
−
200
μA
Current
Latched Shutdown
Release Threshold
VCC(La.OFF)
2−3
6.6
7.3
8.0
V
Voltage
Thermal Shutdown
Tj(TSD)
−
135
−
−
°C
Operating Temperature
(1)
VCC(BIAS) > VCC(OFF) always.
(2)
STR-A61××M and STR-A6153E do not have the Auto Bias Threshold voltage because auto bias function is not
included.
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
4
STR-A6100 Series
Parameter
Symbol
Test
Conditions
Pins
Min.
Typ.
Max.
Units
Notes
500
−
−
650
−
−
800
−
−
−
−
300
−
−
1.9
A6153E
−
−
3.95
A6131/31M
A6151/51M
−
−
6
−
−
19.2
8–1
−
−
250
ns
−
−
−
52
°C/W
MOSFET
Drain-to-Source
Breakdown Voltage
ID = 300 μA
VDSS
IDSS
VD = VDSS
8–1
V
A6151/51M
A6159/59M
A6153E
A6169
μA
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Drain Leakage Current
8–1
A6131/31M
On Resistance
RDS(ON)
Switching Time
tf
ID = 0.4 A
VD = 10V
8–1
Ω
A6159/59M
A6169
Thermal Characteristics
(3)
θch-F
(3)
Thermal Resistance
θch-F is thermal resistance between channel and frame. Frame temperature (TF) is measured at the base of pin 3.
3. Performance Curves
80
60
40
N
ot
Safe Operating Area
Temperature Derating Coefficient (%)
100
EAS Temperature Derating Coefficient (%)
3.1 Derating Curves
20
0
0
25
50
75
100
125
150
100
80
60
40
20
0
25
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
75
100
125
150
Channel Temperature, Tch (°C)
Channel Temperature, Tch (°C)
Figure 3-1 SOA Temperature Derating Coefficient Curve
50
Figure 3-2 Avalanche Energy Derating Coefficient Curve
SANKEN ELECTRIC CO.,LTD.
5
STR-A6100 Series
3.2 MOSFET Safe Operating Area Curves
• When the IC is used, the safe operating area curve should be multiplied by the temperature derating coefficient
derived from Figure 3-1.
• The broken line in the safe operating area curve is the drain current curve limited by on-resistance.
• Unless otherwise specified, TA = 25 °C, Single pulse
STR-A6131 / 31M
STR-A6151 / 51M
10
10
0.1ms
Drain Current, ID (A)
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Drain Current, ID (A)
0.1ms
1
1ms
0.1
0.01
1
1ms
0.1
0.01
1
10
100
1000
1
10
100
STR-A6159 / 59M
STR-A6169
10
10
0.1ms
0.1ms
Drain Current, ID (A)
Drain Current, ID (A)
1000
Drain-to-Source Voltage (V)
Drain-to-Source Voltage (V)
1
1ms
0.1
0.01
1
1ms
0.1
0.01
1
10
100
1000
Drain-to-Source Voltage (V)
1
10
100
1000
Drain-to-Source Voltage (V)
ot
STR-A6153E
10
Drain Current, ID (A)
N
0.1ms
1
1ms
0.1
0.01
1
10
100
1000
Drain-to-Source Voltage (V)
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
6
STR-A6100 Series
3.3 Ambient Temperature versus Power Dissipation, PD1 Curves
1.6
1.2
1
0.8
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Power Dissipation, PD1 (W)
1.4
0.6
0.4
0.2
0
0
25
50
75
100
125
150
Ambient Temperature, TA (°C )
3.4 Internal Frame Temperature versus Power Dissipation, PD2 Curves
• STR-A61××
• STR-A61××M
• STR-A6153E
0.50
0.14
0.45
PD2 = 0.15 W
Power Dissipation, PD2 (W)
Power Dissipation, PD2 (W)
0.16
0.12
0.10
0.08
0.06
0.04
0.02
PD2 = 0.46 W
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.00
0
20
40
60
80
100 120 140
0
25
50
75
100
125
150
Internal Frame Temperature, TF (°C)
N
ot
Internal Frame Temperature, TF (°C)
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
7
STR-A6100 Series
3.5 Transient Thermal Resistance Curves
• STR-A6131 / 31M
10
1
0.1
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Transient Thermal Resistance
θch-c (°C/W)
100
0.01
1µ
10µ
100µ
10µ
100µ
1m
Time (s)
10m
100m
1
10
1m
10m
100m
1
10
• STR-A6151 / 51M
Transient Thermal
Resistance θch-c (°C/W)
100
10
1
0.1
0.01
1µ
Time (s)
• STR-A6159 / 59M
1
0.1
0.01
ot
Transient Thermal Resistance
θch-c (°C/W)
10
10µ
100µ
1m
10m
100m
1m
10m
100m
Time (s)
N
1µ
• STR-A6169
Transient Thermal Resistance
θch-c (°C/W)
10
1
0.1
0.01 1µ
10µ
100µ
Time (s)
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
8
STR-A6100 Series
• STR-A6153E
1
0.1
0.01
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Transient Thermal Resistance
θch-c (°C/W)
10
0.001
1µ
10µ
100µ
1m
10m
100m
N
ot
Time (s)
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
9
STR-A6100 Series
4. Block Diagram
STR-A61××
2 VCC
ST
5
OVP
UVLO
＋
－
Internal
Bias
＋
－
Latch
Delay
TSD
7,8
D
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Power
MOS FET
OFF Timer
Drive
PWM Latch
＋
OLP
S Q
R
Bias
＋
－
－
－
＋
Burst
Blanking
＋
－
Discharge
FB
－
OCP
1
S/OCP
＋
－
＋
Buffer
3
GND
FB/OLP
4
STR-A61××M
2
ST
5
OVP
UVLO
＋
－
VCC
＋
－
Internal
Bias
Latch
Delay
TSD
Power
MOS FET
OFF Timer
7,8
D
Drive
PWM Latch
＋
OLP
S Q
R
＋
－
Burst
N
ot
－
Blanking
＋
－
Discharge
FB
－
OCP
1
S/OCP
＋
－
＋
Buffer
FB/OLP
3
GND
4
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
10
STR-A6100 Series
STR-A6153E
2
ST
5
OVP
UVLO
＋
－
Internal
Bias
＋
－
VCC
Latch
Delay
TSD
Power
MOS FET
OFF Timer
7,8
D
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Drive
PWM Latch
＋
－
OLP
S Q
R
＋
－
Burst
Blanking
＋
－
Discharge
FB
－
OCP
1
S/OCP
＋
－
＋
Buffer
FB/OLP
3
GND
4
5. Pin Configuration Definitions
● DIP7
S/OCP
VCC
GND
FB/OLP
1
8
D
2
7
D
3
6
4
5
ST
Pin
Name
1
S/OCP
2
VCC
3
GND
4
FB /OLP
5
ST
6
−
(Pin removed)
D
Power MOSFET drain
7
ot
8
● DIP8
S/OCP
1
8
D
VCC
2
7
D
3
GND
GND
3
6
NC
4
FB /OLP
FB/OLP
4
5
ST
5
ST
Descriptions
MOSFET source and input of overcurrent
protection (OCP) signal
Power supply voltage input for control part and
input of overvoltage protection (OVP) signal
Ground
Input of constant voltage control signal and
input of over load protection (OLP) signal
Startup current input
6
NC
−
N
Pin
Name
1
S/OCP
2
VCC
Descriptions
MOSFET source and input of overcurrent
protection (OCP) signal
Power supply voltage input for control part and
input of overvoltage protection (OVP) signal
Ground
Input of constant voltage control signal and
input of over load protection (OLP) signal
Startup current input
7
8
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
D
Power MOSFET drain
SANKEN ELECTRIC CO.,LTD.
11
STR-A6100 Series
6. Typical Application
• The PCB traces of D pins should be as wide as possible, in order to enhance thermal dissipation.
• In applications having a power supply specified such that VDS has large transient surge voltages, a clamp snubber
circuit of a capacitor-resistor-diode (CRD) combination should be added on the primary winding P, or a damper
snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the D pin and
the S/OCP pin.
• As shown in Figure 6-2, STR-A6153E does not need diode connected to ST pin.
CRD clamp snubber
BR1
L1
D51
T1
VOUT
(+)
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
VAC
R54
R51
R1
C6
C1
PC1
P
DST
D1
D2
8
D
D
C5
R52
S
C52
R53
U51
ST
NC
C53
R2
5
7
R55
C51
C2
U1
R56
D
(-)
STR-A61××
STR-A61××M
GND
S/OCP VCC GND FB/OLP
C（RC）
Damper snubber
1
2
3
4
CY
DZ1
ROCP
C3
PC1
C4
Figure 6-1 Typical application (STR-A61××/ STR-A61××M)
CRD clamp snubber
BR1
L1
D51
T1
VAC
VOUT
(+)
R54
R51
R1
C6
C1
PC1
P
R55
C51
ot
D1
N
D2
8
C5
D
C52
U51
ST
NC
R52
C2
U1
C53
R53
R2
5
7
D
S
D
R56
(-)
GND
STR-A6153E
S/OCP VCC GND FB/OLP
C（RC）
Damper snubber
1
2
3
4
CY
DZ1
ROCP
C3
PC1
C4
Figure 6-2 Typical application (STR-A6153E)
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
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STR-A6100 Series
7. Physical Dimensions
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• DIP7 (Type A)
NOTES:
5) Dimension is in millimeters
6) Pb-free. Device composition compliant with the RoHS directive
• DIP7 (Type B)
NOTES:
3) Dimension is in millimeters
4) Pb-free. Device composition compliant with the RoHS directive
N
ot
• DIP8
NOTES:
1) Dimension is in millimeters
2) Pb-free. Device composition compliant with the RoHS directive
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
13
STR-A6100 Series
8. Marking Diagram
• STR-A6131/51/59/69/31M/59M/51E
8
Part Number
S KY MD
(A61xx / A6153E A6131M / A6159M)
Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N, or D)
D is a period of days:
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10–11 days of the month (21st to 31st)
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1
Control Number
• STR-A6151M
8
A6151
Part Number
S KY MD M
1
Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N, or D)
D is a period of days:
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10–11 days of the month (21st to 31st)
N
ot
Control Number
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
14
STR-A6100 Series
9. Operational Description
• All of the parameter values used in these descriptions
are typical values of STR-A6151, unless they are
specified as minimum or maximum.
• With regard to current direction, "+" indicates sink
current (toward the IC) and "–" indicates source
current (from the IC).
The approximate value of auxiliary winding voltage is
about 15 V to 20 V, taking account of the winding turns
of D winding so that VCC pin voltage becomes
Equation (2) within the specification of input and output
voltage variation of power supply.
VCC ( BIAS) (max .) < VCC < VCC ( OVP ) (min .)
⇒ 11.6(V) < VCC < 28.7(V)
(1)
9.1 Startup Operation
The startup time of IC is determined by C2 capacitor
value. The approximate startup time tSTART is
calculated as follows:
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Figure 9-1 shows the circuit around VCC pin. Figure
9-2 shows VCC pin voltage behavior during the startup
period.
BR1
t START = C2 ×
T1
VCC ( ON )－VCC ( INT )
I STRATUP
(2)
VAC
C1 P
DST
where,
tSTART
VCC(INT)
5
U1
ST
VCC
2
D2
Figure 9-1.
R2
9.2 Undervoltage Lockout (UVLO)
C2
GND
3
Figure 9-3 shows the relationship of VCC pin voltage
and circuit current ICC. When VCC pin voltage
increases to VCC(ON) = 17.5 V, the control circuit starts
switching operation and the circuit current ICC increases.
When VCC pin voltage decreases to VCC(OFF) = 10 V, the
control circuit stops operation by UVLO (Undervoltage
Lockout) circuit, and reverts to the state before startup.
VD
D
VCC pin peripheral circuit
VCC pin voltage IC starts operation
Startup success
Target operating
voltage
VCC(ON)
VCC(OFF)
: Startup time of IC (s)
: Initial voltage on VCC pin (V)
Circuit current, ICC
ICC（ON）
Increase with rising of
output voltage
Stop
N
ot
Startup failure
Figure 9-2.
Time
VCC pin voltage during startup period
The IC incorporates the startup circuit. The circuit is
connected to ST pin. During the startup process, the
constant current, ISTARTUP = − 790 µA, charges C2 at
VCC pin. When VCC pin voltage increases to
VCC(ON) = 17.5 V, the IC starts the operation. Then
circuit current increases and VCC pin voltage decreases.
Since the Operation Stop Voltage VCC(OFF) = 10 V is low,
the auxiliary winding voltage reaches to setting value
before VCC pin voltage decreases to VCC(OFF). Thus
control circuit continues the operation. The voltage from
the auxiliary winding D in Figure 9-1 becomes a power
source to the control circuit in operation.
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
Start
VCC（OFF）
VCC（ON） VCC pin
voltage
Figure 9-3. Relationship between
VCC pin voltage and ICC
9.3 Constant Output Voltage Control
Figure 9-4 shows FB/OLP pin peripheral circuit,
Figure 9-5 shows the waveform of ID and FB
comparator input.
The IC achieves the constant voltage control of the
power supply output by PRC (Pulse Ratio Control). PRC
SANKEN ELECTRIC CO.,LTD.
15
STR-A6100 Series
controls on-time with fixed off-time. In addition, the IC
uses the peak-current-mode control method, which
enhances the response speed and provides the stable
operation.
D
Timer reset
OFF signal
output
OFF
Timer
Circuit
7,8
Drive
S
Gate
control
Q
PRC latch circuit
When load conditions become lighter, the output
voltage, VOUT, increases. Thus, the feedback current
from the error amplifier on the secondary-side also
increases. The feedback current is sunk at the FB/OLP
pin, transferred through a photo-coupler, PC1, and the
FB/OLP pin voltage decreases. Thus, VSC decreases,
and the peak value of VOCPM is controlled to be low,
and the peak drain current of ID decreases.
This control prevents the output voltage from
increasing.
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VSC
-V
+ OCPM
FB Comp.
Buffer
S/OCP
+
-
OCP Comp.
U1
The IC controls the peak value of VOCPM voltage to be
close to target voltage (VSC), comparing VOCPM with VSC
by internal FB comparator.
VOCPM is amplified VROCP voltage that is a detection
voltage by current detection resistor, ROCP.
• Light load conditions
R
ON/OFF
is latched to High. As a result, turn-off signal is input
to the gate control circuit, and power MOSFET turns
off.
1
VOCP(TH)
ID
• Heavy load conditions
3
4
GND
FB/OLP
VROCP
IFB
ROCP
DZ1
C4
Figure 9-4.
C3
PC1
FB/OLP pin peripheral circuit
VSC
+
VOCPM
9.4 Leading Edge Blanking Function
The constant voltage control of output of the IC uses
the peak-current-mode control method.
In peak-current-mode control method, there is a case
that the power MOSFET turns off due to unexpected
response of FB comparator or overcurrent protection
circuit (OCP) to the steep surge current in turning on a
power MOSFET.
In order to prevent this operation, Leading Edge
Blanking Time, tBW = 320 ns is built-in.
In the period of tBW, the IC does not respond to the
surge voltage in turning on the power MOSFET.
FB comparator
-
When load conditions become greater, the IC
performs the inverse operation to that described above.
Thus, VSC increases and the peak drain current of ID
increases.
This control prevents the output voltage from
decreasing.
ot
Drain current, ID
N
Figure 9-5.
The waveform of ID and FB comparator
input
9.5 Auto Standby Function
The internal fixed off-time, tOFF is made from internal
off timer circuit, the turn-on timing of power MOSFET
depends on tOFF.
• Turn-on
After the period of tOFF, OFF signal output becomes
High, Q of PRC latch circuit is latched to Low. As a
result, turn-on signal is input to the gate control circuit,
and power MOSFET turns on.
• Tuen-off
When the OCP comparator or the FB comparator
resets the PRC latch circuit, Q of PRC latch circuit
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
Automatic standby mode is activated automatically
when the drain current, ID, reduces under light load
conditions, at which ID is less than 25% of the maximum
drain current (it is in the Overcurrent Protection state).
The operation mode becomes burst oscillation, as shown
in Figure 9-6. The 25% of the maximum drain current
corresponds to the Burst Threshold Voltage of FB/OLP
pin, VBURST = 0.79 V (0.75 V for STR-A61××M and
STR-A6153E).
Burst oscillation mode reduces switching losses and
improves power supply efficiency because of periodic
non-switching intervals.
Generally, to improve efficiency under light load
SANKEN ELECTRIC CO.,LTD.
16
STR-A6100 Series
conditions, the frequency of the burst mode becomes
just a few kilohertz. Because the IC suppresses the peak
drain current well during burst mode, audible noises can
be reduced.
Output current,
IOUT
input voltage is, the larger the actual peak of drain
current is. As a result, the detection voltage becomes
higher than VOCP(TH). Thus, the output current depends
on the AC input voltage in OCP operation (refer to
Figure 9-7).
Low AC
input voltage
High AC
input voltage
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Below several kHz
Output voltage, VOUT（V）
Burst oscillation
Drain current,
ID
Normal
operation
Standby
operation
Normal
operation
Output current, IOUT（A）
Figure 9-6.
Auto Standby mode timing
Figure 9-7.
9.6 Auto Bias Function (STR-A61xx)
STR-A61xx includes the auto bias function. The
function becomes active during burst oscillation mode.
When VCC pin voltage decreases to the Auto Bias
Threshold Voltage, VCC(BIAS) = 10.6 V, during burst
oscillation mode, the IC shifts to PRC operation so that
VCC pin voltage does not decrease. As a result, the IC
achieves stable standby operation.
However, if the Bias Assist function is always
activated during steady-state operation including
standby mode, the power loss increases. Therefore, the
VCC pin voltage should be more than VCC(BIAS), for
example, by adjusting the turns ratio of the auxiliary
winding and secondary winding and/or reducing the
value of R2 in Figure 10-2 (refer to Section 10.1
Peripheral Components for a detail of R2).
9.7 Overcurrent Protection Function (OCP)
N
ot
Overcurrent Protection Function (OCP) detects each
drain peak current level of a power MOSFET on
pulse-by-pulse basis, and limits the output power when
the current level reaches to OCP threshold voltage,
VOCP(TH) = 0.77 V (1.13 V for STR-A61××M and
STR-A6153E).
Figure 9-7 shows the output characteristics. When
OCP becomes active, the output voltage decreases and
the auxiliary winding voltage, VD decreases in
proportion to the output voltage.
When VCC pin voltage decreases to VCC(OFF) = 10 V,
the control circuit stops operation by UVLO circuit, and
reverts to the state before startup. After that, VCC pin
voltage is increased by Startup Current, ISTARTUP. When
VCC pin voltage increases to VCC(ON) = 17.5 V, the IC
restarts the operation. Thus the intermittent operation by
UVLO is repeated in OCP operation.
The IC usually has some propagation delay time. The
steeper the slope of the actual drain current at a high AC
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
Output characteristic curve
When the multi outputs transformer is used, there is the
case that the auxiliary winding voltage, VD does not
decrease and the intermittent operation is not started,
even if output voltage decreases in OCP operation. This
is due to the poor coupling of transformer. In this case,
the overload protection (OLP) becomes active. (refer to
Section 9.8.)
9.8 Overload Protection (OLP)
Figure 9-8 shows the FB/OLP pin peripheral circuit.
Figure 9-9 shows the OLP operational waveforms.
When the peak drain current of ID is limited by OCP
operation, the output voltage, VOUT, decreases and the
feedback current from the secondary photo-coupler
becomes zero. Thus, the feedback current, IFB, charges
C3 connected to the FB/OLP pin and the FB/OLP pin
voltage increases. When the FB/OLP pin voltage
increases to VFB(OLP) = 7.2 V or more for the OLP delay
time, tDLY or more, the OLP function is activated and the
IC stops switching operation. tDLY is calculated using
Equation (3).
t DLY = C4 ×
(VOLP − VZ )
(3)
I OLP
there,
tDLY: OLP delay time
VZ: zener voltage of zener diode, DZ1
IOLP: FB/OLP Pin Source Current in OLP Operation is
− 26 µA
After the switching operation stops, VCC pin voltage
decreases to Operation Stop Voltage VCC(OFF) = 10 V and
the intermittent operation by UVLO is repeated.
This intermittent operation reduces the stress of parts
such as power MOSFET and secondary side rectifier
SANKEN ELECTRIC CO.,LTD.
17
STR-A6100 Series
diode. In addition, this operation reduces power
consumption because the switching period in this
intermittent operation is short compared with oscillation
stop period. When the abnormal condition is removed,
the IC returns to normal operation automatically.
As shown in Figure 9-9, tDLY should be longer than
tSTART which is the period until the output voltage
becomes constant. If tDLY is shorter than tSTART, the
power supply may not start due to OLP operation.
Releasing the latched state is done by turning off the
input voltage and by dropping the VCC pin voltage
below VCC(La.OFF) = 7.3 V.
VCC pin voltage
Latched state
VCC（OVP）=31.2V
VCC（ON）=17.5V
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U1
S/OCP
VCC（OFF）=10V
GND FB/OLP
1
3
4
DZ1
VROCP
PC1
ROCP
C4
Drain current,
ID
IFB
C3
Figure 9-10.
Figure 9-8.
FB/OLP pin peripheral circuit
tSTART
tSTART
tDLY
tDLY
VCC pin voltage
VCC(ON)
VCC(OFF)
FB/OLP pin voltage
Non-switching interval
Drain current,
ID
Figure 9-9.
If output voltage detection circuit becomes open, the
output voltage of secondary side increases. In case the
VCC pin voltage is provided by using auxiliary winding
of transformer, the overvoltage conditions can be
detected because the VCC pin voltage is proportional to
output voltage. The approximate value of output voltage
VOUT(OVP) in OVP condition is calculated by using
Equation (4).
VOUT(OVP) =
VOLP
OVP operational waveforms
VOUT ( NORMAL)
VCC ( NORMAL)
× 31.2
(4)
where,
VOUT(NORMAL): Output voltage in normal operation
VCC(NORMAL): VCC pin voltage in normal operation
OLP operational waveforms
9.10 Thermal Shutdown Function (TSD)
ot
9.9 Overvoltage Protection (OVP)
N
Figure 9-10 shows the OVP operational waveforms.
When a voltage between VCC pin and GND terminal
increases to VCC(OVP) = 31.2 V or more, OVP function is
activated. When the OVP function is activated, the IC
stops switching operation at the latched state.
After that, VCC pin voltage is decreased by circuit
current of IC. When VCC pin voltage becomes
VCC(OFF) = 10 V or less, VCC pin voltage is increased by
Startup Current. When VCC pin voltage increases to
VCC(ON) = 17.5 V, the circuit current increases and VCC
pin voltage decreases. In this way, VCC pin voltage
goes up and down between VCC(OFF) and VCC(ON) during
the latched state, excessive increase of VCC pin voltage
is prevented.
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
When the temperature of control circuit increases to
Tj(TSD) = 135 °C or more, Thermal Shutdown function
is activated. When the TSD function is activated, the IC
stops switching operation at the latched state (see the
Section 9.9). Releasing the latched state is done by
turning off the input voltage and by dropping the VCC
pin voltage below VCC(La.OFF) = 7.3 V.
SANKEN ELECTRIC CO.,LTD.
18
STR-A6100 Series
10.Design Notes
Without R2
VCC pin voltage
10.1 External Components
Take care to use properly rated, including derating as
necessary and proper type of components.
Output current, IOUT
CRD clamp snubber
BR1
T1
VAC
(
C6
RST
With R2
Figure 10-2.
R1
Variation of VCC pin voltage and power
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DST
8
D
D2
5
7
D
P
D1
)
C1
R2
ST
NC
U1
C5
C2
STRA6100
D
S/OCP VCC GND FB/OLP
C（RC）
damper snubber
1
2
3
4
DZ1
C3
ROCP
PC1
C4
Figure 10-1.
The IC peripheral circuit
Electrolytic Capacitor
Apply proper derating to ripple current, voltage, and
temperature rise. Use of high ripple current and low
impedance types, designed for switch mode power
supplies, is recommended.
S/OCP Pin Peripheral Circuit
Choose a type of low internal inductance because a
high frequency switching current flows to ROCP in
Figure 10-1, and of properly allowable dissipation.
N
ot
VCC Pin Peripheral Circuit
The value of C2 in Figure 10-1 is generally
recommended to be 10µ to 47μF (refer to Section 9.1,
because the startup time is determined by the value of
C2). In actual power supply circuits, there are cases in
which the VCC pin voltage fluctuates in proportion to
the output current, IOUT (see Figure 10-2), and the
Overvoltage Protection function (OVP) on the VCC
pin may be activated. This happens because C2 is
charged to a peak voltage on the auxiliary winding D,
which is caused by the transient surge voltage coupled
from the primary winding when the power MOSFET
turns off. For alleviating C2 peak charging, it is
effective to add some value R2, of several tenths of
ohms to several ohms, in series with D2 (see Figure
10-1). The optimal value of R2 should be determined
using a transformer matching what will be used in the
actual application, because the variation of the
auxiliary winding voltage is affected by the
transformer structural design.
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
FB/OLP Pin Peripheral Circuit
Figure 10-1 performs high frequency noise rejection
and phase compensation, and should be connected
close to these pins. The value of C3 is recommended
to be about 2200p to 0.01µF.
In order to make the value of C3 low and make the
output response fast, DZ1 and C4 are connected.
DZ1 prevents C4 charging in normal operation. The
zener voltage of DZ1, VZ should be set higher than
FB/OLP pin voltage in normal operation. Usually, the
value of VZ is about 4.7 V to 5.6 V.
C4 is for OLP delay time, tDLY setting. If C4 is too
small, the power supply may not start due to OLP
operation (see Section 9.8). The value of C4 is about
4.7 μF to 22 μF.
C3, C4 and DZ1 should be selected based on actual
operation in the application.
ST Pin Peripheral Circuit
When STR-A61×× and STR-A61××M are used, DST
or RST should be connected to ST pin as shown in
Figure 10-1. DST and RST prevent negative voltage
from applying to ST pin. If ST pin voltage becomes
under −0.3 V, the power supply may not start. The
value of DST and RST should be selected based on
actual operation in the application.
Recommended value of RST is 33 kΩ,
Recommended characteristics of DST is as follows:
Characteristics
Peak Reverse Voltage, VRM
Forward current, IF
Reverse Recovery Time, trr
Reverse Leakage Current, IR
Recommended range
> 35 V
> 1.5 mA
< 27 μs
< 100 μA
Snubber Circuit
In case the serge voltage of VDS is large, the circuit
should be added as follows (see Figure 10-1);
・ A clamp snubber circuit of a capacitor-resistordiode (CRD) combination should be added on the
primary winding P.
・ A damper snubber circuit of a capacitor (C) or a
resistor-capacitor (RC) combination should be
added between the D pin and the GND pin.
In case the damper snubber circuit is added, this
components should be connected near D pin and
S/OCP pin.
SANKEN ELECTRIC CO.,LTD.
19
STR-A6100 Series
Phase Compensation
A typical phase compensation circuit with a
secondary shunt regulator (U51) is shown in Figure
10-3.
C52 and R53 are for phase compensation. The value
of C52 and R53 are recommended to be around 0.047
μF to 0.47 μF and 4.7 kΩ to 470 kΩ, respectively.
They should be selected based on actual operation in
the application.
VOUT
(+)
R55
C51
R52
C53
C52 R53
U51
R56
(-)
Figure 10-3.
Peripheral circuit around secondary shunt
regulator (U51)
N
ot
• Transformer
Apply proper design margin to core temperature rise
by core loss and copper loss.
Because the switching currents contain high
frequency currents, the skin effect may become a
consideration.
Choose a suitable wire gauge in consideration of the
RMS current and a current density of 4 to 6 A/mm2.
If measures to further reduce temperature are still
necessary, the following should be considered to
increase the total surface area of the wiring:
▫ Increase the number of wires in parallel.
▫ Use litz wires.
▫ Thicken the wire gauge.
In the following cases, the surge of VCC pin
voltage becomes high.
▫ The surge voltage of primary main winding, P, is
high (low output voltage and high output current
power supply designs)
▫ The winding structure of auxiliary winding, D, is
susceptible to the noise of winding P.
Winding structural example (b)
P1 and P2 are placed close to S1 to maximize the
coupling of S1 for surge reduction of P1 and P2.
D and S2 are sandwiched by S1 to maximize the
coupling of D and S1, and that of S1 and S2.
This structure reduces the surge of D, and
improves the line-regulation of outputs.
Margin tape
Bobbin
PC1
Figure 10-4 shows the winding structural examples
of two outputs.
Winding structural example (a):
S1 is sandwiched between P1 and P2 to
maximize the coupling of them for surge
reduction of P1 and P2.
D is placed far from P1 and P2 to minimize the
coupling to the primary for the surge reduction of
D.
R54
R51
P1 S1 P2 S2 D
Margin tape
Winding structural example (a)
Margin tape
Bobbin
D51
S
In the case of multi-output power supply, the
coupling of the secondary-side stabilized output
winding, S1, and the others (S2, S3…) should be
maximized to improve the line-regulation of those
outputs.
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L51
T1
▫ The coupling of the winding P and the secondary
output winding S should be maximized to reduce the
leakage inductance.
▫ The coupling of the winding D and the winding S
should be maximized.
▫ The coupling of the winding D and the winding P
should be minimized.
P1 S1
D S2 S1 P2
Margin tape
Winding structural example (b)
Figure 10-4.
Winding structural examples
When the surge voltage of winding D is high, the
VCC pin voltage increases and the Overvoltage
Protection function (OVP) may be activated. In
transformer design, the following should be
considered;
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
20
STR-A6100 Series
10.2 PCB Trace Layout and Component
Placement
(7) Thermal Considerations
Because the power MOSFET has a positive thermal
coefficient of RDS(ON), consider it in thermal design.
Since the copper area under the IC and the D pin
trace act as a heatsink, its traces should be as wide as
possible.
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Since the PCB circuit trace design and the component
layout significantly affects operation, EMI noise, and
power dissipation, the high frequency PCB trace should
be low impedance with small loop and wide trace.
In addition, the ground traces affect radiated EMI
noise, and wide, short traces should be taken into
account.
Figure 10-5 shows the circuit design example.
MOSFET. Proper rectifier smoothing trace layout
helps to increase margin against the power MOSFET
breakdown voltage, and reduces stress on the clamp
snubber circuit and losses in it.
(1) Main Circuit Trace Layout: S/OCP pin to ROCP to C1
to T1 (winding P) to D pin
This is the main trace containing switching currents,
and thus it should be as wide trace and small loop as
possible. If C1 and the IC are distant from each other,
placing a capacitor such as film capacitor (about 0.1
μF and with proper voltage rating) close to the
transformer or the IC is recommended to reduce
impedance of the high frequency current loop.
(2) Control Ground Trace Layout
Since the operation of IC may be affected from the
large current of the main trace that flows in control
ground trace, the control ground trace should be
separated from main trace and connected at a single
point grounding of point A in Figure 10-5 as close
to the ROCP pin as possible.
(3) VCC Trace Layout: GND pin to C2 (negative) to T1
(winding D) to R2 to D2 to C2 (positive) to VCC pin
This is the trace for supplying power to the IC, and
thus it should be as small loop as possible. If C2 and
the IC are distant from each other, placing a
capacitor such as film capacitor Cf (about 0.1 μF to
1.0 μF) close to the VCC pin and the GND pin is
recommended.
(4) ROCP Trace Layout
N
ot
ROCP should be placed as close as possible to the
S/OCP pin. The connection between the power
ground of the main trace and the IC ground should
be at a single point ground (point A in Figure
10-5) which is close to the base of ROCP.
(5) FB/OLP Trace Layout
The components connected to FB/OLP pin should be
as close to FB/OLP pin as possible. The trace
between the components and FB/OLP pin should be
as short as possible.
(6) Secondary Rectifier Smoothing Circuit Trace
Layout: T1 (winding S) to D51 to C51
This is the trace of the rectifier smoothing loop,
carrying the switching current, and thus it should be
as wide trace and small loop as possible. If this trace
is thin and long, inductance resulting from the loop
may increase surge voltage at turning off the power
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
21
STR-A6100 Series
(1) Main trace should be wide
trace and small loop
(6) Main trace of secondary side should
be wide trace and small loop
D51
T1
R1
C6
C1
P
DST
(7)Trace of D pin should be wide
for heat release
C51
D1
R
ec
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, S fo
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61 D
31 es
M ign
s:
S
8
5
7
D
C5
D
D2
NC
R2
ST
U1
STR-A6100
C2
D
S/OCP VCC GND FB/OLP
1
2
3
4
(3) Loop of the power
supply should be small
ROCP
DZ1
C4
PC1
C3
(5)The components connected to
FB/OLP pin should be as close
to FB/OLP pin as possible
A
(4)ROCP should be as close to S/OCP pin as
possible.
CY
(2) Control GND trace should be connected at a
single point as close to the ROCP as possible
Example of peripheral circuit around the IC
N
ot
Figure 10-5.
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
22
STR-A6100 Series
11.Pattern Layout Example
The following show the PCB pattern layout example and the circuit schematic with STR-A6100 series (DIP7).
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
TR r N
-A ew
61 D
31 es
M ign
s:
Top view
Bottom view
Figure 11-1 PCB circuit trace layout example
J1
F1
L1
D1
R1
ZNR1
R2
C1
R13
R91 R92 R93
ot
D4
N
J2
R11
C91
C2
L2
D11
T1
D91
PC1
R12
C11
P
R14
S
D2
8
C12
C13
R16
5
7
D
R9
D
C14
ST
NC
C4
U1
D
IC2
R15
STR-A61××
STR-A61××M
S/OCP VCC GND FB/OLP
1
2
3
4
C99
D3
C3
C8
PC1
C5
R3 R4 R5 R6
Figure 11-2 Circuit schematic for PCB circuit trace layout
The above circuit symbols correspond to these of Figure 11-1.
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
23
STR-A6100 Series
12.Reference Design of Power Supply
As an example, the following show the power supply specification, the circuit schematic, the bill of materials, and
the transformer specification.
• Power supply specification
IC
Input voltage
Maximum output power
STR-A6159
Output
5V/1A
AC 85 V to AC 265 V
5W
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M ign
s:
• Circuit schematic
Refer to Figure 11-2
• Bill of materials
Symbol
F1
L1
ZNR1
D1
D2
D3
D4
D91
C1
C2
C3
C4
C5
C8
C91
C99
R1
R2
R3
N
R5
Ratings(1)
Recommended
Sanken Parts
AC 250 V,
500 mA
Symbol
General, chip
0 Ω, 1/4 W
R91
Metal oxide, chip
270 kΩ, 1/4 W
AM01A (Axial)
R92
Metal oxide, chip
270 kΩ, 1/4 W
AL01Z
R93
Metal oxide, chip
270 kΩ, 1/4 W
5.1 V
PC1
Photo-coupler
PC123 or equiv
General, chip
200 V, 1 A
IC1
IC
Fast recovery
1000 V, 0.2 A
－
See
the specification
Film
0.15 μF, 270 V
Electrolytic
22 μF, 450 V
Ceramic, chip
4700 pF, 50 V
Electrolytic
22 μF, 50 V
C12
Electrolytic
2.2 μF, 50 V
C13
Ceramic, chip
0.33 μF, 50 V
C14
CM inductor
16.5 mH
R9
(2)
Varistor
Open
General
600 V, 1 A
Fast recovery
200 V, 1 A
Zener, chip
(2)
Ratings(1)
10 Ω, 1/4 W
R6
(2)
(2)
Part type
General, chip
Fuse
EG01C
(2)
T1
Transformer
Inductor
2.2 μF
D11
Schottky, chip
60 V, 2 A
C11
Electrolytic
680 μF, 10 V
Electrolytic
220 μF, 10 V
L2
(2)
(2)
Ceramic, chip
0.1 μF, 50 V
Ceramic, chip
Open
Ceramic, chip
1000 pF, 630 V
R11
General, chip
220 Ω, 1/8 W
(2)
Ceramic, Y1
2200 μF,
AC 250 V
R12
General, chip
1.5 kΩ, 1/8 W
(2)
General, chip
Open
R13
(2)
General, chip
Open
R14
General, chip, 1% 10 kΩ, 1/8 W
General, chip
10 Ω, 1/4 W
R15
General, chip, 1% 10 kΩ, 1/8 W
General, chip
10 Ω, 1/4 W
R16
General, chip
47kΩ, 1/8 W
General, chip
10 Ω, 1/4 W
IC2
Shunt regulator
VREF = 2.5 V
TL431 or equiv
ot
R4
Part type
(2)
Recommended
Sanken Parts
STR-A6159
SJPB-H6
General, chip, 1% 0 Ω, 1/8 W
(1)
Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less.
It is necessary to be adjusted based on actual operation in the application.
(3)
Resistors applied high DC voltage and of high resistance are recommended to select resistors designed against electromigration or use
combinations of resistors in series for that to reduce each applied voltage, according to the requirement of the application.
(2)
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
24
STR-A6100 Series
• Transformer specification
▫ Primary inductance, LP
▫ Core size
▫ Al-value
▫ Winding specification
: 3.1 mH
: EI-16
: 114 nH/N2 (Center gap of about 0.188 mm)
Symbol
Number of
turns (T)
Primary winding
P1
66
φ 0.18 UEW
Primary winding
P2
99
φ 0.18 UEW
Wire diameter (mm)
Construction
Double-layer,
solenoid winding
Triple-layer,
solenoid winding
Solenoid winding
Solenoid winding
φ 0.18 UEW
φ 0.4 × 3 TIW
R
ec
ST om
R m
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61 nd
31 ed
, S fo
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31 es
M ign
s:
Winding
Auxiliary winding
Output
D
S1
29
11
5V
VOUT(+)
VDC
P1
P2
D
S1
P1
Bobbin
S1
P2
VOUT(-)
D
VCC
D
GND
: Start at this pin
N
ot
Cross-section view
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
25
STR-A6100 Series
Important Notes
N
ot
R
ec
ST om
R m
-A e
61 nd
31 ed
, S fo
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31 es
M ign
s:
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DSGN-CEZ-16002
STR-A6100 - DS Rev.2.2
Oct. 06, 2016
SANKEN ELECTRIC CO.,LTD.
26
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