STR-Y6766A

Quasi-Resonant Controllers with Integrated Power MOSFET STR-Y6700 Series General Descriptions Package The STR-Y6700 series are power ICs for switching power supplies, incorporating a MOSFET and a quasi-resonant controller IC. Including an auto standby function in the controller, the product achieves the low standby power by the automatic switching between the quasi-resonant operation in normal operation, one bottom-skip operation under medium to light load conditions and the burst-oscillation under light load conditions. The product achieves high cost-performance power supply systems with few external components. TO220F-7L Features Lineup • Electrical Characteristics The optimum operation depending on load conditions is changed automatically and is achieved high efficiency operation across the full range of loads. ew fo rN STR–Y6754 STR–Y6766 STR–Y6766A STR–Y6765 STR–Y6763 STR–Y6763A de d en R ec om m • • • • Operation Mode Normal load ------------------------- Quasi-resonant mode Medium to light load -------------One bottom-skip mode Light load -------------------------- Burst oscillation mode (Auto standby function) No load power consumption PIN < 30 mW (100VAC) PIN < 50 mW (230VAC) Leading Edge Blanking Function Bias Assist Function Built-in startup circuit reduces Protections Overcurrent Protection 1 (OCP1): Pulse-by-Pulse, with Input Compensation Function Overcurrent Protection 2 (OCP2)(1): Latched shutdown Overload Protection (OLP): Latched shutdown Overvoltage Protection (OVP): Latched shutdown Thermal Shutdown Protection (TSD): Latched shutdown Products STR–Y6735 STR–Y6735A STR–Y6753 (1) Products with the last letter "A" don’t have the OCP2 function. ot N BR1 L51 D51 T1 RDS(ON)(max.) 500 V 0.8 Ω 650 V 1.9 Ω 1.4 Ω 1.7 Ω 800 V 2.2 Ω 3.5 Ω • Output Power, POUT(2) Products STR–Y6735 STR–Y6735A STR–Y6753 STR–Y6754 STR–Y6766 STR–Y6766A STR–Y6765 STR–Y6763 STR–Y6763A (2) Typical Application VDSS(min.) D • Multi-mode Control • es ig ns Not to Scale POUT (Open frame) 380VDC 85~265VAC 120 W(100VAC) – 100 W 60 W 120 W 67 W 140 W 80 W 120 W 70 W 80 W 50 W The output power is actual continues power that is measured at 50 °C ambient. The peak output power can be 120 to 140 % of the value stated here. Core size, ON Duty, and thermal design affect the output power. It may be less than the value stated here. VOUT(+) VAC P C1 PC1 Applications R55 C51 S R54 R51 R52 C53 U1 C52 R53 D2 STR-Y6700 C3 D/ST 2 S/OCP VCC GND FB/OLP BD NF 1 R2 U51 D R56 VOUT(-) • White goods • Office automation equipment • Industrial equipment DZBD 2 3 4 5 6 7 RBD1 R3 ROCP CBD C4 C5 RBD2 PC1 STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 CY SANKEN ELECTRIC CO., LTD. https://www.sanken-ele.co.jp/en/ 1 STR-Y6700 Series CONTENTS General Descriptions ------------------------------------------------------------------------------------------ 1 1. Absolute Maximum Ratings ----------------------------------------------------------------------------- 3 2. Electrical Characteristics -------------------------------------------------------------------------------- 4 3. Performance Curves -------------------------------------------------------------------------------------- 6 3.1 Derating Curves ------------------------------------------------------------------------------------ 6 3.2 Ambient Temperature versus Power Dissipation Curves ---------------------------------- 6 3.3 MOSFET Safe Operating Area Curves ------------------------------------------------------- 8 3.4 Transient Thermal Resistance Curves --------------------------------------------------------- 9 es ig ns 4. Block Diagram ------------------------------------------------------------------------------------------- 10 5. Pin Configuration Definitions ------------------------------------------------------------------------- 10 6. Typical Application ------------------------------------------------------------------------------------- 11 7. Physical Dimensions ------------------------------------------------------------------------------------ 12 D 8. Marking Diagram --------------------------------------------------------------------------------------- 12 R ec om m en de d fo rN ew 9. Operational Description ------------------------------------------------------------------------------- 13 9.1 Startup Operation ------------------------------------------------------------------------------- 13 9.2 Undervoltage Lockout (UVLO) --------------------------------------------------------------- 13 9.3 Bias Assist Function ----------------------------------------------------------------------------- 13 9.4 Soft Start Function ------------------------------------------------------------------------------ 14 9.5 Constant Output Voltage Control ------------------------------------------------------------ 15 9.6 Leading Edge Blanking Function ------------------------------------------------------------- 15 9.7 Quasi-Resonant Operation and Bottom-On Timing Setup ------------------------------ 15 9.7.1 Quasi-Resonant Operation ------------------------------------------------------------ 15 9.7.2 Bottom-On Timing Setup ------------------------------------------------------------- 16 9.8 BD Pin Blanking Time -------------------------------------------------------------------------- 17 9.9 Multi-mode Control ----------------------------------------------------------------------------- 18 9.9.1 One Bottom-Skip Quasi-Resonant Operation ------------------------------------- 18 9.9.2 Automatic Standby Mode Function ------------------------------------------------- 19 9.10 Maximum On-Time Limitation Function --------------------------------------------------- 19 9.11 Overcurrent Protection (OCP) ---------------------------------------------------------------- 20 9.11.1 Overcurrent Protection 1 (OCP1) --------------------------------------------------- 20 9.11.2 Overcurrent Protection 2 (OCP2) --------------------------------------------------- 20 9.11.3 OCP1 Input Compensation Function ----------------------------------------------- 20 9.11.4 When Overcurrent Input Compensation is Not Required ---------------------- 23 9.12 Overload Protection (OLP) -------------------------------------------------------------------- 23 9.13 Overvoltage Protection (OVP) ---------------------------------------------------------------- 24 9.14 Thermal Shutdown (TSD) ---------------------------------------------------------------------- 24 N ot 10. Design Notes ---------------------------------------------------------------------------------------------- 25 10.1 External Components --------------------------------------------------------------------------- 25 10.2 Transformer Design ----------------------------------------------------------------------------- 27 10.3 PCB Trace Layout and Component Placement -------------------------------------------- 28 11. Pattern Layout Example ------------------------------------------------------------------------------- 30 12. Reference Design of Power Supply ------------------------------------------------------------------ 31 Important Notes ---------------------------------------------------------------------------------------------- 33 STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 2 STR-Y6700 Series 1. Absolute Maximum Ratings • Current polarities are defined as follows: a current flow going into the IC (sinking) is positive current (+); and a current flow coming out of the IC (sourcing) is negative current (−). • Unless otherwise specified TA = 25 °C Parameter Symbol Test Conditions Pins Single pulse Ta= −20 to 125°C IDMAX ILPEAK=2.3A Avalanche Energy(3)(4) ILPEAK=2.9A EAS ILPEAK=3.2A 1–2 ILPEAK=4.1A de d ILPEAK=3.5A m en VSTARTUP VOCP VCC VFB IFB VBD R ec om D/ST Pin Voltage S/OCP Pin Voltage VCC Pin Voltage FB/OLP Pin Voltage FB/OLP Pin Sink Current BD Pin Voltage PD1 N Control Part Power Dissipation Internal Frame Temperature in Operation Operating Ambient Temperature Storage Temperature Junction Temperature V V V V mA V With infinite heatsink A 1−4 2–4 3–4 5–4 5–4 6–4 1–2 STR–Y6763 / 63A STR–Y6765 A −2.0 to 6.0 35 −0.3 to 7.0 10.0 − 6.0 to 6.0 19.9 21.8 20.2 23.6 STR–Y6766 / 66A STR–Y6735 / 35A STR–Y6763 / 63A STR–Y6765 mJ STR–Y6753 STR–Y6766 / 66A STR–Y6754 STR–Y6735 / 35A STR–Y6763 / 63A STR–Y6765 W STR–Y6753 STR–Y6766 / 66A STR–Y6735 / 35A STR–Y6754 W W TF − −40 to 115 °C TOP Tstg Tch − − − −40 to 115 −40 to 125 150 °C °C °C PD2 STR–Y6753 STR–Y6754 1.8 0.8 VCC×ICC STR–Y6766 / 66A STR–Y6735 / 35A 1–2 3–4 Without heatsink STR–Y6753 STR–Y6754 21.5 ot Power Dissipation(5) −1.0 to VDSS 1–2 fo rN ILPEAK=2.6A 1–2 STR–Y6765 es ig ns Maximum Switching Current(2) Single pulse Remarks STR–Y6763 / 63A D IDPEAK Units ew Drain Peak Current(1) Rating 6.7 8.9 9.2 10.5 11.0 14.6 6.7 8.9 9.2 10.5 11.0 14.6 60 77 99 116 198 152 (1) Refer to 3.3 MOSFET Safe Operating Area Curves The maximum switching current is the drain current determined by the drive voltage of the IC and threshold voltage (Vth) of the MOSFET. (3) Refer to Figure 3-2 Avalanche Energy Derating Coefficient Curve (4) Single pulse, VDD = 99 V, L = 20 mH (5) Refer to 3.2 TA-PD1curves. (2) STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 3 STR-Y6700 Series 2. Electrical Characteristics • The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC. • Unless otherwise specified, TA = 25 °C, VCC = 20 V Symbol Test Conditions Pins Min. Typ. Max. Units VCC(ON) 3−4 13.8 15.1 17.3 V VCC(OFF) 3−4 8.4 9.4 10.7 V ICC(ON) 3−4 − 1.3 3.7 mA 3−4 − 4.5 50 µA 1−4 42 57 72 V 3−4 − 4.5 − 3.1 − 1.0 mA VCC(BIAS) 3−4 9.5 fOSC 1−4 tSS 1−4 VOCP(BS1) fo rN Parameter Remarks Circuit Current in Operation Circuit Current in Non-Operation Startup Circuit Operation Voltage ICC(OFF) VCC = 13 V VSTART(ON) Startup Current ICC(STARTUP) Startup Current Biasing Threshold Voltage PWM Switching Frequency Soft Start Operation Duration VCC = 13 V Normal Operation Bottom-Skip Operation Threshold Voltage 1 Bottom-Skip Operation Threshold Voltage 2 Quasi-Resonant Operation Threshold Voltage 1 Quasi-Resonant Operation Threshold Voltage 2(2) Maximum On-Time Overcurrent Detection 1 Threshold Voltage in Input Compensation Operation Overcurrent Detection 1 Threshold Voltage in Normal Operation Overcurrent Detection 2 Threshold Voltage (1) (2) 21.0 24.4 kHz − 6.05 − ms 0.665 V 2−4 0.200 0.289 0.380 V VBD(TH1) 6−4 0.14 0.24 0.34 V VBD(TH2) 6−4 0.07 0.17 0.27 V IFB(MAX) 5−4 −320 −205 −120 µA VFB(STBOP) 5−4 0.45 0.80 1.15 V tON(MAX) 1−4 30.0 40.0 50.0 µs − 455 − de d 1−4 tON(LEB) N ot Leading Edge Blanking Time 18.4 0.572 en R ec Protected Operation V 0.487 om Standby Operation Threshold Voltage 12.5 m Standby Operation 11.0 2−4 VOCP(BS2) Maximum Feedback Current D Operation Stop Voltage (1) ew Operation Start Voltage es ig ns Power Supply Startup Operation ns − 470 − VOCP(L) VBD = –3V 2−4 0.560 0.660 0.760 V VOCP(H) VBD = 0V 2−4 0.820 0.910 1.000 V VOCP(La.OFF) 2−4 1.65 1.83 2.01 V STR–Y6735 / 35A/ 65/ 66/ 54 STR–Y6763 / 63A/ 53 Products without the last letter "A" VCC(OFF) < VCC(BIAS) always. VBD(TH2) < VBD(TH1) always. STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 4 STR-Y6700 Series Pins Min. Typ. Max. Units IBD(O) 6−4 − 250 − 83 − 30 µA OLP Bias Current IFB(OLP) 5−4 − 15 − 10 −5 µA OLP Threshold Voltage VFB(OLP) 5−4 5.50 5.96 6.40 V FB Pin Maximum Voltage in Feedback Operation VFB(MAX) 5−4 3.70 4.05 4.40 V OVP Threshold Voltage VCC(OVP) 3− 4 28.5 31.5 34.0 V Tj(TSD) − 135 − − °C 500 − − 650 − − 800 − − − − 300 − − 0.8 STR-Y6735 / 35A − − 1.4 STR–Y6754 1.7 STR–Y6766 / 66A BD Pin Source Current Thermal Shutdown Operating Temperature Symbol Test Conditions ns Parameter IDSS 1–2 VDS=VDSS fo RDS(ON) 1–2 tf ec om m Switching Time en d ed On Resistance D 1–2 IDS=300μA rN Drain Leakage Current VDSS ew Drain-to-Source Breakdown Voltage es ig MOSFET 1–2 V Remarks STR-Y6735 / 35A STR-Y6753 / 54 STR-Y6763 / 63A / 65 /66 /66A μA Ω 1.9 STR–Y6753 2.2 STR–Y6765 STR–Y6763 / 63A STR–Y6753 / 63 / 63A STR-Y6735 / 35A / 54 / 66 / 66A / 65 − − 3.5 − − 250 ns − − 300 ns − 2.4 2.7 − 1.9 2.2 − 2.7 3.1 − 2.3 2.6 − 2.8 3.2 − 5.1 5.9 − 4.6 5.3 − 5.4 6.2 − 5.0 5.8 STR–Y6765 − 5.5 6.3 STR–Y6763 / 63A R Thermal Resistance θch-F − N ot Channel to Frame Thermal Resistance(3) Channel to Case Thermal Resistance(4) (3) (4) θch-C − STR-Y6735 / 35A / 54 STR–Y6766 / 66A °C/W STR–Y6753 STR–Y6765 STR–Y6763 / 63A STR-Y6735 / 35A / 54 STR–Y6766 / 66A °C/W STR–Y6753 θch-F is thermal resistance between channel and internal frame. θch-C is thermal resistance between channel and case. Case temperature is measured at the backside surface. STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 5 STR-Y6700 Series Performance Curves Derating Curves 100 40 20 0 25 50 75 100 115 125 Internal frame temperature, TF (°C) 20 0 25 50 75 100 125 150 Channel Temperature, Tch (°C) Figure 3-2 fo SOA Temperature Derating Coefficient Curve Avalanche Energy Derating Coefficient Curve Ambient Temperature versus Power Dissipation Curves ec om m • STR–Y6735、STR–Y6735A 25 21.5 20 10 25 R With infinite heatsink ot 15 30 N Power Dissipation, PD1 (W) 30 Without heatsink 5 • STR–Y6753 Power Dissipation, PD1 (W) 3.2 en d ed Figure 3-1 40 rN 0 60 ns 60 80 es ig 80 EAS Temperature Derating Coefficient (%) Safe Operating Area Temperature Derating Coefficient (%) 100 D 3.1 ew 3. With infinite heatsink 20.2 20 15 10 Without heatsink 5 1.8 1.8 0 0 0 25 50 75 100 115 125 150 0 25 Ambient Temperature, TA (°C ) STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 50 75 100 115 125 150 Ambient Temperature, TA (°C ) 6 STR-Y6700 Series • STR–Y6754 • STR–Y6763、STR–Y6763A 30 30 25 15 10 Without heatsink 5 1.8 With infinite heatsink 15 10 Without heatsink 5 1.8 25 50 75 100 115 0 125 0 150 25 Ambient Temperature, TA (°C ) 75 100 115 125 150 Ambient Temperature, TA (°C ) • STR–Y6766、STR–Y6766A 30 rN 30 ew • STR–Y6765 23.6 25 With infinite heatsink ed 20 10 Without heatsink 5 1.8 0 0 25 en d 15 50 75 100 115 125 With infinite heatsink fo 21.8 Power Dissipation, PD1 (W) 25 ec om m Power Dissipation, PD1 (W) 50 D 0 0 19.9 20 ns With infinite heatsink 20 es ig 21.5 Power Dissipation, PD1 (W) Power Dissipation, PD1 (W) 25 20 15 10 Without heatsink 5 1.8 0 150 0 50 75 100 115 125 150 Ambient Temperature, TA (°C ) N ot R Ambient Temperature, TA (°C ) 25 STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 7 STR-Y6700 Series 3.3 MOSFET Safe Operating Area Curves • When the IC is used, the safe operating area curve should be multiplied by the temperature derating coefficient derived from Figure 3-1. • The broken line in the safe operating area curve is the drain current curve limited by on-resistance. • Unless otherwise specified, TA = 25 °C, Single pulse • STR–Y6735, STR–Y6735A • STR–Y6753 100 100 0.1 0.01 0.1 10 100 10 1000 Drain-to-Source Voltage (V) 100 rN • STR–Y6763, STR–Y6763A 100 ec om m 10 100 Drain Current, ID (A) 1ms 1 en d 0.1ms 10 ed fo 10 0.1 0.1ms 1 1ms 0.1 0.01 10 1000 R Drain-to-Source Voltage (V) 100 Drain-to-Source Voltage (V) 10 100 Drain Current, ID (A) N 0.1ms 1ms 1 1000 • STR–Y6766, STR–Y6766A ot • STR–Y6765 Drain Current, ID (A) 1000 Drain-to-Source Voltage (V) • STR–Y6754 Drain Current, ID (A) ns 1ms es ig 1 1 D 1ms ew 10 Drain Current, ID (A) Drain Current, ID (A) 0.1ms 10 0.1ms 0.1 0.01 0.1ms 10 1ms 1 0.1 10 100 1000 Drain-to-Source Voltage (V) STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 10 100 1000 Drain-to-Source Voltage (V) SANKEN ELECTRIC CO., LTD. 8 STR-Y6700 Series 3.4 Transient Thermal Resistance Curves • STR–Y6735, STR–Y6735A, STR–Y6754, STR–Y6765 1 0.1 0.01 0.001 1µ 10µ 100µ 1m 10m 100m es ig Time (s) • STR–Y6753, STR–Y6763, STR–Y6763A D 10 ew 1 rN 0.1 0.001 1µ fo 0.01 10µ 100µ 1m 10m 100m 1m 10m 100m ed Transient Thermal Resistance θch-c (°C/W) ns Transient Thermal Resistance θch-c (°C/W) 10 ec om m 10 1 0.1 0.01 R Transient Thermal Resistance θch-c (°C/W) • STR–Y6766, STR–Y6766A 1µ 10µ 100µ Time (s) N ot 0.001 en d Time (s) STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 9 STR-Y6700 Series 4. Block Diagram VCC 3 D/ST 1 STARTUP UVLO Reg / ICONST DRV S/OCP 2 LATCH ns OCP/BS FB/STB OLP OSC GND 4 BD 6 BD_STR-Y6700_R1 D/ST 2 S/OCP 3 VCC 4 5 GND FB/OLP 6 7 BD Pin Name 1 D/ST 2 S/OCP 3 VCC 4 GND 5 FB/OLP 6 BD 7 NF* ec om m 1 en d Pin Configuration Definitions NF R 5. ed fo rN ew BD FB/OLP 5 D NF 7 es ig LOGIC N ot (LF3051) Descriptions MOSFET drain and startup current input MOSFET source and overcurrent protection (OCP) signal input Power supply voltage input for control part and overvoltage protection (OVP) signal input Ground Constant voltage control signal input and over load protection (OLP) signal input Bottom Detection signal input, Input Compensation detection signal input (Non-function) *For stable operation, NF pin should be connected to GND pin, using the shortest possible path. STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 10 STR-Y6700 Series 6. Typical Application • The PCB traces D/ST pins should be as wide as possible, in order to enhance thermal dissipation. • In applications having a power supply specified such that D/ST pin has large transient surge voltages, a clamp snubber circuit of a capacitor-resistor-diode (CRD) combination should be added on the primary winding P, or a damper snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the D/ST pin and the S/OCP pin. • For stable operation, NF pin should be connected to GND pin, using the shortest possible path. CRD clamp snubber BR1 L51 D51 T1 VOUT(+) VAC D1 C51 S U1 R54 R51 es ig PC1 ns R1 P C2 C1 R55 R52 C53 D rN D/ST 2 S/OCP VCC GND FB/OLP BD NF C3 U51 R56 VOUT(-) DZBD fo 2 3 4 5 6 7 1 R2 ew D2 STR-Y6700 D C52 R53 CV R3 en d C(RC) Damper snubber ed RBD1 CBD ROCP C5 PC1 CY ec om m C4 RBD2 N ot R Figure 6-1 Typical application STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 11 STR-Y6700 Series 7. Physical Dimensions 2.8 +0.2 • TO220F-7L 10±0.2 4.2 ±0.2 2.6±0.2 ns 15 ±0.3 3.2±0.2 （5.6） Gate burr （1.1） es ig 2.6 ±0.1 2±0.15 5×P1.17±0.15 ＝5.85±0.15 （Measured at pin base） （Measured at pin base） D R-end ew R-end rN 7-0.55 +0.2 -0.1 +0.2 0.45 -0.1 2.54±0.6 （Measured at pin tip） fo 7-0.62±0.15 5±0.5 10.4 ±0.5 5±0.5 （Measured at pin base） 0.5 0.5 Front view 0.5 0.5 Side view 2 3 4 5 6 7 ec om m 1 en d ed 5.08±0.6 （Measured at pin tip） ot R NOTES : 1) Dimension is in millimeters. 2) Leadform: LF No.3051 3) Gate burr indicates protrusion of 0.3 mm (max.). 4) Pin treatment Pb-free. Device composition compliant with the RoHS directive. N 8. Marking Diagram STR Y67××× Part Number 2 YMDDX 1 2 7 STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 Lot Number: Y is the last digit of the year of manufacture (0 to 9) M is the month of the year (1 to 9, O, N or D) DD is the day of the month (01 to 31) X is the control number SANKEN ELECTRIC CO., LTD. 12 STR-Y6700 Series winding so that VCC pin voltage becomes Equation (1) within the specification of input and output voltage variation of power supply. Operational Description • All of the parameter values used in these descriptions are typical values, unless they are specified as minimum or maximum. • With regard to current direction, "+" indicates sink current (toward the IC) and "–" indicates source current (from the IC). ⇒12.5 (V)  VCC  28.5 (V) The startup time of IC is determined by C3 capacitor value. The approximate startup time tSTART (shown in Figure 9-2) is calculated as follows: Startup Operation Figure 9-1 shows the circuit around IC. Figure 9-2 shows the start up operation. t START  C3 × T1 VAC C1 VCC 3 D2 D Undervoltage Lockout (UVLO) D Figure 9-3 shows the relationship of VCC pin voltage and circuit current ICC. When VCC pin voltage decreases to VCC(OFF) = 9.4 V, the control circuit stops operation by Undervoltage Lockout (UVLO) circuit, and reverts to the state before startup. 4 Circuit current, ICC en d Figure 9-1 VCC pin peripheral circuit ed fo GND R2 VD (2) where, tSTART : Startup time of IC (s) VCC(INT) : Initial voltage on VCC pin (V) P 9.2 C3 I CC (STRATUP ) rN U1 VCC ( ON )－VCC ( INT ) es ig BR1 1 D/ST (1) ns 9.1 VCC( BIAS) (max .)  VCC  VCC(OVP) (min .) ew 9. ec om m VCC pin voltage VCC(ON) Stop Start tSTART VCC（OFF） R Drain current, ID Figure 9-2 Startup operation Figure 9-3 Relationship between VCC pin voltage and ICC ot N The IC incorporates the startup circuit. The circuit is connected to D/ST pin. When D/ST pin voltage reaches to Startup Circuit Operation Voltage V START(ON) = 57 V, the startup circuit starts operation. During the startup process, the constant current, ICC(STARTUP) = − 3.1 mA, charges C3 at VCC pin. When VCC pin voltage increases to VCC(ON) = 15.1 V, the control circuit starts operation. During the IC operation, the voltage rectified the auxiliary winding voltage, VD, of Figure 9-1 becomes a power source to the VCC pin. After switching operation begins, the startup circuit turns off automatically so that its current consumption becomes zero. The approximate value of auxiliary winding voltage is about 20 V, taking account of the winding turns of D STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 VCC（ON） VCC pin voltage 9.3 Bias Assist Function By the Bias Assist Function, the startup failure is prevented and the latched state is kept. The Bias Assist function is activated, when the VCC voltage decreases to the Startup Current Biasing Threshold Voltage, VCC(BIAS) = 11.0 V, in either of following condition: the FB pin voltage is the Standby Operation Threshold Voltage, VFB(STBOP) = 0.80 V or less or the IC is in the latched state due to activating the protection function. SANKEN ELECTRIC CO., LTD. 13 STR-Y6700 Series When the Bias Assist Function is activated, the VCC pin voltage is kept almost constant voltage, VCC(BIAS) by providing the startup current, ISTARTUP, from the startup circuit. Thus, the VCC pin voltage is kept more than VCC(OFF). Since the startup failure is prevented by the Bias Assist Function, the value of C3 connected to VCC pin can be small. Thus, the startup time and the response time of the OVP become shorter. step-wisely (4 steps). This function reduces the voltage and the current stress of MOSFET and secondary side rectifier diode. During the soft start operation period, the operation is in PWM operation, at an internally set operation frequency, fOSC = 21.0 kHz. Until BD pin voltage becomes the following condition after the soft start time, the switching operation is PWM control of fOSC = 21.0 kHz. When BD pin voltage, VBD, becomes the following condition, the IC starts quasi-resonant operation. ns The operation of the Bias Assist Function in startup is as follows. It is necessary to check and adjust the startup process based on actual operation in the application, so that poor starting conditions may be avoided. es ig rN ew D After the soft start period, D/ST pin current, ID, is limited by the overcurrent protection (OCP), until the output voltage increases to the target operating voltage. This period is given as tLIM. When tLIM is longer than the OLP Delay Time, tOLP, the output power is limited by the OLP operation (OLP). Thus, the tOLP must be set longer than tLIM (refer to Section 9.12). fo Figure 9-4 shows VCC pin voltage behavior during the startup period. After VCC pin voltage increases to VCC(ON) = 15.1 V at startup, the IC starts the operation. Then circuit current increases and VCC pin voltage decreases. At the same time, the auxiliary winding voltage VD increases in proportion to output voltage. These are all balanced to produce VCC pin voltage. When VCC pin voltage is decrease to VCC(OFF) = 9.4 V in startup operation, the IC stops switching operation and a startup failure occurs. When the output load is light at startup, the output voltage may become more than the target voltage due to the delay of feedback circuit. In this case, the FB pin voltage is decreased by the feedback control. When the FB pin voltage decreases to the Standby Operation Threshold Voltage, VFB(STBOP) = 0.80 V, or less, the IC stops switching operation and VCC pin voltage decreases. When VCC pin voltage decreases to VCC(BIAS), the Bias Assist function is activated and the startup failure is prevented. Quasi-resonant operation starting condition  VBD ≥ VBD(TH1) = 0.24 V  The effective pulse width of quasi-resonant signal is 1.0 μs or more (refer to Figure 9-12) VCC(OFF) tSS tLIM Time D/ST pin current, ID Startup success ot VCC(ON) VCC(BIAS) tSTART VCC(ON) IC starts operation Target operating voltage Increase with rising of output voltage R VCC pin voltage ec om m en d ed Startup of IC Startup of SMPS Normal operation VCC pin voltage N VCC(OFF) Bias assist period PWM operation Time Quasi-resonant operation BD pin voltage VBD(TH1) Enlarged Waveform Startup failure PWM operation Time Time Quasi-resonant operation Figure 9-4 VCC pin voltage during startup period The effective pulse width is 1.0µs or more 9.4 Soft Start Function Figure 9-5 shows the behavior of VCC pin voltage, drain current and BD pin voltage during the startup period. The IC activates the soft start circuitry during the startup period. Soft start is fixed to tSS = 6.05 ms. During the soft start period, over current threshold is increased STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 Figure 9-5 VCC and ID and VBD behavior during startup SANKEN ELECTRIC CO., LTD. 14 STR-Y6700 Series Constant Output Voltage Control 9.6 The IC achieves the constant voltage control of the power supply output by using the current-mode control method, which enhances the response speed and provides the stable operation. The IC compares the voltage, VROCP, of a current detection resistor with the target voltage, VSC, by the internal FB comparator, and controls the peak value of VROCP so that it gets close to VSC, as shown in Figure 9-6 and Figure 9-7. VSC is generated by the FB/OLP pin voltage. Leading Edge Blanking Function The IC uses the peak-current-mode control method for the constant voltage control of output. In peak-current-mode control method, there is a case that the power MOSFET turns off due to unexpected response of FB comparator or overcurrent protection circuit (OCP) to the steep surge current in turning on a power MOSFET. In order to prevent this response to the surge voltage in turning-on the power MOSFET, the Leading Edge Blanking, tON(LEB) is built-in. During tON(LEB), the OCP threshold voltage becomes VOCP(La.OFF) = 1.83 V in order not to respond to the turn-on drain current surge (refer to Section 9.11). When load conditions become lighter, the output voltage, VOUT, increases. Thus, the feedback current from the error amplifier on the secondary-side also increases. The feedback current is sunk at the FB/OLP pin, transferred through a photo-coupler, PC1, and the FB/OLP pin voltage decreases. Thus, VSC decreases, and the peak value of VROCP is controlled to be low, and the peak drain current of I D decreases. This control prevents the output voltage from increasing. es ig ns • Light load conditions Quasi-Resonant Operation and Bottom-On Timing Setup 9.7.1 • Heavy load conditions Quasi-Resonant Operation Using quasi-resonant operation, switching loss and switching noise are reduced and it is possible to obtain converters with high efficiency and low noise. This IC performs quasi-resonant operation during one bottom-skip operation. Figure 9-8 shows the circuit of a flyback converter. The meaning of symbols in Figure 9-8 is shown in Table 9-1. A flyback converter is a system that transfers the energy stored in the transformer to the secondary side when the primary side power MOSFET is turned off. After the energy is completely transferred to the secondary, when the power MOSFET keeps turning off, the VDS begins free oscillation based on the LP and CV. U1 GND FB/OLP ec om m S/OCP 2 4 5 R3 VROCP en d ed fo When load conditions become greater, the IC performs the inverse operation to that described above. Thus, VSC increases and the peak drain current of ID increases. This control prevents the output voltage from decreasing. ew D 9.7 rN 9.5 PC1 C4 IFB R ROCP C5 N ot Figure 9-6 FB/OLP pin peripheral circuit Target voltage + The quasi-resonant operation is the bottom-on operation that the power MOSFET turns-on at the bottom point of free oscillation of VDS. Figure 9-9 shows an ideal VDS waveform during bottom-on operation. The delay time, tONDLY, is the time from starting free oscillation of VDS to power MOSFET turn-on. The tONDLY of an ideal bottom-on operation is half cycle of the free oscillation, and is calculated using Equation (3). t ONDLY≒  L P  C V (3) VSC VF T1 VROCP FB Comparator Voltage on both sides of ROCP VFLY C1 ID P Drain current, ID STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 S IOFF VO C51 VIN NP U1 Figure 9-7 Drain current, ID, and FB comparator operation in steady operation D51 LP NS CV Figure 9-8 Basic flyback converter circuit SANKEN ELECTRIC CO., LTD. 15 STR-Y6700 Series ID IOFF CV LP VIN ns NP NS VO VF C1 VIN CV 1 3 VCC D/ST tONDLY rN U1 VFLY 2 S/OCP GND 4 R fo VIN VDS 0 OCP ed Bottom point ec om m en d IOFF 0 ID 0 tON DZBD 6 CBD D VFW1 Forward voltage Flyback voltage RBD1 RBD2 VREV2 Figure 9-10 BD pin peripheral circuit Auxiliary winding voltage, VD VREV1 0 Figure 9-9 Ideal bottom-on operation waveform VFW1 R 9.7.2 BD R2 VREV1 C3 T1 P VFLY D2 D VDS Descriptions Input voltage Flyback voltage N VFLY  P  VO  VF  NS The voltage between Drain and Source of power MOSFET Primary side number of turns Secondary side number of turns Output voltage Forward voltage drop of the secondary side rectifier Drain current of power MOSFET Current which flows through the secondary side rectifier when power MOSFET is off Voltage resonant capacitor Primary side inductance ew Symbol VIN VFLY The threshold voltage of quasi-resonant operation has a hysteresis. VBD(TH1) is Quasi-Resonant Operation Threshold Voltage 1, VBD(TH2) is Quasi-Resonant Operation Threshold Voltage 2. When the BD pin voltage, VREV2, increases to VBD(TH1) = 0.24 V or more at the power MOSFET turns-off, the power MOSFET keeps the off-state. After that, the VDS decreases by the free oscillation. When the VDS decreases to VBD(TH2) = 0.17 V, the power MOSFET turns-on and the threshold voltage goes up to VBD(TH1) automatically to prevent malfunction of the BD pin from noise interference. es ig Table 9-1 The meaning of symbols in Figure 9-8 Bottom-On Timing Setup N ot BD pin detects the signal of bottom-on timing and input compensation of OCP1 (refer to Section 9.11.3). Figure 9-10 shows the BD pin peripheral circuit, Figure 9-11 shows the waveform of auxiliary winding voltage. The quasi-resonant signal, VREV2, is proportional to auxiliary winding voltage, VD and is calculated as follows: VREV2  R BD2  VREV1  VF  R BD1  R BD2 (4) where, VREV1: Flyback voltage of auxiliary winding D VF : Forward voltage drop of ZBD The BD pin detects the bottom point using the VREV2. STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 3.0 V recommended, but less than 6.0 V acceptable Quasi-resonant Signal, VREV2 VBD(TH1) tON VBD(TH2) 0 Figure 9-11 The waveform of auxiliary winding voltage  RBD1 and RBD2 Setup RBD1 and RBD2 should be set so that VREV2 becomes the following range: Under the lowest condition of VCC pin voltage in power supply specification, VREV2 ≥ VBD(TH1)= 0.34 V(max.). Under the highest condition of VCC pin voltage in SANKEN ELECTRIC CO., LTD. 16 STR-Y6700 Series power supply specification, VREV2 < 6.0 V (Absolute maximum rating of the BD pin) and the effective pulse width of quasi-resonant signal is 1.0 μs or more (refer to Figure 9-12). The value of VREV2 is recommended about 3.0 V. In the converse situation, if the turn-on point lags behind the VDS bottom point (Figure 9-14), after confirming the initial turn-on point, advance the turn-on point by decreasing the CBD value gradually, so that the turn-on will match the bottom point of VDS. 3.0 V recommended, but less than 6.0 V acceptable Quasi-resonant signal, VREV2 Delayed turn-on point 0.34V VDS 0.27V 0 ID 0 Figure 9-12 The effective pulse width of quasi-resonant signal VBD(TH2) rN ew VBD(TH1) VBD 0 Auxiliary winding voltage ｔON 0 fo VD Figure 9-14 When the turn-on of a VDS waveform occurs after a bottom point ec om m en d ed  CBD Setup The delay time, tONDLY, until which the power MOSFET turns on, is adjusted by the value of CBD, so that the power MOSFET turns on at the bottom-on of VDS (refer to Figure 9-9). The initial value of CBD is set about 1000 pF. CBD is adjusted while observing the actual operation waveforms of VDS and ID under the maximum input voltage and the maximum output power (If a voltage probe is connected to BD pin, the bottom point may misalign). If the turn-on point precedes the bottom of the VDS signal (see Figure 9-13), after confirming the initial turn-on point, delay the turn-on point by increasing the CBD value gradually, so that the turn-on will match the bottom point of VDS. es ig 0 D IOFF ns Bottom point Effective pulse width (1.0μs or more) 0 Bottom point ot VDS R Early turn-on point 0 N IOFF ID 0 ｔON VBD(TH1) VBD 0 Auxiliary winding voltage VD VBD(TH2) 0 Figure 9-13 When the turn-on of a VDS waveform occurs before a bottom point STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 9.8 BD Pin Blanking Time Since the auxiliary winding voltage is input to the BD pin, BD pin voltage may be affected from the surge voltage ringing when the power MOSFET turns off. If the IC detects the surge voltage as quasi-resonant signal, the IC may repeatedly turn the power MOSFET on and off at high frequency. This result in an increase of the MOSFET power dissipation and temperature, and it can be damaged. The BD pin has a blanking period of 250 ns (max.) to avoid detecting voltage during this period. The poor coupling (the high leakage inductance) tends to happen in a low output voltage transformer design with high NP/ NS turns ratio (NP and NS indicate the number of turns of the primary winding and secondary winding, respectively), and the surge voltage ringing of BD pin occurs easily (see Figure 9-15). If the surge voltage continues longer than BD pin blanking period and the high frequency operation of power MOSFET occurs, the following adjustments are required so that the surge period of BD pin is less than 250 ns. In addition, the BD pin waveform during operation should be measured by connecting test probes as short to the BD pin and the GND pin as possible, in order to measure any surge voltage correctly. SANKEN ELECTRIC CO., LTD. 17 STR-Y6700 Series  CBD must be connected near the BD pin and the GND pin.  The circuit trace loop between the BD pin and the GND pin must be separated from any traces carrying high current  The coupling of the primary winding and the auxiliary winding must be good  The clamping snubber circuit (refer to Figure 6-1) must be adjusted properly. and this enables the IC to switch in a stable operation. Before the one bottom-skip point changed from heavy to light load, or after that done from light to heavy load, the switching frequency of the normal quasi-resonant operation becomes higher and the switching loss of power MOSFET increases. Thus, the temperature of the power MOSFET should be checked at higher switching frequency of the operation changing point in maximum AC input voltage. One bottom-skip quasi-resonant VBD(TH2) ns VOCP(H) VOCP(BS1) VBD(TH1) es ig VREV2 (a)Normal BD pin waveform (good coupling) Normal quasi-resonant VOCP(BS2) D VBD(TH1) VBD(TH2) ew VREV2 Figure 9-16 Hysteresis at the operational mode change BD pin blanking time 250ns（max.） rN ed Figure 9-15 The difference of BD pin voltage, VREV2, waveform by the coupling condition of the transformer  The mode is changed from one bottom-skip quasi-resonant operation to normal quasi-resonant operation (light load to heavy load). When load is increased from one bottom-skip operation, the MOSFET peak drain current value will increase, and the positive pulse width will widen. Also, the peak value of the S/OCP pin voltage increases. When the load is increased further and the S/OCP pin voltage rises to VOCP(BS1), the mode is changed to normal quasi-resonant operation (see Figure 9-17). fo (b)Inappropriate BD pin waveform (poor coupling) Multi-mode Control en d 9.9 ec om m When the output power decreases, the usual quasi-resonant control increases the switching frequency and the switching loss. Thus, The IC has the multi-mode control to achieve high efficiency operation across the full range of loads. The automatic multi-mode control changes among the following three operational modes according to the output loading state: normal quasi-resonant operation in heavy load, one bottom-skip quasi-resonant operation in medium to light load, and burst oscillation operation (auto standby function) in light load. R ot STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 Normal quasi-resonant VOCP(H) S/OCP pin voltage Light load One Bottom-Skip Quasi-Resonant Operation The one bottom-skip function limits the rise of the power MOSFET operation frequency in medium to light load in order to reduce the switching loss. Figure 9-17 shows the operation state transition diagram of the output load from light load to heavy load. Figure 9-18 shows the state transition diagram from heavy load to light load. As shown in Figure 9-16, in the process of the increase and decrease of load current, hysteresis is imposed at the time of each operational mode change. For this reason, the switching waveform does not become unstable near the threshold voltage of a change, One bottom-skip quasi-resonant VDS N 9.9.1 Load current VOCP(BS1) Heavy load Figure 9-17 Operation state transition diagram from light load to heavy load conditions  The mode is changed from normal quasi-resonant operation to one bottom-skip quasi-resonant operation (heavy load to light load). When load is decreased from normal quasi-resonant operation, the MOSFET peak drain current value will decrease, and the positive pulse width will narrow. Also, the peak value of the S/OCP pin voltage decreases. When load is reduced further and the S/OCP pin voltage falls to VOCP(BS2), the mode is SANKEN ELECTRIC CO., LTD. 18 STR-Y6700 Series changed to one bottom-skip quasi-resonant operation (see Figure 9-18). One bottom-skip quasi-resonant Normal quasi-resonant VDS 9.9.2 VOCP(H) S/OCP pin voltage VOCP(BS2) Light load ec om m Quasi-resonant signal, VREV2 en d ed fo rN ew D es ig Figure 9-18 Operation state transition diagram from heavy load to light load conditions Figure 9-19 shows the effective pulse width of normal quasi-resonant signal, and Figure 9-20 shows the effective pulse width of one bottom-skip quasi-resonant signal. In order to perform stable normal quasi-resonant operation and one bottom-skip operation, it is necessary to ensure that the pulse width of the quasi-resonant signal is 1 μs or more under the conditions of minimum input voltage and minimum output power. The pulse width of the quasi-resonant signal, VREV2, is defined as the period from the maximum specification of VBD(TH1), 0.34 V, on the rising edge, to the maximum specification of VBD(TH2), 0.27 V on the falling edge of the pulse. The S/OCP pin circuit monitors ID. Automatic standby mode is activated automatically when ID reduces under light load conditions at which the S/OCP pin voltage falls to the standby state threshold voltage (about 9% compared to VOCP(H) = 0.910 V). During standby mode, when the FB/OLP pin voltage falls below VFB(STBOP), the IC stops switching operation, and the burst oscillation mode will begin, as shown in Figure 9-21. Burst oscillation mode reduces switching losses and improves power supply efficiency because of periodic non-switching intervals. Generally, to improve efficiency under light load conditions, the frequency of the burst oscillation mode becomes just a few kilohertz. Because the IC suppresses the peak drain current well during burst oscillation mode, audible noises can be reduced. If the VCC pin voltage decreases to VCC(BIAS) = 11.0 V during the transition to the burst oscillation mode, the Bias Assist function is activated and stabilizes the Standby mode operation, because ICC(STARTUP) is provided to the VCC pin so that the VCC pin voltage does not decrease to VCC(OFF). However, if the Bias Assist function is always activated during steady-state operation including standby mode, the power loss increases. Therefore, the VCC pin voltage should be more than VCC(BIAS), for example, by adjusting the turns ratio of the auxiliary winding and secondary winding and/or reducing the value of R2 in Figure 10-2 (refer to Section 10.1 Peripheral Components for a detail of R2). ns Heavy load Automatic Standby Mode Function 0.34V Output current, IOUT Burst oscillation 0.27V Effective pulse width 1.0µs or more R S/OCP pin voltage Below several kHz Drain current, ID Figure 9-19 The effective pulse width of normal quasi-resonant signal N ot Normal operation Standby operation Normal operation Figure 9-21 Auto Standby mode timing Quasi-resonant signal, VREV2 9.10 Maximum On-Time Limitation Function 0.34V 0.27V S/OCP pin voltage Effective pulse width 1.0µs or more Figure 9-20 The effective pulse width of one bottom-skip quasi-resonant signal STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 When the input voltage is low or in a transient state such that the input voltage turns on or off, the on-time of the incorporated power MOSFET is limited to the maximum on-time, tON(MAX) = 40.0 μs in order to prevent the decreasing of switching frequency. Thus, the peak drain current is limited, and the audible noise of the transformer is suppressed. In designing a power supply, the on-time must be less SANKEN ELECTRIC CO., LTD. 19 STR-Y6700 Series than tON(MAX) (see Figure 9-22). If such a transformer is used that the on-time is tON(MAX) or more, under the condition with the minimum input voltage and the maximum output power, the output power would become low. In that case, the transformer should be redesigned taking into consideration the following: Figure 9-23 S/OCP pin voltage In addition, if a C (RC) damper snubber of Figure 9-24 is used, reduce the capacitor value of damper snubber. If the turn-on timing isn’t fitted to a VDS bottom point, adjustments are required (refer to Section 9.7.2).  Inductance, LP, of the transformer should be lowered in order to raise the operation frequency. C（CR） damper snubber T1  Lower the primary and the secondary turns ratio, N P / NS, to lower the duty cycle. U1 S/OCP 2 time VDS C（CR） damper snubber ew ROCP ns 1 D/ST es ig On-time C51 D ID D51 C1 time rN Figure 9-24 Damper snubber circuit Figure 9-22 Confirmation of maximum on-time fo 9.11.2 Overcurrent Protection 2 (OCP2) 9.11 Overcurrent Protection (OCP) ec om m en d ed The IC has an Overcurrent Protection 1 (OCP1) and an Overcurrent Protection 2 (OCP2). OCP1 function: pulse-by-pulse, with Input Compensation Function. The OCP2 function: In case output winding is shorted etc., the IC stops switching operation at the latched state. The products with the last letter "A" don’t have the OCP2 function. The products with the last letter "A" don’t have the OCP2 function. As the protection for an abnormal state, such as an output winding being shorted or the withstand voltage of secondary rectifier being out of specification, when the S/OCP pin voltage reaches VOCP(La.OFF) = 1.83 V, the IC stops switching operation immediately, in latch mode. This overcurrent protection also operates during the leading edge blanking. Releasing the latched state is done by turning off the input voltage and by dropping the VCC pin voltage below VCC(OFF). 9.11.1 Overcurrent Protection 1 (OCP1) N ot R OCP1 detects each drain peak current level of a power MOSFET on pulse-by-pulse basis, and limits the output power when the current level reaches to OCP threshold voltage. During Leading Edge Blanking Time (tBW), OCP1 is disabled. When power MOSFET turns on, the surge voltage width of S/OCP pin should be less than tON(LEB), as shown in Figure 9-23. In order to prevent surge voltage, pay extra attention to ROCP trace layout (refer to Section 10.3). tON(LEB) VOCP(H)’ Surge at MOSFET turn on STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 9.11.3 OCP1 Input Compensation Function The usual control ICs have some propagation delay time. The steeper the slope of the actual drain current at a high AC input voltage is, the larger the detection voltage of actual drain peak current is, compared to overcurrent detection threshold voltage. Thus, the peak current has some variation depending on the AC input voltage in OCP1 state. When using a quasi-resonant converter with universal input (85 to 265 VAC), if the output power is set constant, then because higher input voltages have higher frequency, the on-time is reduced. Thus, the peak current in OCP1 state tends to be affected by propagation delay in the higher input voltage. If the IC does not have Input Compensation Function, the output current at OCP1 point in the maximum input voltage, IOUT(OCP), becomes about double of IOUT (Figure SANKEN ELECTRIC CO., LTD. 20 STR-Y6700 Series detection voltage for an overcurrent event is the Overcurrent 1 Detection Threshold Voltage in Normal Operation, VOCP(H). When VDZBD < VFW1 (Point B through Point D), the input voltage is increased and VFW1 exceeds the Zener voltage, VZ, of DZBD. VFW2 will be produced as a negative voltage to compensate VOCP(H). The value of VFW2 should be adjusted so that the difference between IOUT and IOUT(OCP) is minimized as shown in Figure 9-25 “With optimal input compensation”. If the excessive input compensation, IOUT(OCP) may become less than IOUT (Figure 9-25 “With excessive input compensation”). Thus, value of VFW2 must be adjusted so that IOUT(OCP) remains more than IOUT, across the input voltage range. Without input compensation With optimal input compensation ns Target output current With excessive input compensation 85V 265V AC input voltage （V） es ig IOUT VAC 230 100 0 Figure 9-25 OCP1 input compensation ew Auxiliary winding voltage rN VFW1 fo VDZBD 0 VZ VFW2 0 A en d ec om m VREV1 0 ed Figure 9-26 shows the OCP1 input compensation circuit. The value of input compensation is set by BD pin peripheral circuit. By OCP1 Input Compensation Function, Overcurrent Detection 1 Threshold Voltage in Normal Operation, VOCP(H) = 0.910 V, is compensated depending on an AC input voltage. The forward voltage of auxiliary winding D, VFW1, is proportional to AC input voltage. As shown in Figure 9-26, the voltage obtained by subtracting zener voltage, VZ, of DZBD from VFW1 is biased by either end of RBD1 and RBD2, and thus the BD pin voltage is provided the voltage on RDB2 divided by the divider of RBD1 and RBD2. D Output Current at OCP1 IOUT(OCP) （A） 9-25 “without input compensation”). IOUT is the target output current considered with maximum output power in the minimum input voltage. In order to suppress this variability, this IC has the overcurrent input compensation function. B C D At the input voltage where VFW1 reaches VZ or more, VFW2 goes negative. Flyback voltage, VREV1 D2 R2 T1 Figure 9-27 Each voltage waveform for the input voltage in normal quasi-resonant operation N ot R C3 3 VCC BD S/OCP GND 2 4 ROCP DZBD D Forward voltage VDZBD V FW1 RBD1 6 CBD RBD2 1) VIN(AC)C Setup VIN(AC)C is the AC input voltage that starts input compensation. In general specification, VIN(AC)C is set 120 VAC to 170 VAC. 2) VZ Setup VIN(AC)C is adjusted by the zener voltage, VZ, of DZBD. The VFW1 at VIN(AC)C is calculated by using Equation (5). VZ is set from the result. VFW2 Figure 9-26 OCP input compensation circuit Figure 9-27 shows the each voltage waveform for the input voltage in normal quasi-resonant operation. When VDZBD ≥ VFW1 (Point A), No input compensation required, VFW2 remains zero, and the STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 Setup of BD pin peripheral components (DZBD, RBD1 and RBD2) is as follows: VFW1  ND  VIN( AC) C  2  VZ NP (5) where, NP: Primary side number of turns ND: Secondary side number of turns SANKEN ELECTRIC CO., LTD. 21 STR-Y6700 Series 3) RBD1 and RBD2 Setup. The recommended value of RBD2 is 1.0 kΩ. In general specification, RBD1 is set by using result of Equation (6) so that VFW2 = −3.0 V at maximum AC input voltage. R BD1 5) VREV2 is calculated by using Equation (8) and is checked to be the Quasi-Resonant Operation Threshold Voltage 1, VBD(TH1) = 0.34 V (max.), or more (refer to Figure 9-11). VREV2  R  BD2 VFW 2 N   D  VIN( AC) MAX  2  VZ  VFW 2  NP (6)    where, VREV1: Flyback voltage of auxiliary wining VF: Forward voltage drop of DZBD D es ig 6) The BD pin voltage, which includes surge voltage, must be observed within the absolute maximum rating of the BD pin voltage (–6.0 to 6.0 V) in the actual operation at the maximum input voltage. fo rN ew < BD Pin Peripheral Components Value Selection Reference Example > Setting value: Input voltage: VIN(AC) = 85VAC to 265VAC, AC input voltage that starts input compensation: VIN(AC)C = 120 VAC, Primary side winding number of turns: NP = 40 T, Auxiliary winding number of turns: ND = 5 T Forward voltage of auxiliary winding: VFW1 = 20 V R BD2 R BD1  R BD2  N   D  VIN( AC) MAX  2  VZ    N   P (7) VOCP(H) ot 0.6 N VOCP(H)' (V) 0.8 VFW1 is calculated by using Equation (5) as follows: ND  VIN( AC) C  2 NP VFW1   5 120 2  21.2V 40 Thus, zener voltage of DZBD is chosen to be 22 V of the E series. When VFW2 = −3.0 V at maximum input voltage, 265VAC, RBD1 is calculated by using Equation (6) as follows: R 1 ec om m  R BD2   VFW1  VZ  R BD1  R BD2 en d ed 4) VOCP(H)' is the overcurrent threshold voltage after input compensation. Figure 9-28 shows a relationship of VOCP(H)' and BD pin voltage,VFW2. VFW2 at maximum AC input voltage is calculated by using Equation (7). VOCP(H)' and this variation are gotten by using the result from Figure 9-28. When VOCP(H)' including variation becomes the Bottom-Skip Operation Threshold Voltage 1, VOCP(BS1) = 0.572 V, or less, the operation of IC is one bottom-skip only and the output current may be less than target output current, IOUT. VFW2  Max. R BD1  Typ. 0.4 Min. 0.2 0 00 −1 -1 −2 -2 −3 -3 −4 -4 −5 -5 (8) ns where, VFW2: BD pin voltage (−3.0 V) NP: Primary side winding number of turns ND: Auxiliary winding number of turns VIN(AC)MAX: Maximum AC input voltage VZ: Zener voltage of DZBD R BD2  VREV1  VF  ≥ 0.34 V R BD1  R BD2 −6 -6  R BD2  N D   VIN( AC) MAX  2－VZ  VFW 2 VFW 2  N P    1k  5     265 2  22   3   7.28kΩ  3  40  Thus, RBD1 is chosen to be 7.5 kΩ of the E series. BD pin voltage VFW2 (V) Figure 9-28 Overcurrent threshold voltage after input compensation, VOCP(H)' (reference for design target values) STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 22 STR-Y6700 Series When RBD2 = 1.0 kΩ, |VFW2| value at 265 VAC is calculated by using Equation (7) as follows: VFW2  When the peak drain current of ID is limited by Overcurrent Protection 1 operation, the output voltage, VOUT, decreases and the feedback current from the secondary photo-coupler becomes zero. Thus, the feedback current, IFB, charges C4 connected to the FB/OLP pin and the FB/OLP pin voltage, VFB/OLP, increases. When VFB/OLP increases to the FB Pin Maximum Voltage in Feedback Operation, VFB(MAX) = 4.05 V, or more, C4 is charged by IFB(OLP) = − 10 µA. When VFB/OLP increases to the OLP Threshold Voltage, VFB(OLP) = 5.96 V, the OLP function is activated, the IC stops switching operation in the latched state. In order to keep the latched state, when VCC pin voltage decreases to VCC(BIAS), the bias assist function is activated and VCC pin voltage is kept to over the VCC(OFF). Releasing the latched state is done by turning off the input voltage and by dropping the VCC pin voltage below VCC(OFF). R BD2   VFW1  VZ  R BD1  R BD2  1k  5     265 2  22   2.92V 7.5k  1k  40  es ig ew  D R BD2  VREV1  VF  R BD1  R BD2 GND 1k  20  0.7   2.27V 1k  7.5k rN VREV2  ns Referring to Figure 9-28, when VFW2 is compensated to –2.92 V, the overcurrent threshold voltage after input compensation, VOCP(H)', is set to about 0.66 V (typ). When setting RBD2 = 1.0 kΩ, RBD1 = 7.5 kΩ, VF = 0.7 V, and VREV1 = 20 V, VREV2 is calculated by using Equation (8) as follows: ot R ec om m en d When the input voltage is narrow range, or provided from PFC circuit, the variation of the input voltage is small. Thus, the variation of OCP point may become less than that of the universal input voltage specification. When overcurrent input compensation is not required, the input compensation function can be disabled by substituting a high-speed diode for the zener diode, DZBD, and by keeping BD pin voltage from being minus voltage. In addition, Equation (9) shows the reverse voltage of a high-speed diode. The peak reverse voltage of high-speed diode selection should take account of its derating. ND  VIN( AC) MAX  2 NP (9) N VFW1  where, VFW1: Forward voltage of auxiliary wining NP: Primary side number of turns ND: Secondary side number of turns VIN(AC)MAX: Maximum AC input voltage 9.12 Overload Protection (OLP) Figure 9-29 shows the FB/OLP pin peripheral circuit, Figure 9-29 shows each waveform for Overload Protection (OLP) operation. STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 5 IFB R3 C4 C5 PC1 ed 9.11.4 When Overcurrent Input Compensation is Not Required 4 fo VREV2 is VBD(TH1) = 0.34 V (max.) or more. FB/OLP Figure 9-29 FB/OLP pin peripheral circuit VCC pin voltage VCC(BIAS) VCC(OFF) FB/OLP pin voltage, VFB/OLP VFB(OLP) VFB(MAX) Drain current, ID AC input voltage off Latch release Charged by IFB(OLP) tDLY Figure 9-30 OLP operation waveforms The time of the FB/OLP pin voltage from VFB(MAX) to VFB(OLP) is defined as the OLP delay time, tDLY. Because the capacitor C5 for phase compensation is small compared to C4, the approximate value of tDLY is calculated by Equation (10). When C4 = 4.7 μF, the value of tDLY would be approximately 0.9 s. The recommended value of R3 is 47 kΩ. SANKEN ELECTRIC CO., LTD. 23 STR-Y6700 Series FB ( OLP ) 9.13 Overvoltage Protection (OVP)   VFB ( MAX )  C4 When a voltage between VCC pin and GND pin increases to VCC(OVP) = 31.5 V or more, Overvoltage Protection (OVP) is activated, the IC stops switching operation at the latched state. In order to keep the latched state, when VCC pin voltage decreases to VCC(BIAS), the bias assist function is activated and VCC pin voltage is kept to over the VCC(OFF). Releasing the latched state is done by turning off the input voltage and by dropping the VCC pin voltage below VCC(OFF). When the VCC pin voltage is provided by using auxiliary winding of transformer, the overvoltage conditions such as output voltage detection circuit open can be detected because the VCC pin voltage is proportional to output voltage. The approximate value of output voltage VOUT(OVP) in OVP condition is calculated by using Equation (11). I FB ( OLP ) 5.96V  4.05V  C4 es ig D VOUT ( NORMAL ) ew VOUT(OVP)  VCC ( NORMAL )  31.5 (V) (11) where, VOUT(NORMAL): Output voltage in normal operation VCC(NORMAL): VCC pin voltage in normal operation ed To enable the overload protection function to initiate an automatic restart, 220 kΩ is connected between the FB/OLP pin and ground, as a bypass path for I FB(OLP), as shown in Figure 9-31. Thus, the FB/OLP pin is kept under VFB(OLP) in OLP state. In OLP state as an output shorted, the output voltage and VCC pin voltage decrease. During the operation, Bias Assist Function is disabled. Thus, VCC pin voltage decreases to VCC(OFF), the control circuit stops operation. After that, the IC reverts to the initial state by UVLO circuit, and the IC starts operation when VCC pin voltage increases to VCC(ON) by startup current. Thus the intermittent operation by UVLO is repeated in OLP state without latched operation as shown in Figure 9-32. The intermittent oscillation is determined by the cycle of the charge and discharge of the capacitor C3 connected to the VCC pin. In this case, the charge time is determined by the startup current from the startup circuit, while the discharge time is determined by the current supply to the internal circuits of the IC. ns (10)  10 rN t DLY ≒ fo t DLY V ≒ GND FB/OLP 4 5 PC1 ec om m IFB en d 9.14 Thermal Shutdown (TSD) C5 220kΩ When the temperature of control circuit increases to Tj(TSD) = 135 °C (min.) or more, Thermal Shutdown (TSD) is activated, the IC stops switching operation at the latched state. In order to keep the latched state, when VCC pin voltage decreases to VCC(BIAS), the bias assist function is activated and VCC pin voltage is kept to over the VCC(OFF). R Figure 9-31 FB/OLP pin peripheral circuit (without latched operation) N ot VCC pin voltage VCC(ON) VCC(OFF) FB/OLP pin voltage VFB(OLP) Drain current, ID Figure 9-32 OLP operation waveform at output shorted (without latched operation) STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 24 STR-Y6700 Series transformer matching what will be used in the actual application, because the variation of the auxiliary winding voltage is affected by the transformer structural design. 10. Design Notes 10.1 External Components Take care to use properly rated, including derating as necessary and proper type of components. CRD clamp snubber BR1 VCC pin voltage Without R2 T1 VAC R1 P C2 C1 With R2 U1 D2 ns D1 R2 D/ST 2 S/OCP VCC GND FB/OLP BD NF es ig Output current, IOUT C3 D Figure 10-2 Variation of VCC pin voltage and power DZBD CV D 2 3 4 5 6 7 RBD1 CBD C4 C5 ew R3 ROCP RBD2 PC1 rN C(RC) damper snubber • FB/OLP Pin Peripheral Circuit C5 is for high frequency noise reduction and phase compensation, and should be connected close to these pins. The value of C5 is recommended to be about 470 pF to 0.01µF, and should be selected based on actual operation in the application. C4 is for the OLP delay time, tDLY, setting (refer to Section 9.12). Figure 10-1 The IC peripheral circuit fo 1 The recommended value of R3 is 47 kΩ. en d ed • Input and Output Electrolytic Capacitor Apply proper derating to ripple current, voltage, and temperature rise. Use of high ripple current and low impedance types, designed for switch mode power supplies, is recommended. R ec om m • S/OCP Pin Peripheral Circuit In Figure 10-1, ROCP is the resistor for the current detection. A high frequency switching current flows to ROCP, and may cause poor operation if a high inductance resistor is used. Choose a low inductance and high surge-tolerant type. N ot • VCC Pin Peripheral Circuit The value of C3 in Figure 10-1 is generally recommended to be 10µ to 47μF (refer to Section 9.1 Startup Operation”, because the startup time is determined by the value of C3). In actual power supply circuits, there are cases in which the VCC pin voltage fluctuates in proportion to the output current, IOUT (see Figure 10-2), and the Overvoltage Protection function (OVP) on the VCC pin may be activated. This happens because C3 is charged to a peak voltage on the auxiliary winding D, which is caused by the transient surge voltage coupled from the primary winding when the power MOSFET turns off. For alleviating C3 peak charging, it is effective to add some value R2, of several tenths of ohms to several ohms, in series with D2 (see Figure 10-1). The optimal value of R2 should be determined using a STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 • BD Pin Peripheral Circuit Since BD pin detects the signal of bottom-on timing and input compensation of OCP1, the values of BD pin peripheral components (DZBD, RBD1, RBD2 and CBD) are considered about both functions and should be adjusted. Refer to Section 9.7.2 and Section 9.11.3. • NF Pin For stable operation, NF pin should be connected to GND pin, using the shortest possible path. • Snubber Circuit When the surge voltage of VDS is large, the circuit should be added as follows (see Figure 10-1); ・ A clamp snubber circuit of a capacitor-resistordiode (CRD) combination should be added on the primary winding P. ・ A damper snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the D/ST pin and the S/OCP pin. When the damper snubber circuit is added, this components should be connected near D/ST pin and S/OCP pin. • Peripheral Circuit of Secondary Side Shunt Regulator Figure 10-3 shows the secondary side detection circuit with the standard shunt regulator IC (U51). SANKEN ELECTRIC CO., LTD. 25 STR-Y6700 Series C52 and R53 are for phase compensation. The value of C52 and R53 are recommended to be around 0.047 μF to 0.47 μF and 4.7 kΩ to 470 kΩ, respectively. They should be selected based on actual operation in the application. should be maximized. ▫ The coupling of the winding D and the winding P should be minimized. In the case of multi-output power supply, the coupling of the secondary-side stabilized output winding, S1, and the others (S2, S3…) should be maximized to improve the line-regulation of those outputs. Figure 10-4 shows the winding structural examples of two outputs. Winding structural example (a): S1 is sandwiched between P1 and P2 to maximize the coupling of them for surge reduction of P1 and P2. D is placed far from P1 and P2 to minimize the coupling to the primary for the surge reduction of D. Winding structural example (b) P1 and P2 are placed close to S1 to maximize the coupling of S1 for surge reduction of P1 and P2. D and S2 are sandwiched by S1 to maximize the coupling of D and S1, and that of S1 and S2. This structure reduces the surge of D, and improves the line-regulation of outputs. L51 VOUT (+) R55 R52 C53 es ig C51 S ns PC1 R54 R51 R56 ew U51 D C52 R53 rN (-) Margin tape Winding structural example (a) Margin tape P1 S1 D S2 S1 P2 Margin tape Winding structural example (b) Figure 10-4 Winding structural examples N ot In the following cases, the surge of VCC pin voltage becomes high. ▫ The surge voltage of primary main winding, P, is high (low output voltage and high output current power supply designs) ▫ The winding structure of auxiliary winding, D, is susceptible to the noise of winding P. P1 S1 P2 S2 D Margin tape R ec om m en d ed • Transformer Apply proper design margin to core temperature rise by core loss and copper loss. Because the switching currents contain high frequency currents, the skin effect may become a consideration. Choose a suitable wire gauge in consideration of the RMS current and a current density of 4 to 6 A/mm2. If measures to further reduce temperature are still necessary, the following should be considered to increase the total surface area of the wiring: ▫ Increase the number of wires in parallel. ▫ Use litz wires. ▫ Thicken the wire gauge. fo Figure 10-3 Peripheral circuit of secondary side shunt regulator (U51) Bobbin D51 Bobbin T1 When the surge voltage of winding D is high, the VCC pin voltage increases and the Overvoltage Protection function (OVP) may be activated. In transformer design, the following should be considered; ▫ The coupling of the winding P and the secondary output winding S should be maximized to reduce the leakage inductance. ▫ The coupling of the winding D and the winding S STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 26 STR-Y6700 Series where, VIN(MIN) : C1 voltage at the minimum AC input voltage DON: On-duty at the minimum input voltage PO: maximum output power fMIN: minimum operation frequency η1: transformer efficiency CV: the voltage resonance capacitor connected between the drain and source of the power MOSFET 10.2 Transformer Design The design of the transformer is fundamentally the same as the power transformer of a Ringing Choke Converter (RCC) system: a self-excitation type flyback converter. However, because the duty cycle will change due to the quasi-resonant operations delaying the turn-on, the duty cycle needs to be compensated. Figure 10-5 shows the quasi-resonant circuit. Each parameter, such as the peak drain current, I DP, is calculated by the following formulas: VF IOFF S t ONDLY  π L P 'C V VO C51 NP NS CV U1 fo The on duty, DON, at the minimum AC input voltage is calculated as follows: VFLY VIN( MIN)  VFLY NS  N The inductance, LP' on the primary side, taking into consideration the delay time, is calculated using Equation (14). LP '  IN ( MIN)  D ON  2  2PO  f MIN    VIN( MIN)  D ON  f MIN  π C V    η1   STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 2 (14) LP ' Al‐value (19) N P  VO  VF  VFLY (20) where, tONDLY: Delay time of quasi-resonant operation IIN: Average input current η2: conversion efficiency of the power supply IDP: peak drain current DON’: On-duty after compensation VO: Secondary side output voltage The minimum operation frequency, fMIN, can be calculated by the Equation (22):  ot R (13) where, VIN(MIN): C1 voltage at the minimum AC input voltage VFLY: Flyback voltage. V 2  I IN D ON ' rN ec om m en d ed (12) where, NP: Primary side number of turns NS: Secondary side number of turns VO: Output voltage VF: Forward voltage drop of D51 D ON  (18) NP  N VFLY  P  VO  VF  NS (16) (17) I DP  The flyback voltage, VFLY is calculated as follows: (15) PO 1  η2 VIN(MIN) I IN  Figure 10-5 Quasi-resonant circuit es ig D ON '  D ON 1  f MIN  t ONDLY  VIN D P ew VFLY C1 ID D51 ns T1 LP f MIN  2  2PO 2PO 4π VIN( MIN)  D ON  C V      η1 η1 LP'   2π C V  VIN( MIN)  D ON            2 (21) Figure 10-6 shows the Example of NI-Limit versus AL-Value characteristics. Choose the ferrite core that does not saturate and provides a design margin in consideration of temperature effects and other variations to NI-Limit versus AL-Value characteristics. SANKEN ELECTRIC CO., LTD. 27 STR-Y6700 Series Al-value is calculated by using LP’ and NP. NI is calculated by using Equation (22). It is recommended that Al-value and NI provide the design margin of 30 % or more for saturation curve of core. NI  N P  I DP (AT) (2) Control Ground Trace Layout Since the operation of IC may be affected from the large current of the main trace that flows in control ground trace, the control ground trace should be separated from main trace and connected at a single point grounding of point A in Figure 10-7 as close to the ROCP pin as possible. (22) (3) VCC Trace Layout This is the trace for supplying power to the IC, and thus it should be as small loop as possible. If C3 and the IC are distant from each other, placing a capacitor such as film capacitor Cf (about 0.1 μF to 1.0 μF) close to the VCC pin and the GND pin is recommended. where, NP: Primary side number of turns IDP: Peak switching current ns Saturation curve es ig (4) ROCP Trace Layout ROCP should be placed as close as possible to the S/OCP pin. The connection between the power ground of the main trace and the IC ground should be at a single point ground (point A in Figure 10-7) which is close to the base of ROCP. D NI ew NI-limit (AT) Margin : about 30% rN LP’/NP2 ed Figure 10-6 Example of NI-Limit versus AL-Value characteristics (5) Peripheral components of the IC The components for control connected to the IC should be placed as close as possible to the IC, and should be connected as short as possible to the each pin. fo Al-value (nH/T2) en d 10.3 PCB Trace Layout and Component Placement ec om m Since the PCB circuit trace design and the component layout significantly affects operation, EMI noise, and power dissipation, the high frequency PCB trace should be low impedance with small loop and wide trace. In addition, the ground traces affect radiated EMI noise, and wide, short traces should be taken into account. Figure 10-7 shows the circuit design example. N ot R (1) Main Circuit Trace Layout This is the main trace containing switching currents, and thus it should be as wide trace and small loop as possible. If C1 and the IC are distant from each other, placing a capacitor such as film capacitor (about 0.1 μF and with proper voltage rating) close to the transformer or the IC is recommended to reduce impedance of the high frequency current loop. STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 (6) Secondary Rectifier Smoothing Circuit Trace Layout: This is the trace of the rectifier smoothing loop, carrying the switching current, and thus it should be as wide trace and small loop as possible. If this trace is thin and long, inductance resulting from the loop may increase surge voltage at turning off the power MOSFET. Proper rectifier smoothing trace layout helps to increase margin against the power MOSFET breakdown voltage, and reduces stress on the clamp snubber circuit and losses in it. (7) Thermal Considerations Because the power MOSFET has a positive thermal coefficient of RDS(ON), consider it in thermal design. Since the copper area under the IC and the D/ST pin trace act as a heatsink, its traces should be as wide as possible. SANKEN ELECTRIC CO., LTD. 28 STR-Y6700 Series (1) Main trace should be wide trace and small loop (6) Main trace of secondary side should be wide trace and small loop T1 C2 D51 R1 P C1 D1 C51 D2 U1 ns D es ig D/ST 2 S/OCP VCC GND FB/OLP BD NF C3 DZBD ROCP RBD1 R3 C5 PC1 CBD rN RBD2 (2) Control GND trace should be connected at a single point as close to the ROCP as possible CY (5)The components connected to the IC should be as close to the IC as possible, and should be connected as short as possible ed (4)ROCP should be as close to S/OCP pin as possible. fo C4 A ew D CV (7)Trace of D/ST pin should be wide for heat release R2 (3) Loop of the power supply should be small 2 3 4 5 6 7 1 S N ot R ec om m en d Figure 10-7 Peripheral circuit example around the IC STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 29 STR-Y6700 Series 11. Pattern Layout Example en d ed fo rN ew D es ig ns The following show the four outputs PCB pattern layout example and the schematic of circuit using STR-Y6700 series. The PCB pattern layout example is made usable to other ICs in common. The parts in Figure 11-2 are only used. CN1 ec om m Figure 11-1 PCB circuit trace layout example CN52 1 OUT1(+) D50 T1 S1 C53 C50 C58 TH2 2 RC1 L1 J2 C4 C1 TH1 F1 L51 J53 R 1 D6 P1 TK1 8 OUT2(-) S2 R52 C54 R51 ot J54 R57 R50 R9 PC1 R53 R58 C59 R56 R55 R54 C62 J56 F2 J55 R59 D55 N OUT1(-) OUT2(+) C51 C12 R7 R8 C6 C2 2 3 D51 C3 4 OUT3(+) D2 D52 D3 S3 IC1 D5 Q1 R5 C8 D/ST 2 S/OCP VCC GND FB/OLP BD NF D10 L50 S4 C52 2 PC1 C9 C10 OUT4(-) 9 OUT5(+) D53 S5 C7 C63 D7 R11 R2 7 OUT4(+) C57 C65 R3 OUT3(-) J50 J51 J52 R6 C11 C5 R1 C60 D54 D D4 2 3 4 5 6 7 1 C64 5 D1 R4 STR-Y6700 C55 R10 C56 C61 J57 R12 6 C13 OUT5(-) TK50 Figure 11-2 Circuit schematic for PCB circuit trace layout STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 30 STR-Y6700 Series 12. Reference Design of Power Supply  Power supply specification IC Input voltage Maximum output power Output 1 Output 2 STR-Y6754 85 VAC to 265 VAC 40.4 W 14 V / 2.6A 8 V / 0.5 A  Circuit schematic D2 D4 D3 T1 S2 S4 C1 C3 C2 R1 D51 OUT1(+) 14V/2.6A C53 C51 P1 F1 ns D1 L1 es ig D52 OUT2(+) D5 R51 C52 P2 PC1 D6 R3 D/ST 2 S/OCP VCC GND FB/OLP BD NF DZ1 C4 R6 C8 C7  Bill of materials Recommended Sanken Parts Ratings(1) Film, X2 Electrolytic Ceramic Ceramic Electrolytic Ceramic Ceramic Ceramic Ceramic, Y1 Ceramic Ceramic Electrolytic Electrolytic Ceramic General General General 0.1 μF, 275 V 220 μF, 400 V 2200 pF, 630 V 100 pF, 2 kV 22 μF, 50V 4.7 μF, 16 V 4700 pF, 50V 470 pF, 50V 2200 pF, 250 V 2200 pF, 1 kV Open 1000 μF, 50 V 470 µF, 16 V 0.1 µF 600V, 1A 600V, 1A 600V, 1A EM01A EM01A EM01A D4 General 600V, 1A EM01A T1 Transformer D5 Fast recovery 1000 V, 0.5 A EG01C U1 IC D6 Fast recovery 200 V, 1 A AL01Z U51 Shunt regulator ec om m (2) (2) R (2) N ot C1 C2 C3 C4 C5 C6 C7 C8 C9 C51 C52 C53 C54 C55 D1 D2 D3 en d Part type Symbol OUT(-) C9 ed C6 R56 fo PC1 R4 S3 rN S1 R5 R2 ew U51 C5 2 3 4 5 6 7 1 R55 R53 C55 D STR-Y6700 R52 8V/0.5A D U1 C54 R54 Symbol D52 DZ1 F1 L1 PC1 R1 R2 R3 R4 R5 R6 R51 R52 R53 R54 R55 R56 (2) (3) (2) (2) (2) (2) (2) Part type Schottky Zener Fuse CM inductor Photo-coupler Metal oxide General General General General General General General General General General, 1% General, 1% Ratings(1) 90 V, 1.5 A 22V 250 VAC, 3 A 3.3 mH PC123or equiv 150 kΩ, 1 W 0.56 Ω, 1 W 15 Ω 47 kΩ 6.8 kΩ 1 kΩ 820 Ω 1.5 kΩ 22 kΩ 6.8 kΩ 39 kΩ 10 kΩ See the specification － VREF = 2.5 V TL431or equiv Recommended Sanken Parts EK 19 STR-Y6754 D51 Schottky 150 V, 10 A FMEN-210B Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less. (2) It is necessary to be adjusted based on actual operation in the application. (3) Resistors applied high DC voltage and of high resistance are recommended to select resistors designed against electromigration or use combinations of resistors in series for that to reduce each applied voltage, according to the requirement of the application. (1) STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 31 STR-Y6700 Series  Transformer specification ▫ Primary inductance, LP: 0.95 mH ▫ Core size: EER28L ▫ AL-value: 183 nH/N2 (Center gap of about 0.8 mm) ▫ Winding specification Number of Winding Symbol turns (T) Wire diameter P1 43 1EUW – φ 0.30 Primary winding 2 P2 29 1EUW – φ 0.30 Auxiliary winding D 12 TEX – φ 0.23 × 2 Output winding 1 S1 5 φ 0.32 × 2 Output winding 2 S2 3 φ 0.32 × 2 Output winding 3 S3 5 φ 0.32 × 2 Output winding 4 S4 3 φ 0.32 × 2 es ig D ew rN P2 ed P1 S3 S1 P2 D S2 S3 OUT2(+) 8V GND ec om m Bobbin D/ST VCC en d D S2 S4 OUT1(+) 14V fo P1 S4 Two-layer, solenoid winding Single-layer, solenoid winding Single-layer, Space winding Single-layer, solenoid winding Single-layer, solenoid winding Single-layer, solenoid winding Single-layer, solenoid winding ns Primary winding 1 VDC Construction (mm) S1 Cross-section view OUT(-) N ot R : Start at this pin STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 32 STR-Y6700 Series Important Notes N ot R ec om m en d ed fo rN ew D es ig ns ● All data, illustrations, graphs, tables and any other information included in this document (the “Information”) as to Sanken’s products listed herein (the “Sanken Products”) are current as of the date this document is issued. The Information is subject to any change without notice due to improvement of the Sanken Products, etc. Please make sure to confirm with a Sanken sales representative that the contents set forth in this document reflect the latest revisions before use. ● The Sanken Products are intended for use as components of general purpose electronic equipment or apparatus (such as home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Prior to use of the Sanken Products, please put your signature, or affix your name and seal, on the specification documents of the Sanken Products and return them to Sanken. When considering use of the Sanken Products for any applications that require higher reliability (such as transportation equipment and its control systems, traffic signal control systems or equipment, disaster/crime alarm systems, various safety devices, etc.), you must contact a Sanken sales representative to discuss the suitability of such use and put your signature, or affix your name and seal, on the specification documents of the Sanken Products and return them to Sanken, prior to the use of the Sanken Products. The Sanken Products are not intended for use in any applications that require extremely high reliability such as: aerospace equipment; nuclear power control systems; and medical equipment or systems, whose failure or malfunction may result in death or serious injury to people, i.e., medical devices in Class III or a higher class as defined by relevant laws of Japan (collectively, the “Specific Applications”). Sanken assumes no liability or responsibility whatsoever for any and all damages and losses that may be suffered by you, users or any third party, resulting from the use of the Sanken Products in the Specific Applications or in manner not in compliance with the instructions set forth herein. ● In the event of using the Sanken Products by either (i) combining other products or materials or both therewith or (ii) physically, chemically or otherwise processing or treating or both the same, you must duly consider all possible risks that may result from all such uses in advance and proceed therewith at your own responsibility. ● Although Sanken is making efforts to enhance the quality and reliability of its products, it is impossible to completely avoid the occurrence of any failure or defect or both in semiconductor products at a certain rate. You must take, at your own responsibility, preventative measures including using a sufficient safety design and confirming safety of any equipment or systems in/for which the Sanken Products are used, upon due consideration of a failure occurrence rate and derating, etc., in order not to cause any human injury or death, fire accident or social harm which may result from any failure or malfunction of the Sanken Products. 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DSGN-CEZ-16003 STR-Y6700 - DS Rev.4.2 Mar. 17, 2020 SANKEN ELECTRIC CO., LTD. 33