Off-Line PWM Controllers with Integrated Power MOSFET
STR4A100 Series
Data Sheet
Description
Package
The STR4A100 series are power ICs for switching
power supplies, incorporating a sense MOSFET and a
current mode PWM controller IC.
The low standby power is accomplished by the
automatic switching between the PWM operation in
normal operation and the burst-oscillation under light
load conditions. The product achieves high
cost-performance power supply systems with few
external components.
DIP8
Not to Scale
Lineup
● Electrical Characteristics
Features
VD/ST(max.) = 730 V
● Current Mode Type PWM Control
● Auto Standby Function
No Load Power Consumption < 10 mW
● Operation Mode
Normal Operation: PWM Mode
Standby : Burst Oscillation Mode
● Random Switching Function
● Slope Compensation Function
● Leading Edge Blanking Function
● Bias Assist Function
● Soft Start Function
● Protections
− Overcurrent Protection (OCP) : Pulse-by-Pulse,
built-in compensation circuit to minimize OCP point
variation on AC input voltage
− Overload Protection (OLP) : Aauto-restart
− Overvoltage Protection (OVP) : Auto-restart
− Thermal Shutdown (TSD) : Auto-restart with
hysteresis
Products
Package
STR4A162S
SOIC8
STR4A162D
PC1
P
U1
D1
S
4
S/GND
8
S/GND
FB/OLP
100kHz
Adapter
0.520 A
12.9 Ω
0.485 A
Open frame
AC230V
AC85
~265V
AC230V
AC85
~265V
STR4A162S
5W
4W
7W
5.5 W
STR4A162D
5.5 W
4.5 W
7.5 W
6W
STR4A164D
8W
6W
10 W
8.5 W
STR4A164HD
9W
7W
13 W
10.5 W
* The output power is actual continues power that is measured at
Application
R54
R51
R52
U51
D2
VCC
DIP8
Products
C53
C52 R53
6
S/GND
12.9 Ω
● Output Power, POUT*
R55
C51
STR4A100
7
0.365 A
VOUT
(+)
R1
C5
C1
5
24.6 Ω
L2
D51
T1
D/ST
IDLIM(H)
65kHz
DIP8
STR4A164HD
RDS(ON)
(max.)
50 °C ambient. The peak output power can be 120 to 140 % of the
value stated here. Core size, duty cycle, and thermal design affect
the output power. It may be less than the value stated here.
BR1
S/GND
fOSC(AVG)
STR4A164D
Typical Application
VAC
SOIC8
R2
R56
(-)
2
C2
1
D
●
●
●
●
●
White goods
Auxiliary power for Flat TVs
Low power AC/DC adapter
Battery Chargers
Other SMPS
PC1
C3
C6
TC_STR4A100_1_R1
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
1
STR4A100 Series
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings----------------------------------------------------------------------------- 3
2. Recommended Operating Conditions ----------------------------------------------------------------- 3
3. Electrical Characteristics -------------------------------------------------------------------------------- 4
4. Performance Curves -------------------------------------------------------------------------------------- 6
5. Block Diagram --------------------------------------------------------------------------------------------- 7
6. Pin Configuration Definitions--------------------------------------------------------------------------- 7
7. Typical Application --------------------------------------------------------------------------------------- 8
8. Physical Dimensions and Marking Diagrams-------------------------------------------------------- 9
8.1 DIP8 ---------------------------------------------------------------------------------------------------- 9
8.2 SOIC8------------------------------------------------------------------------------------------------ 10
9. Operational Description ------------------------------------------------------------------------------- 11
9.1 Startup Operation --------------------------------------------------------------------------------- 11
9.2 Undervoltage Lockout (UVLO) ---------------------------------------------------------------- 11
9.3 Bias Assist Function ------------------------------------------------------------------------------ 11
9.4 Soft Start Function -------------------------------------------------------------------------------- 12
9.5 Constant Output Voltage Control-------------------------------------------------------------- 12
9.6 Leading Edge Blanking Function -------------------------------------------------------------- 13
9.7 Random Switching Function -------------------------------------------------------------------- 13
9.8 Automatic Standby Mode Function ----------------------------------------------------------- 13
9.9 Overcurrent Protection (OCP) ----------------------------------------------------------------- 14
9.9.1
OCP Operation ------------------------------------------------------------------------------ 14
9.9.2
OCP Input Compensation Function ----------------------------------------------------- 14
9.10 Overload Protection (OLP)---------------------------------------------------------------------- 14
9.11 Overvoltage Protection (OVP) ------------------------------------------------------------------ 15
9.12 Thermal Shutdown (TSD) ----------------------------------------------------------------------- 15
10. Design Notes ---------------------------------------------------------------------------------------------- 16
10.1 External Components ---------------------------------------------------------------------------- 16
10.1.1 Input and Output Electrolytic Capacitor ----------------------------------------------- 16
10.1.2 FB/OLP Pin Peripheral Circuit ---------------------------------------------------------- 16
10.1.3 VCC Pin Peripheral Circuit --------------------------------------------------------------- 16
10.1.4 D/ST Pin --------------------------------------------------------------------------------------- 17
10.1.5 Peripheral circuit of secondary side shunt regulator --------------------------------- 17
10.1.6 Transformer ---------------------------------------------------------------------------------- 17
10.2 PCB Trace Layout and Component Placement --------------------------------------------- 18
11. Pattern Layout Example ------------------------------------------------------------------------------- 20
12. Reference Design of Power Supply ------------------------------------------------------------------ 21
Important Notes ---------------------------------------------------------------------------------------------- 23
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
2
STR4A100 Series
1.
Absolute Maximum Ratings
● The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.
● Unless otherwise specified TA = 25 °C, pin 5 = pin 6 = pin 7 = pin 8
Parameter
Symbol
Test Conditions
Pins
Rating
Units
FB/OLP Pin Voltage
VFB
1–8
−0.3 to 14
V
FB/OLP Pin Sink Current
IFB
1–8
1.0
mA
VCC Pin Voltage
VCC
2–8
32
V
D/ST Pin Voltage
VD/ST
4–8
−0.3 to 730
V
−0.2 to 0.66
Drain Peak Current
IDP
Positive: Single pulse
Negative: Within 2μs of
pulse width
4–8
4A162S
−0.2 to 0.7
A
4A162D
4A164D
4A164HD
4A162S
W
4A162D
4A164D
4A164HD
−0.2 to 0.98
1.34
Power Dissipation(1)
PD
4–8
(2)
1.49
1.55
Operating Ambient
Temperature
Storage Temperature
Junction Temperature
(1)
(2)
Remarks
TOP
—
−40 to 125
°C
Tstg
—
−40 to 125
°C
Tj
—
150
°C
Refer to Section 4 MOSFET Temperature versus Power Dissipation Curve
When embedding this hybrid IC onto the printed circuit board (cupper area in a 15mm×15mm)
2. Recommended Operating Conditions
Recommended operating conditions means the operation conditions maintained normal function shown in electrical
characteristics.
Parameter
Symbol
Min.
Max.
Units
D/ST Pin Voltage in Operation
VD/ST(OP)
−0.3
584
V
VCC Pin Voltage in Operation
VCC(OP)
11
27
V
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
Remarks
3
STR4A100 Series
3.
Electrical Characteristics
● The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC
● Unless otherwise specified, TA = 25 °C, VCC = 18 V,pin 5 = pin 6 = pin 7 = pin 8, VFB = 3 V, VD/ST = 10 V
Parameter
Symbol
Conditions
Pins
Min.
Typ.
Max.
Units
Remarks
2−8
13.8
15.2
16.8
V
2−8
7.3
8.1
8.9
V
VCC = 12 V
2−8
—
—
2.5
mA
VFB = 0 V
VCC = 13.5 V
VFB = 0 V
VCC = 13.5 V
VD/ST = 100 V
4−8
19
29
39
V
2−8
−3.7
−2.1
−0.9
mA
VFB = 0 V
2−8
7.9
9.4
10.5
V
58
65
72
90
100
110
—
5
—
—
7
—
65
74
83
65
73
82
—
290
—
—
250
—
—
36
—
0.290
0.322
0.354
0.413
0.459
0.505
0.385
0.428
0.471
4A164HD
0.336
0.365
0.394
4A162S/ 62D
0.478
0.520
0.562
0.446
0.485
0.524
Power Supply Startup Operation
Operation Start Voltage
VCC(ON)
Operation Stop Voltage(1)
VCC(OFF)
Circuit Current in Operation
Startup Circuit Operation
Voltage
Startup Current
ICC(ON)
VSTARTUP
ISTARTUP
Startup Current Biasing
Threshold Voltage(1)
PWM Operation
Average PWM Switching
Frequency
PWM Frequency Modulation
Deviation
Maximum Duty Cycle
VCC(BIAS)
VFB = 0 V
4−8
fOSC(AVG)
Δf
4−8
4−8
DMAX
kHz
4A162S
/ 62D/ 64D
4A164HD
kHz
4A162S
/ 62D/ 64D
4A164HD
%
4A162S
/ 62D/ 64D
4A164HD
Protection Function
Leading
Time(2)
Edge
Blanking
Drain Current Limit
Compensation Duty Cycle(2)
Drain Current Limit
(Duty Cycle = 0 %)
Drain Current Limit
(Duty Cycle ≥ 36 %)
—
tBW
—
DDPC
4−8
IDLIM(L)
4−8
IDLIM(H)
ns
4A164HD
%
4A162S/ 62D
A
A
IFB(MAX)
VCC = 12 V
VFB = 0 V
1−8
−120
−77
−45
µA
Minimum Feedback Current
FB/OLP Pin Oscillation Stop
Threshold Voltage
OLP Threshold Voltage
IFB(MIN)
VFB = 6.8 V
1−8
−28
−13
−6
µA
VFB(OFF)
1−8
0.98
1.23
1.48
V
VFB(OLP)
1−8
7.3
8.1
8.9
V
OLP Operation Current
ICC(OLP)
2−8
—
230
—
µA
(2)
4A164D
4A164D
4A164HD
Maximum Feedback Current
(1)
4A162S
/ 62D/ 64D
VCC(BIAS) > VCC(OFF) always
Design assurance
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
4
STR4A100 Series
Parameter
OLP Delay Time
FB/OLP Pin Clamp Voltage
OVP Threshold Voltage
Thermal Shutdown
Operating Temperature(2)
Thermal Shutdown
Hysteresis(2)
MOSFET
Drain Leakage Current
Symbol
Pins
Min.
Typ.
Max.
Units
tOLP
—
58
76
94
ms
VFB(CLAMP)
1−8
10.5
12.0
13.5
V
VCC(OVP)
2−8
27.5
29.5
31.5
V
Tj(TSD)
—
135
—
—
°C
Tj(TSDHYS)
—
—
70
—
°C
4−8
—
—
50
µA
—
21.0
24.6
—
11.0
12.9
—
—
250
—
—
18
—
—
21
—
—
16
4A164D
/ 64HD
—
—
15
4A162D
—
—
16
—
—
15
IDSS
Conditions
Ta = 125 °C
VFB = 0 V
VD/ST = 584 V
ID = 37 mA
On Resistance
RDS(ON)
Switching Time
4−8
ID = 52 mA
4−8
tf
Ω
Remarks
4A162××
4A164××
ns
Thermal Characteristics
θj-F
Thermal Resistance
(3)
—
4A162D
°C/W
(2)
θj-C
(4)
—
°C/W
4A162S
4A162S
4A164D
/ 64HD
θj-F is thermal resistance between junction of MIC and frame. Frame temperature (TF) is measured at the root of the
pin 7 (S/GND).
(4)
θj-C is thermal resistance between junction of MIC and case. Case temperature (TC) is measured at the center of the
case top surface
(3)
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
5
STR4A100 Series
4.
Performance Curves
⚫ STR4A162S
Ambient Temperature versus
Power Dissipation Curve
Transient Thermal Resistance Curve
1.6
10
PD = 1.34 W
1.2
Transient Thermal Resistance
θj-c (°C /W)
Power Dissipation, PD (W)
1.4
1
0.8
0.6
0.4
0.2
0
0
25
50
75
100 125 150
1
0.1
0.01
1μ
1.0E-06
10μ
1.0E-05
100μ
1.0E-04
Ambient Temperature, TA (°C )
1m
1.0E-03
10m
1.0E-02
100m
1.0E-01
10m
1.0E-02
100m
1.0E-01
1.0E-02
10m
1.0E-01
100m
Time (s)
⚫ STR4A162D
Ambient Temperature versus
Power Dissipation Curve
Transient Thermal Resistance Curve
10
1.6
PD = 1.49 W
Transient Thermal Resistance
θj-c (°C /W)
Power Dissipation, PD (W)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1
0.1
0.01
0
25
50
75
100
125
1μ
1.0E-06
150
10μ
1.0E-05
100μ
1.0E-04
Ambient Temperature, TA (°C )
1m
1.0E-03
Time (s)
⚫ STR4A164D / 64HD
Ambient Temperature versus
Power Dissipation Curve
Transient Thermal Resistance Curve
1.8
Power Dissipation, PD (W)
Transient Thermal Resistance
θj-c (°C /W)
10
1.6
PD = 1.55 W
1.4
1.2
1
0.8
0.6
0.4
1
0.1
0.2
0
0
25
50
75
100 125 150
0.01
1.0E-06
1μ
1.0E-05
10μ
1.0E-04
100μ
Ambient Temperature, TA (°C )
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
1.0E-03
1m
Time (s)
6
STR4A100 Series
5.
Block Diagram
VCC
D/ST
2
STARTUP
UVLO
REG
PWM OSC
S Q
VREG
OVP
4
TSD
DRV
R
OCP
VCC
OLP
Feedback
Control
FB/OLP
Drain Peak Current
Compensation
LEB
1
Slope
Compensation
5~8
S/GND
BD_STR4A100_R1
6.
Pin Configuration Definitions
Pin
Name
FB/OLP
1
8
S/GND
1
FB/OLP
VCC
2
7
S/GND
2
VCC
3
6
S/GND
3
―
4
4
D/ST
5
S/GND
D/ST
Descriptions
Input of constant voltage control signal and
Overload Protection (OLP) signal
Power supply voltage input for Control Part and
Overvoltage Protection (OVP) signal input
(Pin removed)
MOSFET drain and startup current input
5
6
7
S/GND
MOSFET source and ground
8
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
7
STR4A100 Series
7.
Typical Application
The PCB traces of the S/GND pins should be as wide as possible, in order to enhance thermal dissipation.
In applications having a power supply specified such that D/ST pin has large transient surge voltages, a clamp
snubber circuit of a capacitor-resistor-diode (CRD) combination should be added on the primary winding P, or a
damper snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the D/ST
pin and the S/GND pin.
VAC
CRD clamp snubber
BR1
C1
C（RC）
Damper snubber
L2
D51
T1
VOUT
(+)
R1
C5
PC1
P
C4
R55
C51
D1
U1
S/GND
5
D/ST
S
S/GND
7
8
R52
U51
D2
VCC
S/GND
FB/OLP
C53
C52 R53
4
6
S/GND
R54
R51
R2
R56
(-)
2
C2
1
D
PC1
STR4A100
C3
C6
TC_STR4A100_2_R1
Figure 7-1. Typical Application
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
8
STR4A100 Series
8.
8.1
Physical Dimensions and Marking Diagrams
DIP8
● Physical Dimensions
9.4±0.3
5
1
4
6.5 ±0.2
8
1.52 +0.3
-0.05
7.6 TYP
3.3 ±0.2
4.2±0.3
3.4 ±0.1
7.5±0.5
1.0 +0.3
-0.05
0.2 +0
5 .1
-0.
05
2.54 TYP
０～１５°
０～１５°
0.89 TYP
0.5±0.1
NOTES:
1) Units: mm
2) Pb-free. Device composition compliant with the RoHS directive
● Marking Diagram
DIP8
8
4A16××
Part Number
S KY MD
1
Lot Number
Y = Last Digit of Year (0-9)
M = Month (1-9,O,N or D)
D = Period of days (1 to 3)
1 : 1st to 10th
2 : 11th to 20th
3 : 21st to 31st
Sanken Control Number
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
9
STR4A100 Series
8.2
SOIC8
● Physical Dimensions
Land Pattern Example (not to scale)
NOTES:
1) Units: mm
2) Pb-free. Device composition compliant with the RoHS directive
1.6
3.8
1.27
0.61
Unit: mm
● Marking Diagram
SOIC8
8
4A16××
Part Number
S KY MD
1
Lot Number
Y = Last Digit of Year (0-9)
M = Month (1-9,O,N or D)
D = Period of days (1 to 3)
1 : 1st to 10th
2 : 11th to 20th
3 : 21st to 31st
Sanken Control Number
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
10
STR4A100 Series
9.
Operational Description
All of the parameter values used in these descriptions
are typical values, unless they are specified as minimum
or maximum.
With regard to current direction, "+" indicates sink
current (toward the IC) and "–" indicates source current
(from the IC).
9.1
Startup Operation
Figure 9-1 shows the circuit around the VCC pin.
The IC incorporates the startup circuit. The circuit is
connected to D/ST pin. When the D/ST pin voltage
reaches to Startup Circuit Operation Voltage
VSTARTUP = 29 V, the startup circuit starts operation.
During the startup process, the constant current,
ISTARTUP = −2.1 mA, charges C2 at the VCC pin. When
VCC pin voltage increases to VCC(ON) = 15.2 V, the
control circuit starts switching operation. During the IC
operation, the voltage rectified the auxiliary winding
voltage, VD, of Figure 9-1 becomes a power source to
the VCC pin. After switching operation begins, the
startup circuit turns off automatically so that its current
consumption becomes zero.
The startup time of the IC is determined by C2
capacitor value. The approximate startup time tSTART is
calculated as follows:
t START = C2 ×
VCC(ON) − VCC(INT)
|ISTARTUP |
(2)
Where,
tSTART : Startup time of the IC (s)
VCC(INT) : Initial voltage on the VCC pin (V)
9.2
Undervoltage Lockout (UVLO)
Figure 9-2 shows the relationship of the VCC pin
voltage and circuit current ICC. When VCC pin voltage
decreases to VCC(OFF) = 8.1 V, the control circuit stops
operation by UVLO (Undervoltage Lockout) circuit, and
reverts to the state before startup.
Circuit current, ICC
Stop
Start
T1
D1
VAC
C1
4
D/ST
U1
VCC
2
D2
C2
S/GND
VCC（OFF）
P
Figure 9-2. Relationship between
VCC Pin Voltage and ICC
R2
VD
D
9.3
5~8
Figure 9-1. VCC Pin Peripheral Circuit
The approximate value of auxiliary winding voltage is
15 to 20 V, taking account of the winding turns of D
winding so that the VCC pin voltage becomes Equation
(1) within the specification of input and output voltage
variation of power supply.
VCC(BIAS) (max. ) < VCC < VCC(OVP) (min. )
⇒ 10.5 (V) < VCC < 27.5 (V)
VCC（ON） VCC pin
voltage
(1)
Bias Assist Function
By the Bias Assist Function, the startup failure is
prevented.
When FB pin voltage is the FB/OLP Pin Oscillation
Stop Threshold Voltage, VFB(OFF)= 1.23 V or less and
VCC pin voltage decreases to the Startup Current
Biasing Threshold Voltage, VCC(BIAS) = 9.4 V, the Bias
Assist Function is activated.
When the Bias Assist Function is activated, the VCC
pin voltage is kept almost constant voltage, VCC(BIAS) by
providing the startup current, ISTARTUP, from the startup
circuit. Thus, the VCC pin voltage is kept more than
VCC(OFF).
Since the startup failure is prevented by the Bias
Assist Function, the value of C2 connected to the VCC
pin can be small. Thus, the startup time and the response
time of the Overvoltage Protection (OVP) become
shorter.
The operation of the Bias Assist Function in startup is
as follows. It is necessary to check and adjust the startup
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
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© SANKEN ELECTRIC CO., LTD. 2011
11
STR4A100 Series
process based on actual operation in the application, so
that poor starting conditions may be avoided.
Figure 9-3 shows the VCC pin voltage behavior
during the startup period.
After the VCC pin voltage increases to VCC(ON) = 15.2
V at startup, the IC starts the operation. Then circuit
current increases and the VCC pin voltage decreases. At
the same time, the auxiliary winding voltage, VD,
increases in proportion to output voltage. These are all
balanced to produce the VCC pin voltage.
When the VCC pin voltage is decrease to
VCC(OFF) = 8.1 V in startup operation, the IC stops
switching operation and a startup failure occurs.
When the output load is light at startup, the output
voltage may become more than the target voltage due to
the delay of feedback circuit. In this case, the FB pin
voltage is decreased by the feedback control. When the
FB pin voltage decreases to VFB(OFF) or less, the IC stops
switching operation and the VCC pin voltage decreases.
When the VCC pin voltage decreases to VCC(BIAS), the
Bias Assist function is activated and the startup failure is
prevented.
VCC pin
voltage
Startup success
Target operating
voltage
Increase with rising of
output voltage
Bias assist period
Startup failure
Time
Figure 9-3. VCC Pin Voltage During Startup Period
9.4
VCC pin
voltage
Startup of IC Startup of SMPS
Normal opertion
tSTART
VCC(ON)
VCC(OFF)
Time
D/ST pin
current, ID
Soft start period
approximately 6 ms (fixed)
IDLIM
tLIM < tOLP (min.)
Time
Figure 9-4. VCC and ID Behavior During Startup
9.5
Constant Output Voltage Control
IC starts operation
VCC(ON)
VCC(BIAS)
VCC(OFF)
winding D so that the tLIM is less than tOLP = 58 ms
(min.).
Soft Start Function
Figure 9-4 shows the behavior of VCC pin voltage
and drain current during the startup period.
The IC activates the soft start circuitry during the
startup period. Soft start time is fixed to around 6 ms.
during the soft start period, overcurrent threshold is
increased step-wisely (5 steps). This function reduces
the voltage and the current stress of a power MOSFET
and the secondary side rectifier diode.
Since the Leading Edge Blanking Function (refer to
Section 9.6) is deactivated during the soft start period,
there is the case that on time is less than the Leading
Edge Blanking Time, tBW. After the soft start period,
D/ST pin current, ID, is limited by the Drain Current
Limit, IDLIM, until the output voltage increases to the
target operating voltage. This period is given as tLIM. In
case tLIM is longer than the OLP Delay Time, tOLP, the
output power is limited by the Overload Protection
(OLP) operation. Thus, it is necessary to adjust the value
of output capacitor and the turn ratio of auxiliary
The IC achieves the constant voltage control of the
power supply output by using the current-mode control
method, which enhances the response speed and
provides the stable operation.
The FB/OLP pin voltage is internally added the slope
compensation at the feedback control (refer to Section
5.Block Diagram), and the target voltage, VSC, is
generated. The IC compares the voltage, VROCP, of a
current detection resistor with the target voltage, VSC, by
the internal FB comparator, and controls the peak value
of VROCP so that it gets close to VSC, as shown in Figure
9-5 and Figure 9-6.
● Light load conditions
When load conditions become lighter, the output
voltage, VOUT, increases. Thus, the feedback current
from the error amplifier on the secondary-side also
increases. The feedback current is sunk at the FB/OLP
pin, transferred through a photo-coupler, PC1, and the
FB/OLP pin voltage decreases. Thus, VSC decreases,
and the peak value of VROCP is controlled to be low,
and the peak drain current of ID decreases. This
control prevents the output voltage from increasing.
● Heavy load conditions
When load conditions become greater, the IC
performs the inverse operation to that described above.
Thus, VSC increases and the peak drain current of ID
increases.This control prevents the output voltage
from decreasing.
In the current mode control method, when the drain
current waveform becomes trapezoidal in continuous
operating mode, even if the peak current level set by the
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STR4A100 Series
target voltage is constant, the on-time fluctuates based
on the initial value of the drain current.
This results in the on-time fluctuating in multiples of
the fundamental operating frequency as shown in Figure
9-7. This is called the subharmonics phenomenon. In
order to avoid this, the IC incorporates the Slope Compensation Function. Because the target voltage is added
a down-slope compensation signal, which reduces the
peak drain current as the duty cycle gets wider relative
to the FB/OLP pin signal to compensate VSC, the
subharmonics phenomenon is suppressed. Even if
subharmonic oscillations occur when the IC has some
excess supply being out of feedback control, such as
during startup and load shorted, this does not affect
performance of normal operation.
STR4A100
FB Comp.
VROCP
FB/OLP
ROCP
9.6
Leading Edge Blanking Function
The constant voltage control of output of the IC uses
the peak-current-mode control method.
In peak-current-mode control method, there is a case
that the power MOSFET turns off due to unexpected
response of a FB comparator or Overcurrent Protection
(OCP) circuit to the steep surge current in turning on a
power MOSFET.
In order to prevent this response to the surge voltage
in turning-on the power MOSFET, the Leading Edge
Blanking Time, tBW, is built-in.
9.7
Random Switching Function
The IC modulates its switching frequency randomly
by superposing the modulating frequency on fOSC(AVG) in
normal operation. This function reduces the conduction
noise compared to others without this function, and
simplifies noise filtering of the input lines of power
supply.
S/GND
1
5~8
9.8
PC1
IFB
C3
Figure 9-5. FB/OLP Pin Peripheral Circuit
Target voltage including
slope compensation
-
VSC
+
VROCP
In light load, FB/OLP pin voltage according to
decreasing drain current, ID.
Automatic standby mode is activated automatically
when FB/OLP pin voltage decreases to VFB(OFF).
The operation mode becomes burst oscillation, as
shown in Figure 9-8.
Output current,
IOUT
Voltage on both
sides of ROCP
FB comparator
Automatic Standby Mode Function
Below several kHz
Drain current,
ID
Drain current,
ID
Normal
operation
Figure 9-6. Drain Current, ID, and FB Comparator
Operation in Steady Operation
Target voltage
without slope compensation
tON1
T
tON2
T
Burst oscillation
T
Figure 9-7. Drain Current, ID, Waveform in
Subharmonic Oscillation
Standby
operation
Normal
operation
Figure 9-8. Auto-standby Mode Timing
Burst oscillation mode reduces switching losses and
improves power supply efficiency because of periodic
non-switching intervals. Generally, in order to improve
efficiency under light load conditions, the frequency of
the burst oscillation mode becomes just a few kilohertz.
Because the IC suppresses the peak drain current well
during burst oscillation mode, audible noises can be
reduced. If VCC pin voltage decreases to VCC(BIAS) = 9.4
V during the transition to the burst oscillation mode, the
Bias Assist Function is activated and stabilizes the
Standby mode operation, because the Startup Current,
ISTARTUP is provided to the VCC pin so that the VCC pin
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voltage does not decrease to VCC(OFF).
However, if the Bias Assist Function is always
activated during steady-state operation including
standby mode, the power loss increases. Therefore, the
VCC pin voltage should be more than VCC(BIAS), for
example, by adjusting the turns ratio of the auxiliary
winding and the secondary-side winding and/or reducing
the value of R2 in Figure 10-2 (refer to Section 10.1
Peripheral Components for a detail of R2)
9.9
Overcurrent Protection (OCP)
Drain Current Limit after
compensation, IDLIM'
STR4A100 Series
0.520
STR4A164HD
0.459
0.428
0.4
0.365
STR4A162D/62S
DDPC=36%
0.322
0.3
9.9.1
STR4A164D
0.5
0.485
0
DMAX=74%
50
100
ON Duty (%)
OCP Operation
Overcurrent Protection (OCP) detects each drain peak
current level of a power MOSFET on pulse-by-pulse
basis, and limits the output power when the current level
reaches to OCP threshold voltage.
Figure 9-9. Relationship between Duty Cycle and
Drain Current Limit after Compensation
9.10 Overload Protection (OLP)
9.9.2
OCP Input Compensation Function
ICs with PWM control usually have some propagation
delay time. The steeper the slope of the actual drain
current at a high AC input voltage is, the larger the
actual drain peak current is, compared to the Drain
Current Limit. Thus, the peak current has some variation
depending on AC input voltage in OCP state. In order to
reduce the variation of peak current in OCP state, the IC
has Input Compensation Function. This function corrects
the Drain Current Limit depending on AC input voltage,
as shown in Figure 9-9.
When AC input voltage is low (Duty cycle is broad),
the Drain Current Limit is controlled to become high.
The difference of peak drain current become small
compared with the case where the AC input voltage is
high (Duty cycle is narrow). The compensation signal
depends on the duty cycle. The relation between the
Duty cycle and the Drain Current Limit after
compensation, IDLIM', is expressed as Equation エラー!
参 照 元 が 見 つ か り ま せ ん 。 . When duty cycle is
broader than 36 %, the Drain Current Limit becomes a
constant value IDLIM(H).
IDLIM ′ =
IDLIM(H) − IDLIM(L)
× Duty + IDLIM(L)
36 (%)
Figure 9-10 shows the FB/OLP pin peripheral circuit,
and Figure 9-11 shows each waveform for Overload
Protection (OLP) operation. When the peak drain current
of ID is limited by Overcurrent Protection operation, the
output voltage, VOUT, decreases and the feedback current
from the secondary photo-coupler becomes zero. Thus,
the feedback current, IFB, charges C3 connected to the
FB/OLP pin and FB/OLP pin voltage increases. When
the FB/OLP pin voltage increases to VFB(OLP) = 8.1 V or
more for the OLP delay time, tOLP = 76 ms or more, the
OLP is activated, the IC stops switching operation.
During OLP operation, Bias Assist Function is
disabled. Thus, VCC pin voltage decreases to VCC(OFF),
the control circuit stops operation. After that, the IC
reverts to the initial state by UVLO circuit, and the IC
starts operation when VCC pin voltage increases to
VCC(ON) by startup current. Thus, the intermittent
operation by UVLO is repeated in OLP state.
This intermittent operation reduces the stress of parts
such as a power MOSFET and secondary side rectifier
diodes. In addition, this operation reduces power
consumption because the switching period in this
intermittent operation is short compared with oscillation
stop period. When the abnormal condition is removed,
the IC returns to normal operation automatically.
(3)
U1
where,
Duty : MOSFET duty cycle (%)
IDLIM(H) : Drain current limit (Duty cycle ≥ 36 %)
IDLIM(L) : Drain current limit (Duty cycle = 0 %)
Products
IDLIM(H)
IDLIM(L)
4A162D / 62S
0.365 A
0.322 A
4A164HD
0.485 A
0.428A
4A164D
0.520 A
0.459 A
S/GND
FB/OLP
1
5~8
2
PC1
C3
VCC
D2 R2
C2
D
Figure 9-10. FB/OLP Pin Peripheral Circuit
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STR4A100 Series
Junction temperature
Tj
Tj(TSD)
Non-switching interval
Tj(TSD)−Tj(TSD)HYS
VCC pin voltage
VCC(ON)
VCC(OFF)
ON
Bias Assist Function
OFF
FB/OLP pin voltage
tOLP
VFB(OLP)
tOLP
ON
OFF
VCC pin voltage
VCC(OVP)
VCC(ON)
Drain current,
ID
VCC(BIAS)
VCC(OFF)
Drain current
ID
Figure 9-11. OLP Operational Waveforms
9.11 Overvoltage Protection (OVP)
When a voltage between the VCC pin and the S/GND
pin increases to VCC(OVP) = 29.5 V or more, Overvoltage
Protection (OVP) is activated and the IC stops switching
operation. During OVP operation, the Bias Assist
Function is disabled, the intermittent operation by
UVLO is repeated (refer to Section 9.10). When the
fault condition is removed, the IC returns to normal
operation automatically (refer to Figure 9-12).
Figure 9-13 shows OVP operational waveforms at
high temperature.
If OVP is activated in the condition that the junction
temperature, Tj, of IC is higher than Tj(TSD)−Tj(TSD)HYS,
the OVP operations as below.
When the VCC pin voltage decreases to VCC(OFF), the
Bias Assist Function is activated. When Tj reduces to
less than Tj(TSD)−Tj(TSD)HYS, the Bias Assist Function is
disabled and the VCC pin voltage decreases to VCC(OFF).
Release condition of OVP at high temperature is Tj ≤
(Tj(TSD)−Tj(TSD)HYS) and VCC pin voltage ≤ VCC(OFF).
VCC pin voltage
VCC(OVP)
VCC(ON)
VCC(OFF)
Drain current,
ID
Figure 9-12. OVP Operational Waveforms
Figure 9-13. OVP Operational Waveforms in High
Temperature
When VCC pin voltage is provided by using auxiliary
winding of transformer, the VCC pin voltage is
proportional to output voltage. Thus, the VCC pin can
detect the overvoltage conditions such as output voltage
detection circuit open. The approximate value of the
output voltage VOUT(OVP) in OVP condition is calculated
by using Equation (4).
VOUT(OVP) =
VOUT(NORMAL)
× 29.5 (V)
VCC(NORMAL)
(4)
Where,
VOUT(NORMAL): Output voltage in normal operation
VCC(NORMAL): VCC pin voltage in normal operation
9.12 Thermal Shutdown (TSD)
Figure 9-14 shows the TSD operational waveforms.
When the temperature of control circuit increases to
Tj(TSD) = 135 °C or more, Thermal Shutdown (TSD) is
activated and the IC stops switching operation. After
that, VCC pin voltage decreases. When the VCC pin
voltage decreases to VCC(BIAS), the Bias Assist Function
is activated and the VCC pin voltage is kept to over the
VCC(OFF).
When the temperature reduces to less than
Tj(TSD)−Tj(TSD)HYS, the Bias Assist Function is disabled
and the VCC pin voltage decreases to VCC(OFF). At that
time, the IC stops operation and reverts to the state
before startup. After that, the startup circuit is activated,
the VCC pin voltage increases to VCC(ON), and the IC
starts switching operation again.
In this way, the intermittent operation by the TSD and
the UVLO is repeated while there is an excess thermal
condition. When the fault condition is removed, the IC
returns to normal operation automatically.
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STR4A100 Series
10.1.2 FB/OLP Pin Peripheral Circuit
C3 (see Figure 10-1) is for high frequency noise
rejection and phase compensation, and should be
connected close to the FB/OLP pin and the S/GND pin.
The value of C3 is recommended to be about 2200 pF to
0.01 µF, and should be selected based on actual
operation in the application.
Junction Temperature,
Tj
Tj(TSD)
Tj(TSD)−Tj(TSD)HYS
Bias assist
function
ON
ON
OFF
OFF
10.1.3 VCC Pin Peripheral Circuit
VCC pin voltage
VCC(ON)
VCC(BIAS)
VCC(OFF)
Drain current
ID
Figure 9-14. TSD Operational Waveforms
10. Design Notes
10.1 External Components
Take care to use properly rated, including derating as
necessary and proper type of components.
BR1
The value of C2 in Figure 10-1 is generally
recommended to be 10 µF to 47 μF (refer to Section 9.1
Startup Operation, because the startup time is
determined by the value of C2)
In actual power supply circuits, there are cases in
which the VCC pin voltage fluctuates in proportion to
the output current, IOUT (see Figure 10-2), and the
Overvoltage Protection (OVP) on the VCC pin may be
activated. This happens because C2 is charged to a peak
voltage on the auxiliary winding D, which is caused by
the transient surge voltage coupled from the primary
winding when the power MOSFET turns off.
For alleviating C2 peak charging, it is effective to add
some value R2, of several tenths of ohms to several
ohms, in series with D2 (see Figure 10-1). The optimal
value of R2 should be determined using a transformer
matching what will be used in the actual application,
because the variation of the auxiliary winding voltage is
affected by the transformer structural design.
T1
VAC
R1
C5
P
VCC pin voltage
Without R2
C1
U1
S/GND
5
D1
D/ST
4
S/GND
6
7
8
D2
S/GND
VCC
S/GND
FB/OLP
R2
With R2
2
C2
1
C3
D
Output current, IOUT
PC1
Figure 10-2. Variation of VCC Pin Voltage and Power
Figure 10-1. IC Peripheral Circuit
10.1.1 Input and Output Electrolytic
Capacitor
Apply proper derating to ripple current, voltage, and
temperature rise. Use of high ripple current and low
impedance types, designed for switch mode power
supplies, is recommended.
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STR4A100 Series
10.1.4 D/ST Pin
Figure 10-3 shows D/ST pin peripheral circuit and
Figure 10-4 shows D/ST pin waveform in normal
operation.
The internal power MOSFET connected to D/ST pin
is permanently damaged when the D/ST pin voltage and
the current exceed the Absolute Maximum Ratings. The
D/ST pin voltage is tuned to be less than about 90 % of
the Absolute Maximum Ratings (657 V) in all condition
of actual operation, and the value of transformer and
components should be selected based on actual
operation in the application. And the D/ST pin voltage in
normal operation is tuned to be the Recommended
Operating Conditions, VD/ST(OP) < 584 V.
The fast recovery diodes are recommended for using
as D1, D2 and D51. (for D1, SARS is also
recommended)
10.1.5 Peripheral circuit of secondary side
shunt regulator
Figure 10-5 shows the secondary side detection circuit
with the standard shunt regulator IC (U51).
C52 and R53 are for phase compensation. The value
of C52 and R53 are recommended to be around 0.047 μF
to 0.47 μF and 4.7 kΩ to 470 kΩ, respectively. They
should be selected based on actual operation in the
application.
L51
T1
VOUT
(+)
D51
PC1
R55
C51
VAC
BR1
D51
T1
C5
R1
S
R54
R51
R52
C53
C52 R53
C51
P
C1
U51
D1
U1
S
R56
(-)
4
D/ST
VCC
2
D2
R2
Figure 10-5. Peripheral Circuit of Secondary Side
Shunt Regulator (U51)
Control
C2
D
S/GND
5~8
10.1.6 Transformer
Figure 10-3. D/ST Pin Peripheral Circuit
D/ST pin voltage
< 657 V
VD/ST(OP) < 584 V
Time
Figure 10-4. D/ST Pin Voltage Waveform
in Normal Operation
Apply proper design margin to core temperature rise
by core loss and copper loss.
Because the switching currents contain high
frequency currents, the skin effect may become a
consideration.
Choose a suitable wire gauge in consideration of the
RMS current and a current density of 4 to 6 A/mm2.
If measures to further reduce temperature are still
necessary, the following should be considered to
increase the total surface area of the wiring:
● Increase the number of wires in parallel.
● Use litz wires.
● Thicken the wire gauge.
In the following cases, the surge of VCC pin voltage
becomes high.
● The surge voltage of primary main winding, P, is high
(low output voltage and high output current power
supply designs)
● The winding structure of auxiliary winding, D, is
susceptible to the noise of winding P.
When the surge voltage of winding D is high, the
VCC pin voltage increases and the Overvoltage
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STR4A100 Series
Protection (OVP) may be activated. In transformer
design, the following should be considered;
● The coupling of the winding P and the secondary
output winding S should be maximized to reduce the
leakage inductance.
● The coupling of the winding D and the winding S
should be maximized.
● The coupling of the winding D and the winding P
should be minimized.
In the case of multi-output power supply, the coupling
of the secondary-side stabilized output winding, S1, and
the others (S2, S3…) should be maximized to improve
the line-regulation of those outputs.
Figure 10-6 shows the winding structural examples of
two outputs.
● Winding structural example (a):
S1 is sandwiched between P1 and P2 to maximize the
coupling of them for surge reduction of P1 and P2.
D is placed far from P1 and P2 to minimize the
coupling to the primary for the surge reduction of D.
● Winding structural example (b)
P1 and P2 are placed close to S1 to maximize the
coupling of S1 for surge reduction of P1 and P2.
D and S2 are sandwiched by S1 to maximize the
coupling of D and S1, and that of S1 and S2. This
structure reduces the surge of D, and improves the
line-regulation of outputs.
Bobbin
Margin tape
P1 S1 P2 S2 D
Margin tape
Winding structural example (a)
Bobbin
Margin tape
P1 S1 D S2 S1 P2
Margin tape
Winding structural example (b)
Figure 10-6. Winding Structural Examples
10.2 PCB Trace Layout and Component
Placement
Since the PCB circuit trace design and the component
layout significantly affects operation, EMI noise, and
power dissipation, the high frequency PCB trace should
be low impedance with small loop and wide trace.
In addition, the ground traces affect radiated EMI
noise, and wide, short traces should be taken into
account.
Figure 10-7 shows the circuit design example.
(1) Main Circuit Trace Layout:
This is the main trace containing switching currents,
and thus it should be as wide trace and small loop as
possible.
If C1 and the IC are distant from each other, placing
a capacitor such as film capacitor (about 0.1 μF and
with proper voltage rating) close to the transformer
or the IC is recommended to reduce impedance of
the high frequency current loop.
(2) Control Ground Trace Layout
Since the operation of IC may be affected from the
large current of the main trace that flows in control
ground trace, the control ground trace should be
separated from main trace and connected at a single
point as close to the S/GND pin as possible.
(3) VCC Trace Layout:
This is the trace for supplying power to the IC, and
thus it should be as small loop as possible. If C2 and
the IC are distant from each other, placing a
capacitor such as film capacitor Cf (about 0.1 μF to
1.0 μF) close to the VCC pin and the S/GND pin is
recommended.
(4) FB/OLP Trace Layout
The components connected to FB/OLP pin should be
as close to FB/OLP pin as possible. The trace
between the components and FB/OLP pin should be
as short as possible.
(5) Secondary Rectifier Smoothing Circuit Trace
Layout:
This is the trace of the rectifier smoothing loop,
carrying the switching current, and thus it should be
as wide trace and small loop as possible. If this trace
is thin and long, inductance resulting from the loop
may increase surge voltage at turning off the power
MOSFET. Proper rectifier smoothing trace layout
helps to increase margin against the power MOSFET
breakdown voltage, and reduces stress on the clamp
snubber circuit and losses in it.
(6) Thermal Considerations
Because the power MOSFET has a positive thermal
coefficient of RDS(ON), consider it in thermal design.
Since the copper area under the IC and the S/GND pin
trace act as a heatsink, its traces should be as wide as
possible.
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STR4A100 Series
(1) Main trace should be wide
trace and small loop
(5) Main trace of secondary side should
be wide trace and small loop
T1
D51
R1
C5
C1
P
C4
S
D1
5
6
7
8
(2) Control ground trace
should be connected at a
single point as close to
the S/GND as possible
D/ST
S/GND
4
NC
(6)Trace of S/GND pin
should be wide for heat
release
C51
S/GND
D2
VCC
S/GND
S/GND
2
FB/OLP
U1
(4)The components connected to
FB/OLP pin should be as close
to FB/OLP pin as possible
R2
C2
1
C3
D
PC1
C9
(3) Loop of the power
supply should be small
Figure 10-7. Peripheral Circuit Example Around IC
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STR4A100 Series
11. Pattern Layout Example
The following show the two outputs PCB layout example and the schematic of circuit using SOIC8 type of
STR4A100 series.
Top View
Bottom View
Slit width: 1 mm
Figure 11-1. PCB Layout Example (SOIC8 Type)
F1
C51
R51
L51
L1
RC1
5
T1 6, 7
D50
JW1
VOUT
(+)
VAC
JW3
C3
C1
C2
R53
PC1
R2
P1
Z1
7
D2
S/GND
VCC
S/GND
FB/OLP
R52
R54
R56
C54
C53
Z51
JW2
S/GND
6
C52
3
4
NC
5
D/ST
S1
D1
C6
S/GND
R55
R1
9, 10
R57
(-)
2
2
JW4
8
1
D
PC1
C4
1
C5
JW5
C7
Figure 11-2. Circuit Schematic for PCB Layout
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STR4A100 Series
12. Reference Design of Power Supply
As an example, the following show the power supply specification, the circuit schematic, the bill of materials, and
the transformer specification.
● Power Supply Specification
IC
Input Voltage
Maximum Output Power
Output Voltage
Output Current
STR4A162S
AC85V to AC265V
5 W (peak)
5V
1 A (max.)
● Circuit Schematic
Refer to Figure 11-2
● Bill of Materials
Symbol
RC1
General, chip
F1
L1
C1
C2
C3
C4
C5
C6
C7
C51
Part Type
(2)
(2)
(2)
C52
Ratings(1)
Recommended
Sanken Parts
800 V, 1 A
Symbol
Part Type
D50
Fuse
AC 250 V, 1 A
R1
CM inductor
Electrolytic
Electrolytic
Ceramic, chip
Electrolytic
Ceramic, chip
Ceramic, chip
Ceramic, chip
Ceramic, chip
470 μH
400 V, 6.8 μF
400 V, 6.8 μF
630 V, 680 pF
50 V, 10 µF
50 V, 4700 pF
Open
250 V,680 pF
Open
R2
R51
R52
R53
R54
R55
R56
R57
L51
Electrolytic
16 V, 1000 μF
PC1
(3)
(2)
(2)
Schottky
Metal oxide,
chip
General, chip
General, chip
General, chip
General, chip
General, chip
General, chip
General, chip
General, 1%
Inductor
Photo-coupler
C53
(2)
Electrolytic
50 V, 0.47 μF
T1
Transformer
C54
(2)
Electrolytic
Open
Z1
IC
D1
General, chip
800V, 1A
SARS05
Z51
Shunt regulator
Ratings(1)
60 V, 3 A
Recommended
Sanken Parts
SJPB-L6
680 kΩ
47 Ω
Open
560 Ω
6.8 kΩ
5.6 kΩ
6.8 kΩ
0Ω
2.2 kΩ
Short
PC123
or equiv
See
the specification
STR4A162S
VREF = 1.24 V
KIA2431AS
or equiv
D2
First recovery
250 V, 250 mA
Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less.
(2) It is necessary to be adjusted based on actual operation in the application.
(3) Resistors applied high DC voltage and of high resistance are recommended to select resistors designed against electromigration or use
combinations of resistors in series for that to reduce each applied voltage, according to the requirement of the application.
(1)
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
21
STR4A100 Series
● Transformer Specification
・
・
・
・
Primary Inductance, LP : 2.0 mH
Core size
: EI-16
Al-value
: 108 nH/N2 (Center gap of about 0.15 mm)
Winding Specification
Winding
Symbol
Number of Turns (T)
Wire Diameter (mm)
Construction
Primary Winding
P1
136
φ 0.20
Four layers, solenoid winding
Output Winding
S1
8
φ 0.32 × 2
Single-layer, solenoid winding
Auxiliary Winding
D
21
φ 0.20
Single-layer, solenoid winding
D
S1
VDC
P1
D/ST
P1
S1
VCC
Bobbin
Core
5V
GND
D
GND
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
● : Start at this pin
22
STR4A100 Series
Important Notes
● All data, illustrations, graphs, tables and any other information included in this document (the “Information”) as to Sanken’s
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change without notice due to improvement of the Sanken Products, etc. Please make sure to confirm with a Sanken sales
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● Please refer to our official website in relation to general instructions and directions for using the Sanken Products, and refer to the
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DSGN-CEZ-16003
STR4A100-DSE Rev.3.5
SANKEN ELECTRIC CO., LTD.
Oct. 12, 2020
https://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2011
23
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