LA6559

Ordering number : ENA0597 Monolithic Linear IC LA6559 Overview For CD 5-Channel Driver (BTL : Four-Channel, H Bridge : One-Channel) The LA6559 is a 5-channel driver (BTL : 4-channel, H bridge : 1-channel) for CD players. Functions • Power amplifier 5-channel built-in. (Bridge-connection (BTL) : 4-channel, H bridge : 1-channel) • IO max 1A • Level shift circuit built-in (except H bridge). • Mute circuit (output ON/OFF) built-in. (Operable with BTL AMP with MUTE1 : CH1 and MUTE2 : CH2 to 4 and not operable for the H bridge of 3.3VREG) • 3.3V regulator built-in (external PNP transistor). • With a function to set the loading output voltage • Overheat protection circuit (thermal shutdown) built-in. Specifications Maximum Ratings at Ta = 25°C Parameter Supply voltage Allowable power dissipation Symbol VCC max Pd max Independent IC Mounted on a standard board. * Maximum output current Maximum input voltage MUTE pin voltage Operating temperature Storage temperature * Standard board size : 76.1×114.3×1.6mm3, IO max VINB VMUTE Topr Tstg glass epoxy. Each output for H bridge, channel 1 to 4. Conditions Ratings 14 0.8 2 1 13 13 -30 to +85 -55 to +150 Unit V W W A V V °C °C Recommended Operating Conditions at Ta = 25°C Parameter Supply voltage Symbol VCC Conditions Same for VCC-VREG Ratings 5.6 to 13 Unit V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 11707 MS PC B8-5272 No.A0597-1/9 LA6559 Electrical Characteristics at Ta = 25°C, VCC1 = VCC2 = 8V, VREF = 1.65V, unless especially specified. Parameter ALL Blocks No-load current drain ON No-load current drain OFF VREF input voltage range Thermal shutdown temperature BTL AMP Block (CH1 to CH4) Output offset voltage Input voltage range Output voltage VOFF VIN VO VG SR VMUTE-ON VMUTE-OFF Voltage difference between outputs for BTL AMP, each channel. *3 Input voltage range for input for OP-AMP. Each voltage between V0+ and V0- when RL = 8Ω. *4 Closed-circuit voltage gain Slew rate MUTE ON voltage MUTE OFF voltage Input AMP Block (CH1 to 4) Input voltage range Output current (SINK) Output current (SOURCE) Output offset voltage Loading Block (CH5, H bridge) Output voltage VO-LOAD VCE-BREAK VIN-L VIN-H VCONT IO = 200mA (Between outputs), VCONT = 3V Power Supply Block (PNP transistor : 2SB632K-use) 3.3V supply voltage REG-IN SINK current Line regulation Load regulation VOUT REG-IN-SINK ΔVOLN ΔVOLD IO = 200mA Base current of external PNP *8 6V ≤ VCC ≤ 12V 5mA ≤ IO ≤ 200mA 3.15 3.3 10 20 50 150 200 3.45 V mA mV mV Forward, reverse, RL = 8Ω, VCONT=8V *4 Break output saturation voltage Input low level Input high level Output set voltage Output voltage at braking *7 0.3 1 2 2.9 3.15 3.4 V V V V 5.7 6.5 V VIN-OP SINK-OP SOURCE-OP VOFF-OP *6 0 2 300 -10 500 10 VCC-1.5 V mA μA mV Input and output gain. *3 AMP Independent Multiply 2 between outputs. *2 Each MUTE *5 Each MUTE *5 2 0.5 V V 5.4 6 0.5 6.6 Times V/μs 0 5.7 6.5 VCC-1.5 mA V -60 60 mV ICC-ON ICC-OFF VREF-IN TSD *2 BTL-AMP output ON, LOADING block OFF *1 All outputs OFF *1 1 150 175 10 20 VCC-1.5 200 mA V °C 30 50 mA Symbol Conditions min Ratings typ max Unit Note *1 : Current dissipation that is a sum of VCC1 and VCC2 and S-VCC at no load. *2 : Design guarantee value *3 : Input AMP is a BUFFER AMP. *4 : Voltage difference between both ends of load (8Ω). Output saturated. *5 : Output ON with MUTE : [H] and OFF with MUTE : [L] (HI impedance). *6 : The source of input OP-AMP is a constant current. As the 11kΩ resistance to the next stage is a load, pay due attention when setting the input OP-AMP gain. *7 : Short (GND) brake used. SINK side output ON. *8 : 3.3VREG incorporates a drooping protection circuit and operated when the base current is 10mA (TYP). No.A0597-2/9 LA6559 Package Dimensions unit : mm (typ) 3251 17.8 (6.2) 36 19 (0.5) 0.8 2.0 0.3 0.25 (2.25) 2.7 SANYO : HSOP36R(375mil) 0.1 2.45max 0.65 1 18 (4.9) 7.9 10.5 3 Pd max – Ta Designated board : 76.1×114.3×1.6mm3 glass epoxy Allowable power dissipation, Pd max – W 2.5 2 Mounted on a board 1.5 1 1.04 0.5 0 – 40 – 30 – 20 0 20 40 60 80 85 100 Ambient temperature, Ta – °C No.A0597-3/9 LA6559 Block Diagram Thermal shutdown REV 1 Signal system VCC Signal system GND Power supply (LOADING) 3 Input (Forward/Reversed/ Break/OFF) Output control 36 FWD S-VCC VCC2 VLO- 2 35 S-GND CH2 to CH4 Output Output ON/OFF MUTE 34 MUTE2 4 MUTE 33 MUTE1 VLO+ 5 32 33kΩ VIN4 VIN4VIN4+ VREF-IN VO4+ VO4VO3+ VO3- 6 Level shift 11kΩ 31 7 30 Level shift 8 29 9 Power system GND 28 VCONT(LOADING) FR FR Power system GND FR FR PNP Tr Collector Level shift VO2+ 10 VO2- 11 VO1+ 12 VO1- 13 VCC1 14 VIN1 15 VIN1- 16 VIN1+ 17 VIN2 18 27 3.3VREG (External PNP) 26 PNP Tr Base 33kΩ REG-OUT REG-IN Level shift 11kΩ 25 VIN3+ VIN3VIN3 GND-VREG 24 23 Power supply (CH1 to CH4) 3.3VREG GND 33kΩ 3.3VREG Power supply 22 11kΩ 21 VCC-VREG VIN2+ VIN2- 33kΩ 11kΩ 20 19 No.A0597-4/9 LA6559 Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol REV S-VCC VCC2 VLOVLO+ VO4+ VO4VO3+ VO3VO2+ VO2VO1+ VO1VCC1 VIN1 VIN1VIN1+ VIN2 VIN2VIN2+ VCC-VREG GND-VREG VIN3 VIN3VIN3+ REG-IN REG-OUT VCONT (LOADING) VREF-IN VIN4+ VIN4VIN4 MUTE1 MUTE2 S-GND FWD Pin descriptions 5CH (VLO) Output change pin (REV), logic input for loading block. Signal system power supply (BTL-AMP : CH1 to 4) Power supply for loading block Loading output (-) Loading output (+) Output pin (+) for channel 4 Output pin (-) for channel 4 Output pin (+) for channel 3 Output pin (-) for channel 3 Output pin (+) for channel 2 Output pin (-) for channel 2 Output pin (+) for channel 1 Output pin (-) for channel 1 CH1 to CH4 (BTL-AMP) output stage power supply Input pin for channel 1 OP-AMP input AMP-A input pin (-) OP-AMP input AMP-A input pin (+) Input pin for channel 2, input AMP output Input pin (-) for channel 2 Input pin (+) for channel 2 3.3VREG power supply 3.3VREG GND Input pin for channel 3, input AMP output Input pin (-) for channel 3 Input pin (+) for channel 3 PNP transistor base connected 3.3V power output to which the PNP transistor collector connected. Output voltage set pin for loading block Reference voltage applied pin Input pin (+) for channel 4 Input pin (-) for channel 4 Input pin for channel 4, input AMP output Output ON/OFF, channel 1 (BTL AMP) Output ON/OFF, channel 2 to 4 (BTL AMP) Signal system GND Output change pin (FWD) for loading output (VLO+ -), logic input for loading block. Note 1 : Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with S-GND. Note 2 : Short-circuit each of VCC1, VCC2, VCC-VREG, and S-VCC power pins externally. No.A0597-5/9 LA6559 Pin Description Pin No. 17 16 15 20 19 18 25 24 23 30 31 32 36 1 Symbol VIN1+ VIN1VIN1 VIN2+ VIN2VIN2 VIN3+ VIN3VIN3 VIN4+ VIN4VIN4 FWD REV Input (LOADING) Logic input pin. By combining H and L of this pin, any one of four modes (forward/ reversed/brake/idling) can be selected. Pin function Input (CH1 to 4) Description Input pin (CH1 to 4) Equivalent circuit VCC VIN*- VIN* VIN*+ S-GND FWD 12 13 10 11 8 9 6 7 33 34 VO1+ VO1VO2+ VO2VO3+ VO3VO4+ VO4MUTE1 MUTE2 Output (CH1 to 4) Output for channel 1 to 4. VCC1 VO* RF MUTE BTL AMP output. Output ON/OFF for CH1 to CH4. MUTE : H Output OFF MUTE : L Output OFF S-VCC MUTE 100kΩ 100kΩ S-GND 5 4 28 VLOVLO+ VCONT Output (LOADING) Output voltage set pin for loading block VO5+ VO5- VCONT No.A0597-6/9 LA6559 Truth Table (loading (H bridge) section) FWD L REV L H H *1 *2 L H The output has a high impedance. At brake, the SINK side transistor is ON (short brake). VLO+ and VLO- are approximately on the GND level. Loading output OFF *1 Forward Reversed (Short) brake *2 Relation of MUTE and Power (VCC*) MUTE1 CH1(BTL) CH2(BTL) MUTE2 CH3(BTL) CH4(BTL) CH5 (H bridge) VCC2 VCC1 No.A0597-7/9 LA6559 Sample Application Circuit MUTE1 MUTE2 1 LOADING 2 SLED LOADING MOTOR M 5 TRACKING COIL 6 7 FOCUS COIL 8 9 VLO+ VO4+ VO4VO3+ VO3VIN4 32 VIN4- 31 VIN4+ 30 VREF-IN 29 VCONT 28 3 4 S-VCC VCC2 VLOS-GND 35 MUTE2 34 MUTE1 33 REV FWD 36 FR FR FR FR SPINDLE MOTOR M 10 VO2+ 11 VO2- REG-OUT 27 REG-IN 26 3.3VREG SLED MOTOR M VCC 12 VO1+ 13 VO1VIN3+ 25 VIN3- 24 VIN3 23 GND-VREG 22 VCC-VREG 21 VIN2+ 20 VIN2- 19 VCC 14 VCC1 15 VIN1 16 VIN117 VIN1+ 18 VIN2 TRACKING FOCUS VCONT SPINDLE VREF Note : Add CR between outputs or to a circuit to GND when oscillation occurs in the output (Example : R = 2.2Ω, C = 0.1μF). Apply 4.5V or more to the external PNPTr emitter pin. No.A0597-8/9 LA6559 Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice. PS No.A0597-9/9