LA6571

Ordering number : EN7739A Monolithic Linear IC LA6571 Overview Features 5CH Driver for Mini Disk and Compact Disk The LA6571 is 5-channel driver for mini disk and compact disk applications (BTL-AMP: 5CH). • Power amplifier 5-channel built-in. • IO max 1A • Level shift circuit built-in. • Mute circuit (output ON/OFF) with three built-in channels (2-2-1). (Operates independently for each of MUTE1: CH1 and 2, MUTE2: CH3 and 4, and MUTE3: CH5. Not operating for the regulator (REG)) • Regulator (REG) built-in (external PNP transistor). Voltage setting (typ: 1.5V or more) with an external resistor • Overheat protection circuit (thermal shutdown) built-in. Specifications Maximum Ratings at Ta = 25°C Parameter Supply voltage Maximum output current Maximum input voltage MUTE pin voltage Allowable loss Symbol VCC max IO max VINB VMUTE Pd max Independent IC Mounted on a specified board* Operating temperature Storage temperature Topr Tstg Each output for channel 1 to 5. Conditions Ratings 14 1 13 13 0.8 2 -30 to +85 -55 to +150 Unit V A V V W W °C °C * Mounted on a specified board: 76.1mm×114.3mm×1.6mm glass epoxy Recommended Operating Conditions at Ta = 25°C Parameter Supply voltage 1 Supply voltage 2 Symbol VCC1 VCC2 Conditions Ratings 4.5 to VCC2 6 to 13 Unit V V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 92706 / 40506 MS IM B8-8101, 5525 No.7739-1/7 LA6571 Electrical Characteristics at Ta = 25°C, VCC1 = 5V, VCC2 = 12V, VREF-IN = 1.65V, unless especially specified Parameter [ALL Blocks] No-load current drain ON No-load current drain OFF VREF input voltage range Thermal shutdown temperature [BTL AMP Block] (CH1 to CH5) Output offset voltage Output offset voltage Output voltage Output voltage Closed-circuit voltage gain Closed-circuit voltage gain Slew rate MUTE ON voltage MUTE OFF voltage [Input AMP Block] Input voltage range Output offset voltage Output current (SINK) Output current (SOURCE) VIN op VOFF op SINK op SOURCE op *5 0 -10 2 300 500 VCC2-1.5 10 V mV mA µA VOFF VOFF1 VO VO1 V G1 V G3 SR VMUTE ON VMUTE OFF Voltage difference in output between BTL AMP and each channel. Voltage difference in output between BTL AMP and each channel. CH1,CH2 *3 CH3,CH4,CH5 *4 Gain between input and output for CH1, CH2, and CH5 *2 Gain between input and output for CH3 and CH4 *2 AMP Independent. Multiply 2 between outputs. *7 Each MUTE *6 Each MUTE *6 2 0.5 -50 -80 3.2 9.7 4.2 8.2 4.0 10.5 5.0 9.0 0.5 6.0 11.0 50 80 mV mV V V times times V/µs V V ICC ON ICC OFF VREF-IN TSD *7 All outputs ON *1 All outputs OFF *1 1 150 175 30 10 50 20 VCC2-1 200 mA mA V °C Symbol Conditions min Ratings typ max Unit [Power Supply Block] (PNP transistor: 2SB632K) Regulator output REG-IN SINK current Line regulation Load regulation VOUT REG-IN-SINK ∆VOLN ∆VOLD For error Amp, RL = 10kΩ at buffer Base current to external PNP 6V ≤ VCC ≤ 12V, IO = 200mA 5mA ≤ IO ≤ 200mA 1.2 5 1.3 10 20 50 150 200 1.4 V mA mV mV *1. Current dissipation that is a sum of VCC1 and VCC2 at no load. *2. Input AMP is a BUFFER AMP. *3. Voltage difference between both ends of load (8Ω). Output saturated. *4. Voltage difference between both ends of load (12Ω). Output saturated. *5. The source of input OP-AMP is a constant current. (See the specified block diagram.) As the 11kΩ resistance to the next stage is a load, pay due attention when setting the input OP-AMP gain. *6. Output ON with MUTE: [H] and OFF with MUTE: [L] (HI impedance). *7. Design guarantee value No.7739-2/7 LA6571 Package Dimensions unit : mm 3251 3.0 Pd max - Ta Mounted on a specified board: 76.1mm×114.3mm×1.6mm glass epoxy 17.8 (6.2) 36 19 Allowable Power Dissipation, Pd max - W 2.5 Mounted on a specified board 2.0 (4.9) 7.9 10.5 1.5 0.65 1.0 0.8 0.5 1.04 (0.5) 1 0.8 2.0 0.3 18 0.25 (2.25) Independent IC 0.42 2.45max 0 -40 -30 -20 0 20 40 60 80 85 100 2.7 SANYO : HSOP36R(375mil) Pin Description Pin Name Input Pin Name VIN1+ VIN1− VIN1 VIN2+ VIN2− VIN2 VIN3+ VIN3− VIN3 VIN4− VIN4+ VIN4 VIN5+ VIN5− VIN5 Output VO1+ VO1− VO2+ VO2− VO3+ VO3− VO4+ VO4− VO5+ VO5− MUTE1 MUTE2 MUTE3 Pin No. 17 16 15 20 19 18 23 22 21 30 29 31 32 33 34 12 13 10 11 8 9 6 7 5 4 1 2 36 Each output Equivalent Circuit Diagram Description Each input pin 0.1 Ambient Temperature, Ta - °C ILA00922 VINVCC VIN VIN+ S-GND VCC VO RF MUTE VCC Turns ON/OFF the output for MUTE1: CH1, 2 MUTE2: CH3, 4, and MUTE3: CH5. Each MUTE operates 100kΩ 100kΩ MUTE independently. MUTE: H output ON MUTE: L output OFF With the output OFF, the output has a high impedance. S-GND No.7739-3/7 LA6571 Relationship between MUTE and Power (VCC) CH1 (4-fold) MUTE1 CH2 (4-fold) CH3 (10.5-fold) MUTE2 CH4 (10.5-fold) MUTE3 CH5 (10.5-fold) VCC2 (12V) VCC1 (5V) * MUTE operates independently for each corresponding channel. Schematic Diagram of I/O Related Components Level Shift VIN VINVIN+ + VREF-IN + 11kΩ 11kΩ + + VO+ + + VO- No.7739-4/7 LA6571 Block Diagram 1 MUTE1 Thermal Shutdown MUTE3 36 MUTE1 CH1,2 CH5 MUTE3 MUTE2 2 MUTE2 CH3,4 VCC2 3 CH3,4,5 Power Supply Each MUTE operates independently for each corresponding current. “H”: Output ON “L”: Output OFF 35 S-GND 34 27.5kΩ 11kΩ + + 32 VIN5 CH5 VO5+ 5 Level Shift VO5− 4 33 VIN5− VIN5+ Level Shift VO4+ 6 CH4 31 50kΩ 11kΩ + 29 + 28 VIN4 VO4− 7 30 VIN4− CH3 VO3− 9 Level Shift VO3+ 8 + VIN4+ VREF-IN FR FR + FR FR Level Shift VO2+ 10 CH2 27 VREG + VREF-IN(CH5) VO2− 11 26 REG-IN(B) Level Shift VO1+ 12 CH1 25 (NC) VO1− 13 CH1,2 5V Power Supply 24 50kΩ 11kΩ + 22 REG-VREF VCC1 14 23 VIN3+ VIN1 15 + + VIN3− VIN1− 16 11kΩ 27.5kΩ + + 27.5kΩ 11kΩ + + - 21 VIN3 VIN1+ 17 20 VIN2+ VIN2 18 19 VIN2− No.7739-5/7 LA6571 Sample Application Circuit No.7739-6/7 LA6571 Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 2006. Specifications and information herein are subject to change without notice. PS No.7739-7/7