LA6572

Ordering number : EN7777A LA6572 Overview Monolithic Linear IC 5-CH Driver for Mini Disc and Compact Disk Applications (BTL : 5CH) The LA6572 power amplifier 5-channel (BTL) built-in. Features • Power amplifier 5-channel (BTL) built-in. • IO max 1A. • Level shift circuit built-in. • Three channels (2-1-1) of MUTE circuit (output ON/OFF) incorporated. Only CH5 normally ON. (Operative independently for each of MUTE1: CH1, 2, MUTE2: CH3, MUTE3: CH4. Inoperative for 3.3REG). • 3.3V power supply (3.3VREG) incorporated (PNP transistor connected externally). • With 3.3V power supply (3.3VREG) ON/OFF function (EN-REG) (Operative for 3.3VREG only (inoperative for BTL AMP). (3.3VREG: OFF with EN-REG: L, 3.3VREG: ON with EN-REG : H). • Operative for the fixed internal VREF (1.65V: TYP) for 5CH only. • Overheat protection circuit (thermal shutdown) built-in. Specifications Maximum Ratings at Ta = 25°C Parameter Power supply voltage Maximum output current Maximum input voltage MUTE pin voltage Allowable operation Symbol VCC max IO max VINB max VMUTE Pd max Independent IC Mounted on a specified board * Operating temperature Storage temperature Topr Tstg Each output for channel 1 to 5. Conditions Ratings 14 1 13 13 0.8 2 -30 to +85 -55 to +150 °C °C Unit V A V V W * Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 11007 TI IM B8-5621 No.7777-1/9 LA6572 Allowable Operating Range at Ta = 25°C Parameter Power supply Voltage Symbol VCC Conditions Ratings 4.5 to 13 Unit V Electrical Characteristics at Ta = 25°C, VCC1 = VCC2 = 8V, VREF = 1.65V, unless especially specified. Parameter All Blocks No-load current drain ON No-load current drain OFF VREF input voltage range VREF-OUT output voltage VREF-OUT output current VREF changeover voltage H VREF changeover voltage L Thermal shutdown temperature BTL AMP (CH1 to CH5) Output offset voltage Input voltage range Output voltage Closed-circuit voltage gain Slew rate MUTE ON voltage MUTE OFF voltage Input Amp Block Input voltage range Output offset voltage Output current (SINK) Output current (SOURCE) VIN-OP VOFF-OP SINK-OP SOURCE-OP *4 0 -10 2 300 500 VCC-1.5 10 V mV mA µA VOFF VIN VO VG SR VMUTE-ON VMUTE-OFF Voltage difference between outputs for BTL AMP, each channel. *2 Input voltage range for input for OP-AMP. Each voltage between VO+ and VO- when RL = 8Ω. *2 Input and output gain. Input OP-AMP: BUFFER AMP Independent Multiply 2 between outputs. Each MUTE *3 Each MUTE *3 2 0.5 -50 0 5.7 3.6 6.5 4 0.5 4.4 50 VCC-1.5 mV V V deg V/µs V V ICC-ON ICC-OFF VREF-IN VREF-OUT I-VREF-OUT VREF-SW-H VREF-SW-L TSD External VREF selected (VREF-SW: H) Internal VREF selected (VREF-SW: L) Design guarantee value * 150 175 All outputs ON *1 All outputs OFF *1 0.5 1.6 2 3.5 1.5 200 1.65 5 30 10 50 20 VCC-1.5 1.7 mA mA V V mA V V °C Symbol Conditions min Ratings typ max Unit Power Supply Block (PNP Transistor: 2SB632K-Use) 3.3V power supply output REG-IN SINK current Line regulation Load regulation 3.3V power supply ON voltage 3.3V power supply OFF voltage VOUT REG-IN-SINK ∆VOLN ∆VOLD REG-ON REG-OFF IO = 200mA Base current to external PNP 6V ≤ VCC ≤ 12V, IO = 200mA 5mA ≤ IO ≤ 200mA EN voltage at which 3.3V power is turned ON. *5 EN voltage at which 3.3V power is turned OFF. *5 2 0.5 3.18 5 3.3 10 20 50 150 200 3.42 V mA mV mV V V *. This is design target value and is not measured. *1. Current dissipation that is a sum of VCC1 and VCC2 at no load. *2. Input AMP is a BUFFER AMP. VIN5+ of CH5 is connected to VREF-OUT (CH5) (internal VREF). *3. Voltage difference between both ends of load (8Ω). Output saturated. *4. The source of input OP-AMP is a constant current. As the 11kΩ resistance to the next stage is a load, pay due attention when setting the input OP-AMP gain. *5. Output ON with MUTE : “H”, output OFF with MUTE : “L” (HI impedance) No.7777-2/9 LA6572 Package Dimensions unit : mm (typ) 3251 17.8 (6.2) 36 19 (0.5) 0.8 2.0 0.3 (2.25) 0.25 2.7 SANYO : HSOP36R(375mil) 3.0 Pd max - Ta Mounted on a Specified board : 114.3mm×76.1mm×1.6mm, glass epoxy Allowable power dissipation, Pd max - W 2.5 Mounted on a specified board 2.0 1.5 0.1 2.45max 1.0 0.8 0.5 Independent IC 1.04 0.42 0 20 40 60 80 85 100 0 --40 --30 --20 Ambient temperature, Ta - °C ILA00922 0.65 1 18 (4.9) 7.9 10.5 No.7777-3/9 LA6572 Pin Description Pin Name Input Pin Name VIN1+ VIN1VIN1 VIN2+ VIN2VIN2 VIN3+ VIN3VIN3 VIN4VIN4+ VIN4 VIN5+ VIN5VIN5 Output VO1+ VO1VO2+ VO2VO3+ VO3VO4+ VO4VO5+ VO5MUTE MUTE1 MUTE2 MUTE3 Pin No. 17 16 15 20 19 18 23 22 21 29 30 31 32 33 34 12 13 10 11 8 9 6 7 5 4 1 2 36 Each output S-GND VIN*+ VCC* VIN*VIN* Equivalent Circuit Diagram Description Each input pin VCC* VO* RF VCC* Turns ON/OFF the output for MUTE1 : CH1, 2, MUTE2 : CH3 and MUTE3 : CH4. Each MUTE operates independently. MUTE* 100kΩ MUTE : H output ON 100kΩ S-GND EN-VREG EN-VREG 24 MUTE : L output OFF The output has a HI impedance when OFF 3.3VREG ON/OFF pin. EN-REG ”H” : ON EN-REG ”L” : OFF EN-REG 100kΩ 100kΩ S-GND No.7777-4/9 LA6572 Relation of MUTE and Power (VCC*) CH1 MUTE1 CH2 MUTE2 MUTE3 CH3 CH4 CH5 VCC2 VCC1 * Connect VCC1 and VCC2 externally (to reduce the effects of voltage drop in the internal metal wiring). * MUTE operates independently for each CH. Relation of Each Channel and VREF CH1 CH2 External VREF CH3 CH4 Internal VREF (1.65V : TYP) CH5 * CH1 through CH4 operate for external VREF. CH5 operates for internal VREF (1.65V (TYP) : fixed). EN-REG (3.3 VREG) Operation EN-REG voltage H L 3.3V power supply state ON OFF 3.3VREG : OFF 3.3VREG : ON EN-VREG 0.5V 2V Outline of Input and Output + - 11kΩ + Level shift VIN* VINVIN+- 11kΩ 11kΩ + 22kΩ VO*+ 22kΩ 11kΩ + VO*- VREF-IN VREF-OUT + + No.7777-5/9 LA6572 Block Diagram MUTE1 1 MUTE1 CH1, 2 Thermal Shutdown CH4 MUTE3 36 MUTE3 MUTE2 2 MUTE2 CH3 Each MUTE operative independently for a corresponding CH. “H” : Output ON 35 S-GND VCC2 3 CH3, 4, 5 Power supply “L” : Output OFF 34 VIN5 Level Shift VO5- 4 CH5 22kΩ 11kΩ + + 33 VIN5- VO5+ 5 32 VIN5+ CH4 VO47 Level Shift VO4+ 6 31 VIN4 22kΩ 11kΩ + + 30 VIN4- CH3 VO39 Level Shift VO3+ 8 29 + + 28 VIN4+ VREF-IN FR FR + FR FR 1.65V(TYP) CH2 VO211 Level Shift VO2+ 10 27 3.3VREG + VREF-OUT(CH5) 26 REG-IN CH1 VO113 Level Shift VO1+ 12 25 EN-REG : “H” :3.3VREG, ON “L” :3.3VREG, OFF 24 REG-OUT EN-REG VCC1 14 CH1, 2 Power supply 22kΩ 11kΩ + + - 23 VIN3+ VIN1 15 22 VIN3- VIN1- 16 11kΩ + 22kΩ 21 VIN3 VIN1+ 17 + 22kΩ 11kΩ + + - 20 VIN2+ VIN2 18 19 VIN2- No.7777-6/9 LA6572 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name MUTE1 MUTE2 VCC2 VO5VO5+ VO4+ VO4VO3+ VO3VO2+ VO2VO1+ VO1VCC1 VIN1 VIN1VIN1+ VIN2 VIN2VIN2+ VIN3 VIN3VIN3+ EN-REG REG-OUT REG-IN VREF-OUT(CH5) VREF-IN VIN4+ VIN4VIN4 VIN5+ VIN5VIN5 S-GND MUTE3 CH1 and 2 output ON/OFF CH3 output ON/OFF Power supply for CH3, 4, and 5. Short-circuited with VCC1. Output pin (-) for channel 5 Output pin (+) for channel 5 Output pin (+) for channel 4 Output pin (-) for channel 4 Output pin (+) for channel 3 Output pin (-) for channel 3 Output pin (+) for channel 2 Output pin (-) for channel 2 Output pin (+) for channel 1 Output pin (-) for channel 1 Power supply for CH1, 2. Short-circuited with VCC2. Input pin for channel 1, input AMP output Input pin (-) for channel 1 Input pin (+) for channel 1 Input pin for channel 2, input AMP output Input pin (-) for channel 2 Input pin (+) for channel 2 Input pin for channel 3, input AMP output Input pin (-) for channel 3 Input pin (+) for channel 1 3.3V ON/OFF pin that operates with 3.3VREG. EN: H→3.3VREG:ON, EN: L→3.3VREG:OFF Collector of PNP transistor connected to output 3.3VREG. PNP transistor base connected VREF-AMP (CH5 output (TYP: 1.65V)) Reference voltage applied pin Input pin (+) for channel 4 Input pin (-) for channel 4 Input pin for channel 4, input AMP output Input pin (+) for channel 5 Input pin (-) for channel 5 Input pin for channel 5, input AMP output Signal system GND CH4 output ON/OFF Description * Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with S-GND. No.7777-7/9 LA6572 Sample Application Circuit EN-REG LOADING MUTE3 MUTE2 MUTE1 2 MUTE2 S-GND 35 1 MUTE1 MUTE3 36 3 0.1µF VCC2 VIN5 34 4 VO5- VIN5- 33 LOADING MOTOR M 2.2Ω 5 VO5+ VIN5+ 32 0.1µF 6 VO4+ VIN4 31 SPINDLE MOTOR M 2.2Ω 7 0.1µF VO4- VIN4- 30 8 VO3+ VIN4+ 29 SLED MOTOR M 2.2Ω 9 VO3- VREF-IN 28 FR FR 0.1µF 10 VO2+ VREF-OUT(CH5) 27 TRACKING COIL 2.2Ω VCC 11 0.1µF VO2- REG-IN 26 3.3VREG 12 FOCUS COIL 2.2Ω VO1+ REG-OUT 25 13 VO1- EN-REG 24 VCC 14 VCC1 VIN3+ 23 15 VIN1 VIN3- 22 16 VIN1- VIN3 21 17 VIN1+ VIN2+ 20 VREF 18 VIN2 VIN2- 19 SPINDLE SLED TRACKING FOCUS Add a capacitor + resistor between outputs or between the output and GND as a countermeasure against oscillation of the output. No.7777-8/9 LA6572 Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice. PS No.7777-9/9