LA70100M_06

Ordering number : ENN7204 LA70100M Overview Monolithic Linear IC SECAM Chroma-Signal Processor IC for VCR Package Dimensions unit : mm 3073C-MFP30SD (375mil) [ LA70100M ] LA70100M is a SECAM method chroma-signal processor for VCR applications, realizing reduction in external parts count and adjustment free due to integrated band-pass filter, SECAM discrimination circuit, and BELL filter. Features • Integrates all filters required. • Automatic adjustment BELL filter fo. • Integrates SECAM discrimination circuit. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Ta≤65°C Conditions Ratings 7.0 *440 -10 to +65 -40 to +150 Unit V mW °C °C * 114.3mm×76.1mm×1.6mm when mounted on a grass epoxy PCB. Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2206 / 92502 RM (IM) No.7204-1/16 LA70100M Recommended Operating Conditions at Ta = 25°C Parameter Supply voltage Allowable operating voltage range Symbol VCC VCCOP Conditions Ratings 5.0 4.8 to 5.2 Unit V V Electrical Characteristics at Ta = 25°C, VCC = 5V Parameter Symbol In Out Conditions T4 = OPEN ) 40 145 50 180 60 215 mA mVp-p Ratings min typ max Unit Recording mode ( T2 = 4.43MHz, 400mVp-p T29 = Comp.Sync T17 = 0V REC mode current drain 4.3MHz BPF Characteristics-1 4.3MHz BPF Characteristics-2 GF4L1 4.3MHz BPF Characteristics-3 4.3MHz BPF Characteristics-4 4.3MHz BELL Center frequency FBLR 4.3MHz BELL Characteristics-1 VBLRC 4.3MHz BELL Characteristics-2 GBLRL 4.3MHz BELL Characteristics-3 Anti-BELL Center frequency FEQR Anti-BELL Characteristics-1 Anti-BELL Characteristics-2 GEQRL Anti-BELL Characteristics-3 REC Chroma signal output level Chroma spurius spectrum-1 Chroma spurius spectrum-2 Sync gate start time Sync gate release time BGP-1 start time BGP-2 start time BGP-3 start time BGP width SECAM DET outout resistance SECAM DET characteristics-1 SECAM DET characteristics-2 Regulator voltage T12 T11 T12 T11 T18 T20 T18 T20 T18 T20 T16 T18 ICCR VF4C T16 T16 T23 T24 T18 T16 = 4.286MHz, 200mVp-p T9 = 5V T16 = 4.286MHz, 200mVp-p Same condition as above. However, frequency of T16 is 1.1MHz Measure T18 ratio to V4FC. Same condition as above. However, frequency of T16 = 2.2MHz Same condition as above. However, frequency of T16 = 7.5MHz T18 = 4 to 5MHz, 200mVp-p SW20 = ON (3.9K pull-down) ( see notes-1 ) Measure during other timing than V-sync T18 = 4.286MHz, 200mVp-p, BIAS = 4.6V SW20 = ON (3.9K pull-down) Measure during other timing than V-sync Same condition as above. However, frequency of T18 is FBLR-250kHz Measure T18 ratio to VBLRC Same condition as above. However, frequency of T18 is FBLR+250kHz SW11 = ON (3.9K pull-down) ( see notes-3 ) T12 = 1 to 2MHz, 200mVp-p, BIAS = 4.6V Measure during other timing than V-sync Same condition as above. However, frequency of T12 is 1.0715MHz Same condition as above. However, frequency of T12 is FEQR-62.5kHz Measure T12 ratio to VEQRC Same condition as above. However, frequency of T12 is FEQR+62.5kHz T1 = 5V, T16 = 4.4MHz, 200mVp-p Same condition as above. Measure 2.2MHz ratio to VOR at T12 Same condition as above. Measure 3.3MHz ratio to VOR at T12 T1 = 5V, T9 = 5V ( see notes-7 ) T16 = 4.286MHz, 200mVp-p T9 = 5V ( see notes-10 ) Same condition as above. However, T4 = 5V Same condition as above. However, T4 = 0V ( see notes-10 ) T27 = 5V ( see notes-11 ) T16 = SECAM color-bar ( see notes-12 ) T16 = PAL color-bar ( see notes-13 ) -30 -20 dB GF4L2 GF4H T16 T16 T18 T18 -10 -24 -5 -18 dB dB 4.243 4.286 4.329 MHz 92 110 132 mVp-p -7.5 -6.5 -5.5 dB GBLRH T18 T20 -7.5 -6.5 -5.5 dB 1.0608 1.0715 1.0822 MHz VEQRC T12 T11 14 18 22 mVp-p 5.0 6.0 7.0 dB GEQRH VOR GSR1 GSR2 TRGB TRGE TBGB1 TBGB2 TBGB3 TBGW R26 VSCMR1 VSCMR2 VREG T12 T16 T16 T16 T16 T16 T29 T29 T29 T29 T11 T12 T12 T12 T12 T12 T28 T28 T28 T28 T28 5.0 144 6.0 180 -40 -36 7.0 220 -30 -30 2.1 4.6 6.7 7.1 6.3 3.3 13 dB mVp-p dB dB µs µs µs µs µs µs kΩ V 1.1 3.6 5.7 6.1 5.3 2.3 7 4.5 1.6 4.1 6.2 6.6 5.8 2.8 10 T16 T16 T28 T28 T13 0.5 3.8 4.0 4.2 V V Continued on next page. No.7204-2/16 LA70100M Continued from preceding page. Parameter Forced SECAM mode control voltage range VTHSM T1 T16 T12 Symbol In Out T27 = 3V T16 = 4.286MHz, 200mVp-p Measure voltage range of T1 when signal output from T12. Forced Except-SECAM mode control voltage range VTHMM T1 T16 T12 T27 = 4V T16 = 4.286MHz, 200mVp-p Measure voltage range of T1 when T12 is mute. Playback mode ( T2 = 4.43MHz, 400mVp-p T29 = Comp.Sync T17 = 5V, T10/T4 = OPEN ) PB mode current drain AGC characteristics-1 AGC characteristics-2 GAGC1 AGC characteristics-3 1.1MHz BPF Characteristics-1 GF1L 1.1MHz BPF Characteristics-2 1.1MHz BPF Characteristics-3 1.1MHz BELL Center frequency FEQP T14 T11 T14 T12 T14 T12 ICCP VAGC T14 T14 T23 T24 T12 T14 = 1.0715MHz, 50mVp-p T9=5V, T1=5V Voltage of T15 is V15R. Same condition as above. However, level of T14 is 100mVp-p Measure T14 ratio to VAGC GAGC2 T14 T12 Same condition as above. However, level of T14 is 25mVp-p V15 = V15R ( see notes-4 ) T14 = 500kHz, 50mVp-p Measure T14 ratio to VAGC GF1H1 GF1H2 T14 T14 T12 T12 Same condition as above. However, frequency of T14 is 2.2MHz Same condition as above. However, frequency of T14 is 3.3MHz T15 = V15R ( see notes-4 ) T14 = 1 to 1.2MHz, 50mVp-p ( see notes-5 ) SW11 = ON (3.9K pull-down) Measure during other timing than V-sync 1.1MHz BELL Characteristics-1 1.1MHz BELL Characteristics-2 GEQPL 1.1MHz BELL Characteristics-3 Anti-BELL Center frequency-1 Anti-BELL Center frequency-2 Anti-BELL Center frequency-3 Anti-BELL characteristics-1 Anti-BELL characteristics-2 GBLPL Anti-BELL characteristics-3 GBLPH PB Chroma signal output level Chroma spurius spectrum-1 Chroma spurius spectrum-2 Sync gate start time Sync gate release time Phase Det output voltage-1 Phase Det output voltage-2 T18 T20 T18 T20 T14 T11 VEQPC T14 T11 Same condition as above. However, frequency of T14 is 1.0715MHz Same condition as above. However, frequency of T14 is FEQP-62.5kHz Measure T14 ratio to VEQPC GEQPH FBLP1 FBLP2 FBLP3 VBLPC T14 T18 T18 T18 T18 T11 T20 T20 T20 T20 Same condition as above. However, frequency of T14 is FEQP+62.5kHz ( see notes-6 ) T18 = 4 to 5MHz, 200mVp-p, BIAS = 4.6V Same condition as above. However, T10 = 0V Same condition as above. However, T10 = 5V T18 = 4.286MHz, 200mVp-p, BIAS = 4.6V Same condition as above. However, frequency of T18 is FBLP1-250kHz Measure T18 ratio to VBLPC Same condition as above. However, frequency of T18 is FBLP1+250kHz Measure T18 ratio to VBLPC VOP GSP1 GSP2 TPGB TPGE VSCPD1 VSCPD2 T14 T14 T14 T14 T14 T14 T14 T18 T18 T18 T18 T18 T25 T26 T25 T26 T1 = 5 V, T14 = 1.0715MHz, 50mVp-p Same condition as above. However,. measure 2.2MHz ratio to VOP at T18 Same condition as above. However,. measure 3.3MHz ratio to VOP at T18 T1 = 5V, T9 = 5V ( see notes-9 ) T14 = 1.0715MHz, 50mVp-p T14 = 1.0625/1.1016MHz, 50mVp-p ( see notes-14 ) T14 = 627kHz, 50mVp-p. (see notes-14) 1.2 4.7 150 105 130 -45 -28 1.7 5.2 180 100 160 -35 -20 2.3 5.7 mVp-p dB dB µs µs mV mV 5.0 6.0 7.0 dB 5.0 6.0 7.0 dB -6.5 4.243 4.283 4.323 32 -5.5 4.286 4.326 4.366 40 -4.5 4.329 4.619 4.659 48 dB MHz MHz MHz mVp-p -6.5 -5.5 -4.5 dB 80 100 120 mVp-p 1.0608 1.0715 1.0822 MHz -30 -35 -20 -25 dB dB -3 0 3 dB -1 0 1 dB -1 0 1 dB T14 = 1.0715MHz, 50mVp-p 48 90 60 120 72 150 mA mVp-p 0 0.5 1.0 V 4.0 4.2 VCC V Conditions Ratings min typ max Unit Continued on next page. No.7204-3/16 LA70100M Continued from preceding page. Parameter SECAM detection characteristics-1 SECAM detection characteristics-2 R/P control threshold voltage Clock input level VCLK Sync signal input threshold level SECAM DET comparator threshold voltage T2 T9 Symbol VSCMP1 VSCMP2 VTRP In V25 V26 V25 V26 T17 Out T28 T28 ( see notes-15 ) ( see notes-15 ) Minimum voltage of T16 under normal PB condition T2 = Sign Wave (4.433619MHz), SW9 = ON Minimum voltage of T9 at phase locked T2 with T8. VTHS VTCOMP T29 T27 T28 T28 Minimum voltage of T29 at BGP outputs normally from T28. T9 = 5V Minimum applied voltage of T27 at T28 = H. 1.8 3.2 2.0 3.5 2.2 3.8 Vp-p V 100 200 800 mVp-p Conditions Ratings min 4.5 0.5 2.3 2.5 2.7 typ max Unit V V V Supplemental Description (Note 1) REC mode BELL center frequency (FBLR1, FBLR2, FBLR3) : Input a sine wave (200mVpp, 4 to 5MHz) to T16 and measure the amplitude at T20. Assign to FBLR1 (T10=OPEN), FBLR2 (T10=0V), FBLR3 (T10=5V) the frequency at T16 where the amplitude is maximized. SECAM standard color bar signal (75%) DR T16 DB 4.40625MHz 214.5mVpp 1.5µs T29 4.25MHz 166.7mVpp Fig.1 (Note 3) REC EQ (1.1MHz A-BELL) center frequency (FEQR) : Observe the waveform at T11 when T12=sine wave (200mVpp, 4 to 5MHz, BIAS=4V) is input and assign to FEQR the frequency at T11 where the amplitude is minimized. (Note 4) Assign to V15R the voltage of T15 at the time of VAGC measurement. (Note 5) PB EQ (1.1MHz BELL) center frequency (FEQP) : Input a sine wave (50mVpp, 1 to 1.2MHz) to T14 and assign to FEQP the frequency at T14 where the signal level of T11 is maximized. (Note 6) PB 4.3MHz A-BELL center frequency (1 FBLP1) / (2 FBLP2) / (3 FBLP3) : Input a sine wave (200mVpp, 1 to 1.2MHz, BIAS=4V)) to T18 and assign to FBQP1 (T10=OPEN), FBQP2 (T10=0V), FBEQP3 (T10=5V) the frequency at T18 where the signal level at T20 is minimized. No.7204-4/16 LA70100M (Note 7) REC mode sync gate start time, release time (TRGB, TRGE) : Input Copm. Sync to T29 and assume the sync gate start time (TRGB) as the time from which the signal at T12 attenuates until the signal at T29 rises and assume the sync gate release time (TRGE) as the time from which the horizontal sync signal rises till the signal at T12 increases (Fig. 2). 64µs T29 (C.SYNC) TRGB TRGE T12 Fig.2 REC mode sync gate timing (Note 9) PB mode sync gate start time, release time (TRGB, TPGE) : Input Comp.sync to T29 and assume the sync gate start time (TRGB) as the time from which the siganl at T18 attenuates until the horizontal sync signal rises and assume the sync gate release time (TPGE) as the time from which the horizontal sync signal rises until the signal at T18 starts increasing. 64µs T29 (C.SYNC) TPGB TPGE T18 (PB-OUT) Fig.3 PB mode sync gate timing (Note 10) BGP start time, BGP width (Fig. 4) T9=5V (TEST MODE) T29 (C.SYNC) TBGW TBGB T28 (BGP-OUT) 1V Fig.4 BGP timing No.7204-5/16 LA70100M (Note 11) Output impedance of SECAM DET (R28) Assign to V28 as when generating 100µA from pin 28 by adding 5V to pin 27 and take “H”, and calculate R28. VCC R28 R28= 5(V) - V28 100µA 28 Fig.5 (Note 12) The sync signal at T29 must lag behind the SECAM color bar signal synchronization by 1.5µs (Fig. 1). (Note 13) The sync signal at T29 must lag behind the PAL color bar signal synchronization by 1.5µs (Fig. 6). PAL color bar signal 100% T16 1Vpp 1.5µs T29 4.433619MHz 21.5% Fig.6 (Note 14) PB mode phase detection output differential voltage : VSAPD1 : Assign to VPD1 the DC voltage at T25 when a sine wave of 1.0625MHz is input to T14 and VPD2 the DC voltage at T26 when a sine wave of 1.1016MHz is input. VSCPD1=VPD2 - VPD1 VSAPD2 : Assign to VPD3 and VPD4 the voltage at T25 and T26, respectively, when a sine wave of 627kHz is input to T14. VSCPD2=VPD4 - VPD3 (Note 15) PB mode SECAM detection characteristics VSCMP1 / VSCMP2 : VSCMP1 : Apply the above-mentioned VPD1 and VPD2 to T25 and T26, respectively and measure the voltage at T28. VSCMP2 : Apply the above-mentioned VPD3 and VPD4 to T25 and T26, respectively and measure the voltage at T28. No.7204-6/16 LA70100M Functional Description (1) REC mode MONITOR OUTPUT 20 MONITOR OUTPUT 11 4.3MHz BPF VIDEO SIGNAL INPUT 16 4.3MHz BELL LIM 1/4 DIVIDER SYNC GATE 1.1MHz BPF 1.1MHz A-BELL REC MUTE 12 19 LOW CHROMA SIGNAL OUTPUT 4.286MHz Fig.1 Signal flow in REC mode 1.107MHz Video signals which have been input to Pin 16, pass through the 4.3MHz BPF with unnecessary component (ex. sync signal) removed, and the component of chroma signal is extracted. And the characteristics during transmission are made flat through a 4.3MHz-BELL filter. The center frequency of this filter has automatically been adjusted to be 4.286MHz. After that, the limiter amplifier limits the amplitude, and the chroma signal frequency is converted to 1/4 by a divide-by-four circuit. Though the limiter amplifier amplifies the noise of non-signal parts of the converted signal during synchronization, the sync gate circuit cleans the peripherals of the sync signal. Still more, since this signal has rectangle waveforms, it contains unnecessary component of frequency. To remove it, the signal passes through a 1.1MHz BPF and then is input to 1.1MHz-A-BELL filter. The center frequency of this filter is automatically adjusted to 1.0715MHz, and has opposite characteristics to BELL characteristics. Afterwards, unnecessary components around the sync signal are muted, low-band chroma signal is output to Pin 12 through a buffer. (2) PB mode MONITOR OUTPUT 11 MONITOR OUTPUT 20 14 LOW CHROMA SIGNAL INPUT 15 AGC 1.1MHz AMP BPF PB BELL X2 2.2MHz BPF X2 2.2MHz TRAP VM 4.3MHz BPF LIM 19 SYNC GATE 4.3MHz BPF 4.3MHz A-BELL PB MUTE 18 PB CHROMA SIGNAL OUTPUT AGC DET 1.107MHz 4.286MHz Fig.2 Signal flow in PB mode The low chroma signal that has been input from Pin 14 enters AGC amplifier and is controlled so that the output level of 4 times multiplier be constant. Then it passes through the 1.1MHz BPF with unnecessary components removed before input to 1.1MHz-BELL filter. The center frequency of this filter has automatically been adjusted to be 1.0715MHz. Next, this signal passes through the 4 times multiplier composed of a 2× multiplier + 2.2 MHz BPF + 2× multiplier + 2.2MHz TRAP + 4.3MHz BPF with unnecessary component of frequency generated in multiplier removed. The first 2× multiplier has auto carrier leak balancer allowing beat obstruction reduced. Next, this signal is limited pulse amplitude by limiting amplifier, then noises around the sync signal owing to limited amplifier are cleaned by the sync gate circuit. This signal has a rectangle waveform and contains unnecessary components of frequency. To remove it, the signal passes through a 4.3MHz BPF before input to 4.3MHz-BELL filter. The center frequency of this filter is automatically adjusted to 4.286MHz, allowing the BELL characteristics to the state during transmission. Afterwards, unnecessary components around the sync signal are muted, low-band chroma signal is output to Pin 18 through a buffer. No.7204-7/16 LA70100M (3) CLK INPUT, AFC for BELL ADJUST CLOCK 2 4.43MHz CLOCK BUFF AFC 4.43MHz VCO for EACH FILTER ADJUST 3 Fig.3 Input a frequency of 4.433619MHz sine wave or rectangle waveform signal of PAL fsc to CLK input terminal. This signal is used for automatically adjusting the BELL filter and generating timing pulse for AFC and for sync gate. AFC circuit automatically adjusts the frequency characteristics for each BPF. (4) SYNC GATE CIRCUIT 4.43MHz CLOCK C omposite sync 29 SYNC SEPA C.SYNC V.SYNC CONTROL LOGIC SYNC GATE/MUTE SECAM DET SAMPLE HOLD-1, 2 C.sync SYNC GATE MUTE C.sync V-MUTE BELL ADJUST SECAM DET SAMPLE HOLD-3 BELL ADJUST GATE Fig.4 700µ s Vertical sync signal is extracted by a synchronous separate circuit from Composite Sync signal that has been input from Pin 29, and is conducted to BELL/A-BELL filter automatic adjusting circuit. Additionally, SYNC GATE pulse and sample hold pulse are generated by the logic circuit. (5) BGP generator circuit BGP is used for killer circuit in REC Mode, AGC circuit in PB Mode, and SECAM discrimination circuit. In BP Mode, AGC circuit detects the scale of the signal of BGP duration (ID) so that the output of 4 times multiplier circuit be constant. In SECAM discrimination circuit, BGP is used for making the S/H pulse (SP9, SP2 in Figure 9) mentioned later. Controlling Pin 4 can convert the timing for Composite Sync that is input to Pin 27. The width of BGP is determined by the constant of the inside of IC to about 2.5 µs. And BGP timing can be monitored by Pin 28 in test mode (Pin 9 voltage = 5V). No.7204-8/16 LA70100M (6) REC-BELL filter, PB-A-BELL filter 4.3MHz A-BELL FILTER CHARACTERISTICS 4.3MHz BELL FILTER CHARACTERISTICS It is an internal filter of which center frequency is fitted to 4.286MHz by automatic adjusting circuit (described later) that uses input frequency (fsc), thus prevents this filter from affected by external components. (7) REC-A-BELL filter, PB-BELL filter 1.1MHz A-BELL CHARACTERISTICS 1.1MHz BELL CHARACTERISTICS It is an internal filter of which center frequency is fitted to 1.0715MHz by automatic adjusting circuit (described later) that uses input frequency (fsc), thus prevents this filter from affected by external components. (8) BELL/A-BELL filter frequency automatic adjustment MODE CONTROL 4.43MHz CLOCK 4.286MHz PROGRAMABLE DIVIDER BELL/A-BELL COUNTER OSC DIFFERENCE CLOCK for COUNT UP GATE CLOCK for COUNT DOWN CONTROL ENABLE LOGIC CLOCK for COUNT DOWN GATE CLOCK for COUNT UP DIFFERENCE 1.0715MHz PROGRAMABLE BELL/A-BELL DIVIDER DIVIDER COUNTER OSC CONTROL VOLTAGE CONTROL D0 D1 D2 D3 D4 D5 UP/DOWN COUNTER DIVIDER C.SYNC V.SYNC UP/DOWN COUNTER D0 CONTROL D1 D2 D3 D4 D5 VOLTAGE CONTROL MODE CONTROL Fig.8 (a) No.7204-9/16 LA70100M C.sync VD 4.3MHz/1.1MHz OSC ENOSC ENABLE Fig.8 (b) 700µs During a period when the color signal processing is left untouched (for about 700 µs from the start of vertical sync signal), center frequency of BELL filter is automatically adjusted. MODE CONTROL sets each BELL/A-BELL filter into VCO mode after vertical sync signal is input, then the OSC oscillates at 4.3MHz or 1.1MNz. Oscillation output is divided respectively by a programmable divider and outputs the timing pulse that corresponds to oscillation frequency with control logic. This pulse is compared with the timing pules acquired by dividing 4.43MHz CLK and generates UP or DOWN CLK corresponding to the amount of discrepancies for oscillation frequency 4.286MHz/1.0715MHz. That is input to UP/DOWN counter to increase and decrease the counter value. When ENABLE pulse is generated the outputs D0 to D5 are rewritten, and the control voltage varies so that the oscillation frequency approach 4.286MHz/1.0715MHz. This operation repeats whenever the vertical sync signal is input and stops when the frequency difference becomes to a specified value ( ±43kHz / ±10.7kHz ). (9) SECAM + 27 DET 25 S/H-1 S/H-3 21 + SAMPLE HOLD PULSE S/H-3 PHASE DET 90 DEG 4.3MHz BPF LIM from MAIN SIGNAL LINE S/H-1 28 SECAM DET OUT LOGIC COMP SENS CONTROL Vref 30 S/H-2 SAMPLE HOLD PULSE BELL ADJUST PULSE 26 CTL S/H-2 Fig.9(a) Chroma signal SP1 SP2 SP3 VS1 VS2 Fig.9 (b) V2 Same as ESOSC at fig.8 (b) V1 128µs Voltage V2 VL V1 4.25MHz (4.28MHz) 4.40625MHz Frequency Fig.9 (c) The color signal with the amplitude limited by limiting circuit varies the phase according to the signal frequency after it passes through a 4.3MHz BPF. DC voltage according to the phase can be acquired by shifting this output phase by further 90° and inputting it to a phase detector with the original signal. The characteristic of the output of a phase detector is as shown in the figure 9 (b), as the voltage limiting circuit operates at S/H-3 in order to prevent the malfunction caused by unwanted signals. This limiting circuit voltage is the phase detector output DC voltage to which the signals of 4.286MHz VCO is input used on BELL filter automatic adjusting circuit. Then it is possible to operate the limiting circuit exactly at a frequency more than 4.286 MHz and to prevent the false discrimination during MESECAM signal input. After that, input to two sample & hold circuits, the sampling pulse is shown like pulses correspond to BGP of NTSC and PAL generated every 1H as SP1 and SP2 in figure 9 (b). The SECAM color signal has ID signals of 4.25MHz and 4.40625MHz generated every 1H on the part that corresponds to this BGP, each phase detection output causes the level difference as V1, V2 in figure 9 (b). When this difference is sampled by SP1 and SP2 the waveform becomes as VS1 and VS2 in the figure 9 (b), and when it is hold by external capacitor it becomes as V1 and V2. Input to a comparator after detecting the difference of these two voltages, smoothing it to stable with the external capacitor connected to Pin 27. In addition, applying more than 1V DC voltage to Pin 30 allows the amplification of the level difference to be varied. When the smooth value of V1-V2 exceeds 3.5V, SECAM signal is detected with a high-level output from the Pin 28. This discrimination circuit uses a rule that the output of a phase detector differs every 1H as shown in the figure 9 (b) (c) to detect a SECAM signal. PAL signal always outputs high since its burst is constant and doesn’t vary phase detection output. No.7204-10/16 LA70100M MODE control [ Output mute control ] Forcibly applying a DC voltage to pin-1 allows REC-OUT and PB-OUT muting control. pin-1 voltage 5V OPEN 0V Forced SECAM AUTO ( internal detect ) SECAM : Active Forced mute Except SECAM : mute output mode ( pin-12, pin-18 ) [ TEST mode control ] pin pin-11 pin-12 pin-18 pin-20 pin-28 use monitor output 1.1MHz BELL/A-BELL (11 to GND:3.9k) 1.1MHz BPF (pin-9 : 5V) 4.3MHz BPF (pin-9 : 5V) 4.3MHz BELL/A-BELL (20 to GND:3.9k) BGP out (pin-9 : 5V) use monitor input ⎯ 1.1MHz BELL/A-BELL input (4V BIAS+SIG) 4.3MHz BELL/A-BELL input (4V BIAS+SIG) ⎯ ⎯ [ BGP position control ] pin-4 add voltage L (0V) OPEN (2.5V) H (5V) BGP position -400ns ±0ns +400ns [ 4.3M BELL offset control* ] pin-10 add voltage L (0V) OPEN (2.5V) H (5V) offset frequency +40kHz ±0kHz +80kHz *Active only in PB mode [ REC / PB mode control ] pin-17 add voltage L (0V) H (5V) mode REC mode PB mode Block diagram / application C.SYNC IN SECAM HI 2200pF 2200pF 2.2µF VCC 5V + 27 VCC 5V 0.47µF 0.01µF + 21 PB OUT RP CTL REC IN 0.01µF 0.47µF REC : 0V PB : 5V 16 17 REC / PB PB-H REC PB SYNC GATE REC X2 CHROMA 1.1MHz 2.2MHz BFP X2 2.2MHz TRAP 1.1MHz BFP .1MHz BELL 1BELL PB ANTI BELL ANTI BELL REC 4.3MHz BFP LIM PB REC SYNC GATE REC-IN No Connect SECAMDET OUT SYNC-IN BELL MONIT4 SECAM DET SENS LIM EXC SECAM DET SYNC GATE GEN / V-SEP BGP GEN MODE CTL to MUTE to MUTE to SYNC GATE to PB AGC to REC KILLER CONTROL LOGIC BELL REC 4.3MHz BELL ANTI BELL ANTI BELL 2.2MHz TRAP PB 4.3MHz BFP PB-OUT S/H C1 DET C VCC S/H C2 S/H C3 VCC2 30 29 28 26 25 24 23 22 20 19 18 Buffer PB MUTE 1/4 AFC 4.43MHz VCO Filter Adj. PB 2.2MH z AGC FILTER REC MUT REG 4.0V 13 AGC AMP 0.01µF PB-IN AGC DET TEST MODE VCO MONIT AFC FILTER BGP DELAY No Connect 1 2 3 1kΩ 4 5 0.01µF MODE CTL H:SECAM 4.43MHz M:AUTO DET L:EXCEPT SECAM CW 1µF + BGP DELAY CTL H:+400n M:0n L:-400n 4.3MHz BELL FO CTL H:+80k M: 0k L: +40k * PB ONLY 0.01µF 0.1µF 1µF 6 + 7 8 4.3MHz BELL FO CTL FO CTL 9 10 REC-OUT Buffer Buffer CLK IN MODE GND2 GND BAL BELL MONIT1 11 12 REG 14 15 + REC-C OUT PB-C IN No.7204-11/16 LA70100M Pin Description Pin No. 1 Pin Name MODE CTL DC voltage 2.5V Signal waveform DC Input/output form VCC 100kΩ Note 1 10kΩ 100kΩ 2 CLK IN 2.5V 4.43MHz, 400mVp-p VCC 20kΩ 2 500Ω 5kΩ 3 AFC FILTER 3.5V DC 4.0V 20kΩ VCC 200Ω 1kΩ 3 200Ω 60kΩ VCC 50kΩ 2kΩ 4 BGP DELAY 1 to 5V DC 7kΩ 4 5 6 No Connect BAL ( Balancer ) 1.2V DC 2kΩ VCC 500Ω 50kΩ 6 7 8 9 GND2 GND TEST MODE ( VCO MONITOR ) 0V 0V 2.1V Normal : DC 200Ω VCC 2kΩ Normal : open VCO monitor : insert resistor to GND 20kΩ VCO monitor : CW (4.43MHz, 450mVp-p) 200Ω 1kΩ 9 30kΩ TEST mode ON : pull-up to VCC Continued on next page. No.7204-12/16 LA70100M Continued from preceding page. Pin No. 10 Pin Name F0 CTL (4.3MHz BELL OFFSET) 10 DC voltage 2.5V Signal waveform DC Input/output form VCC 100kΩ Note 11 BELL MONIT 1 (1.1MHz BELL MONIT) 2.7V Normal : DC 500Ω VCC 100kΩ 10kΩ Normal : open BELL monitor : insert resistor to GND BELL monitor : CW (1.1MHz, 300mVp-p) 12 REC OUT ( TEST SIG I/O ) REC : 2.2V PB : GND 1.1MHz, 700mVp-p 200Ω VCC 500Ω 11 TEST input : signal with 4V bias 100Ω 20kΩ 12 1kΩ 13 REG 4.0V DC VCC 13 14 PB IN 2.5V 1.1MHz, 50mVp-p VCC 10kΩ 2kΩ 14 1kΩ 15 AGC FILTER VCC/2 ±VBE DC 2kΩ VCC 2kΩ 25kΩ 15 3kΩ 16 REC IN 2.5V Composite VIDEO 1.0Vp-p 8kΩ VCC 1kΩ 1kΩ 16 8kΩ 10kΩ Continued on next page. No.7204-13/16 LA70100M Continued from preceding page. Pin No. 17 Pin Name R/P CTL DC voltage 0 to VCC Signal waveform DC Input/output form VCC Note VTH = VCC/2 17 1kΩ 18 PB OUT ( TEST SIG I/O ) PB : 1.95V REC : GND 200Ω VCC TEST input : signal with 4V bias 4.3MHz, 400mVp-p 20kΩ 100Ω 18 1kΩ 19 LIM EXC 2.3V DC VCC 1kΩ 20kΩ 19 10pF 20 BELL MONIT 4 (4.3MHz BELL MONIT) 2.7V Normal : DC 500Ω VCC Normal : open BELL monitor : insert resistor to GND BELL monitor : CW (4.3MHz, 400mVp-p) 21 S/H C3 2.5V DC (when connecting capacitor) 500Ω 20 VCC 2kΩ 21 22 23 24 25 No Connect VCC VCC2 S/H C1 5V 5V 2.5V DC DC DC (when connecting capacitor) VCC 2kΩ 25 10kΩ 1kΩ 10kΩ 1kΩ Continued on next page. No.7204-14/16 LA70100M Continued from preceding page. Pin No. 26 Pin Name S/H C2 DC voltage 2.5V Signal waveform DC (when connecting capacitor) Input/output form VCC Note 2kΩ 26 27 DET C 2 to 5V DC 1kΩ VCC 30kΩ 30kΩ 2kΩ 27 1kΩ 20kΩ 28 SECAM DET OUT 0V/5V DC (0V or 5V) 10kΩ 1kΩ VCC 10kΩ Normal mode (BGP MONITOR ) BGP pulse 5V 0V 28 At TEST mode 29 SYNC IN Threshold voltage 2.0V Composite sync VCC 30kΩ 29 2kΩ 30 SECAM DET SENS 2.0V DC VCC 30kΩ 30 1kΩ 20kΩ 50kΩ No.7204-15/16 LA70100M Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 2002. Specifications and information herein are subject to change without notice. PS No.7204-16/16