LA72700V

Ordering number : ENA0015 Monolithic Linear IC LA72700V Overview US MTS (Multi Channel Television Sound) Decoder LA72700V is a US MTS (Multi Channel Television Sound) decoder. Features • With SIF circuit, STEREO channel separation is alignment-free. • Built-in filters are adjustment free. • SAP output level is selectable 2 levels. • Included control function for STEREO and SAP detection sensitivity. Functions • SIF FM-Demodulator. • STEREO decoder. • ALC function is included. • dbx Noise Reduction system. • SAP demodulator. • STEREO detection. • SAP detection. Specifications Maximum Ratings at Ta = 25°C Parameter Maximum power supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Ta≤70°C * Conditions Ratings 9.6 810 -10 to +70 -55 to +150 Unit V mW °C °C * ON board (114.3 × 76.1 × 1.6 mm Glass Epoxy resin board) Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2206 / O2505 MS OT B8-8873 No.A0015-1/16 LA72700V Operating Conditions at Ta = 25°C Parameter Recommended operating voltage Operating voltage range VCC op 8.5 to 9.5 V Symbol VCC Conditions Ratings 9.0 Unit V Electrical Characteristics at Ta = 25°C, VCC = 9.0V Parameter Current dissipation SIF input level (Reference) Symbol ICC VILIM Conditions min No signal Inflow current at pin 31 * Default condition fc = 4.5MHz Deviation MONO (300Hz, Mod = 100%, Pre-emphasis ON) ±25kHz Base band input level (Reference) VILIMB 100% Modulation MONO(L+R): 530mVp-p (300Hz, Pre-emphasis ON) SUB(L-R): SAP: MONO output level MONO distortion MONO frequency characteristics VOMON THDMON FCM1 380mVp-p (300Hz, dbx-NR ON), Pilot: 110mVp-p 300mVp-p (300Hz, dbx-NR ON) -7.0 -6.0 0.15 -2 0 -5.0 0.6 2 dBV % dB (80) (90) (100) dBµV 50 Ratings typ 60 max 70 mA Unit Input: fm = 1kHz, 100% Mod, MONORAL Measure OUT (L), OUT (R) Input: fm = 1kHz, 100% Mod, MONORAL Measure OUT (L), OUT (R) Input: fm = 8kHz, 30% Mod, MONORAL Measure OUT(L), OUT(R), Ratio from fm = 1kHz level. MONO S/N ratio SNM S = VOMON, N = 0% Mod Measure OUT (L), OUT (R) With 15kHz LPF, JIS-A 55 65 dB STEREO output level STEREO distortion STEREO frequency characteristics STEREO S/N ratio VOST THDS FCS1 Input: fm = 1kHz, 100% Mod, STEREO Measure OUT (L), OUT(R) Input: fm = 1kHz, 100% Mod, STEREO Measure OUT (L), OUT (R) fm = 8kHz, 30% Mod, STEREO Measure OUT (L), OUT (R), Ratio from fm = 1kHz level. -7.0 -6.0 1.0 -5.0 2.5 3 dBV % dB -3 0 SNS S = VOST, N = 0% Mod Measure OUT (L), OUT (R) With 15kHz LPF, JIS-A 50 60 dB STEREO separation 1 STEREO separation 2 STEREO Detection level-1 STEREO Detection level-2 STSE1 STSE2 VINSD1 VINSD2 f = 300Hz (R/L), 30% Mod Measure ratio OUT (L) with OUT (R) f = 3kHz (R/L), 30% Mod Measure ratio OUT (L) with OUT (R) Except Stereo Detection Except Stereo Detection Stereo Detection Stereo Detection 20 20 52 62 25 25 57 67 62 72 dB dB % % Measure PILOT level, at STERO det. * Insert Resistor pin 14 to GND (ex. 51kΩ) Measure PILOT level, at STERO det. Continued on next page. No.A0015-2/16 LA72700V Continued from preceding page. Parameter STEREO detection hysteresis SAP output level-1 Symbol HYST VOSA Conditions min Input Mod. Difference at Stereo /Except Stereo Det. * at default condition Fm = 1kHz, 100% Mod, SAP Measure OUT (L), OUT * at bit6 = 0 SAP output level-2 VOSA2 Fm = 1kHz, 100% Mod, SAP Measure OUT (L), OUT * at bit6 = 1 SAP distortion SAP S/N ratio THDSA SNSA Fm = 1kHz, 100% Mod, SAP Measure OUT (L), OUT S = VOSA, N = 0% Mod, Measure OUT (L), OUT (R) With 15kHz LPF, JIS-A SAP detection level-1 VINSA1 Measure SAP carrier level, when SAP det * Default condition SAP detection level-2 (Reference) SAP detection level-3 (Reference) SAP detection hysteresis MODE output MONO MODE output SAP MODE output STEREO MODE output ST + SAP HYSA MODMO MODSA MODST MODSS VINSA3 VINSA2 Measure SAP carrier level, when SAP det * pin15 to GND (ex 33kΩ) Measure SAP carrier level, when SAP det * pin15 to GND (ex 8.2kΩ) Input Mod. Difference at SAP/Except SAP Det. * at default condition Input = MONO: f = 1kHz, 0% Mod Measure pin32 Input = SAP: Carrier Measure pin32 Input = STEREO: Pilot Measure pin32 Input = STEREO: Pilot, SAP: Carrier Measure pin32 Distortion THDALC MONO 1kHz Mod 100% * ALC on Measure OUT (L), OUT (R) 0.3 0.5 % 3.5 3.8 4.2 V 2.7 3 3.3 V 1.7 2 2.3 V 0.7 1 1.3 V 2 5 10 % (20) (25) (30) % (5) (10) (15) % 13 18 23 % 55 65 dB 1.5 3.5 % -5.5 -4.5 -3.5 dBV -7.5 -6.5 -5.5 dBV 10 Ratings typ 15 max 25 % Unit * Normally measurement condition is Input = SIF mode (-90dBµV), ALC = OFF * " Reference " Items are reference levels, their specs are no-guarantee. Package Dimensions unit : mm 3247B No.A0015-3/16 LA72700V Block Diagram and Application Circuit Example No.A0015-4/16 LA72700V 00p-1 ( Normally use : group-1 only ) D8 * D7 D6 D5 D4 D3 D2 0 0 1 1 * 0 1 * 0 1 * 0 1 * 0 1 * 0 1 * 0 1 D1 0 1 0 1 Condition Stereo SAP Both Prohibit Normal (Auto det) Forced Mono Normal (MUTE off) MUTE ALC off (Through) ALC on SAP LEVEL-1 SAP LEVEL-2 SIF mode Base Band mode Fix Prohibit (TEST MODE) *: Initial condition Read out data D8 D7 D6 0 0 1 0 1 D5 0 D4 0 D3 0 D2 0 D1 0 Condition Fixed Normal SAP det Normal Stereo det Test mode condition When STOP condition transform at Grp-1 data-end, controlled NORMAL mode. Grp-2(Only test condition: Normally, this data is no-need) D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Condition/Monitor position Normal (Usually, Fixed) TEST-1 SIF output TEST-2 SAP BPF TEST-3 SAP VCO TEST-4 ST VCO TEST-5 ADJ VCO TEST-6 dbx input TEST-7 L-R Demod output TEST-8 Pilot cancel TEST-9 dbx 2.19k LPF TEST-10 dbx 408 LPF TEST-11 dbx DET 10k LPF TEST-12 dbx SPEC 7.6k LPF TEST-13 dbx SPEC output TEST-14 (No operation) TEST-15 (No operation) No.A0015-5/16 LA72700V Pin Functions DC voltage No. Pin function AC level 1 PC_DC_IN DC: 3.8V AC: 2.4Vp-p AC coupling (Input) Input/output form Reference 2 PC_DCOUT DC: 3.8V AC: 2.4Vp-p AC coupling (Output) 3 PCSTFILT DC: 3.8V Stereo VCO PLL filter 4 PCPLDET DC: 3.8V Pilot level detect 5 PISIF DC: 3.7V Signal input Continued on next page. No.A0015-6/16 LA72700V Continued from preceding page. No. 6 Pin function GND CSAPDET DC: 2.8V SAP carrier level detect DC voltage AC level Input/output form Reference 8 9 NC PC FIL DC: 2.9V No connect SIF offset cancel 10 MUTE DC: 0V MUTE = 5V 11 SDA Serial data input 12 SCL Serial clock input Continued on next page. No.A0015-7/16 LA72700V Continued from preceding page. No. 13 Pin function PC DBXIN DC voltage AC level DC: 2.5V Offset cancel filter Input/output form Reference 14 PSTSENS DC: 3.1V Stereo det sensitivity change OPEN = default Insert resistor(30k or over) = Low sensitivity 15 PSAPSENS DC: 3.1V SAP detect sensitivity control OPEN = default controlled by insert resistor * see electrical reference 16 PCTNWID DC: 4.0V dbx RMS detect(wide band) 17 PCDETWID DC: 3.8V dbx wide detect Continued on next page. No.A0015-8/16 LA72700V Continued from preceding page. No. 18 Pin function PCTIMSPE DC voltage AC level DC: 3.8V dbx spectral detect Input/output form Reference 18 5kΩ OMP05019 19 PCDETSPE DC: 3.8V dbx RMS detect (Spectral band) 20 PCSPECIN DC: 3.8V dbx main signal V/I convert filter 21 PCDOSPE DC: 3.8V AC: 220mVp-p Offset cancel filter 22 PCDBXOUT DC: 3.8V AC: 220mVp-p AC coupling (Output) 23 PCDBX_IN AC coupling (Input) Continued on next page. No.A0015-9/16 LA72700V Continued from preceding page. No. 24 Pin function PCALCFIL DC voltage AC level DC: 0.6V ALC filter * When ALC function no-use, this terminal is open. Input/output form Reference 25 PORCH DC: 3.8V AC: 1.4mVp-p Line out R 26 POLCH DC: 3.8V AC: 1.4mVp-p Line out L 27 PCREG DC: 3.8V Reference Voltage Continued on next page. No.A0015-10/16 LA72700V Continued from preceding page. No. 28 Pin function PMAIN_IN DC voltage AC level DC: 3.5V AC: 220mVp-p AC coupling (Input) Input/output form Reference 29 PMAINOUT DC: 3.8V AC: 220mVp-p AC coupling (Output) 30 PCREG76 DC: 1.2V Regulator 31 32 VCC POLED DC* * See Mode table Mode out MONO = 0.9V SAP = 2.0V STEREO = 3.0V STEREO+SAP = 3.8V 33 PICLKFSC DC: 0V AC* * 200mVp-p Recommend Fsc input 3.579545MHz, 200mVp-p Continued on next page. No.A0015-11/16 LA72700V Continued from preceding page. No. 34 Pin function PCDJFIL DC voltage AC level DC: 2.5V Filter adjustment signal detect Input/output form Reference 35 PCPLC DC: 6.3V Pilot canceller reference-1 36 PCPLC2 DC: 6.3V Pilot canceller reference-2 No.A0015-12/16 LA72700V Serial Control (I2C) (1) Data Transfer Manual This LSI adopts control method (I2C -BUS) with serial data, and controlled by two terminals which called SCL (serial clock) and SDA (serial data). At first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this LSI pull down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 Defined by SCL rise down SDA during ‘H’ period. *2 Defined by SCL rise up SDA during ‘H’ period. (2) Transfer Data Format After transfer start condition, transfers slave address (1000000*) to SDA terminal, control data, then, stop condition (See figure 1). Slave address is made up of 7bits, *3 8th bit shows the direction of transferring data, if it is “L”, takes write mode (As this LSI side, this is input operation mode), and in case of ‘H’, reading mode (As this LSI side, this is output operation mode). Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled the transfer dates. *3 It is called R/W bit. Fig.1 DATA STRUCTURE " WRITE " mode START Condition Slave Address R/W L ACK Control data ACK STOP condition Fig.2 DATA STRUCTURE " READ " mode START condition Slave Address R/W H ACK Internal Data* ACK STOP condition * Output 5bits data as follows; bit8 is result of STERO DET (H: STEREO) bit7 is result of SAP DET (H: SAP) bit6 to bit1 are fixed to “L” No.A0015-13/16 LA72700V (3) Initialize This LSI is initialized for circuit protection. Initial condition is “0 (all bits)”. Parameter LOW level input voltage HIGH level input voltage LOW level output current SCL clock frequency Set-up time for a repeated START condition Hold time START condition. After this period, the first clock pulse is generated LOW period of the SCL clock Rise time of both SDA and SDL signals HIGH period of the SCL clock Fall time of both SDA and SDL signals Data hold time Data set-up time Set-up time for STOP condition BUS free time between a STOP and START condition Symbol VIL VIIH IOL fSCL tSU: STA tHD: STA tLOW tR tHIGH tF tHD: DAT tSU: DAT tSU: STO tBUF 0 4.7 4.0 4.7 0 4.0 0 0 250 4.0 4.7 1.0 1.0 Min -0.5 3.0 Max 1.5 5.5 3.0 100 Unit V V mA kHz µs µs µs µs µs µs µs ns µs µs Timing Chart No.A0015-14/16 LA72700V Measurement Circuit No.A0015-15/16 LA72700V Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 2005. Specifications and information herein are subject to change without notice. PS No.8340-16/16