LA72710V

Ordering number : ENA0237 Monolithic Linear IC LA72710V Overview For JPN TV Multi Channel Television Sound Decoder The LA72710V is a JPN MTS (Multi Channel Television Sound) Decoder. Features • With SIF circuit, alignment-free STEREO channel separation. • Separation is fine-tuned by input level adjustment. • Included filters are adjustment free. Functions • Stereo & Bilingual demodulate. • Stereo & Bilingual detection. • JUST CLOCK OUT. • Built-in ALC. Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Ta ≤ 70°C ∗ Conditions Ratings 9.6 610 -10 to +70 -55 to +150 unit V mW °C °C ∗ When mounted on a 114.3×76.1×1.6mm3 glass epoxy board. Operating Conditions at Ta = 25°C Parameter Recommended operating voltage Allowable operating voltage range Symbol VCC VCC op Conditions Ratings 9.0 8.5 to 9.5 unit V V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 83006 / 51106 MS OT B8-7330 No.A0237-1/10 LA72710V Electrical Characteristics at Ta = 25°C, VCC = 9.0V Ratings Parameter Current dissipation Input level MONO output level MONO L/R level difference MONO distortion MONO frequency characteristics MONO S/N STEREO output level STEREO distortion STEREO S/N Main output level Main distortion Main S/N SUB output level SUB distortion SUB frequency characteristics SUB Main S/N STEREO separation L → R STERO separation R → L Stay behind carrier level Stay behind carrier level Cross-talk MAIN → SUB Cross-talk SUB → MAIN MODE output MONO MODE output STEREO MODE output BILINGUAL Just Clock output High volt Just Clock output Low volt ALC level ALC Distortion Symbol ICC VSIN VOMN ∆VOMN THDM fcM1 SNM VOST THDS SNS VOMA THDMA SNMA VOSU THDSU fcSU SNSU SEPR SEPL CLSU CLMA CTSUB CTMA MODMO MODST MODBI JCH JCL VOALC THDALC Conditions No signal, Inflow current at Pin 19 fc = 4.5MHz fm = 1kHz, 100% Mod, Pre-Emphasis OFF fm = 1kHz, 100% Mod, Pre-Emphasis OFF fm = 1kHz, 100% Mod, Pre-Emphasis OFF fm = 10kHz/1kHz, 100% Mod, 15kHz LPF Pre-Emphasis OFF Non Mod, 15kHz LPF fm = 1kHz, 100% Mod, Cue (Stereo), 15kHz LPF fm = 1kHz, 100% Mod, Cue (Stereo), 15kHz LPF Sub Carrier (Non Mod), Cue (Stereo), 15kHz LPF fm = 1kHz, 100% Mod, Cue (Bilingual), 15kHz LPF fm = 1kHz, 100% Mod, Cue (Bilingual), 15kHz LPF Sub Carrier (Non Mod), Cue (Bilingual), 15kHz LPF fm = 1kHz, 100% Mod, Cue (Bilingual), 15kHz LPF fm = 1kHz, 100% Mod, Cue (Bilingual), 15kHz LPF fm = 10kHz/1kHz, 60% Mod, Cue (Bilingual), 15kHz LPF, Pre-Emphasis OFF Sub Carrier (Non Mod), Cue (Bilingual), 15kHz LPF fm = 1kHz (L-only), 60% Mod, Cue (Stereo), 15kHz LPF fm = 1kHz (R-only), 60% Mod, Cue (Stereo), 15kHz LPF Main = 0%, Sub = 0% (Carrier) Cue (Bilingual) Main = 0%, Sub = 0% (Carrier) Cue (Bilingual) Main: fm = 1kHz, 100% modulation, Cue (Bilingual), 15kHz LPF Sub: fm = 1kHz, 100% modulation, Cue (Bilingual), 15kHz LPF Input = Mono Signal Input = Stereo Signal Input = Bilingual Signal f = 400Hz (mono), 40%Mod f = 400Hz (mono), 10%Mod MONO 1kHz Mod 100% MONO 1kHz Mod 100% -11 -9.5 0.2 0.7 1.7 2.7 4 1 -8 0.5 1 2 3 1.3 2.3 3.3 V V V V V dBV % 45 55 dB 35 45 dB -55 -45 dBV -50 -40 dBV 30 35 dB 45 30 35 dB dB -18 -14 dB 1 2 % 50 -7.5 -6 -4.5 dB dBV 0.3 1 % -7.5 -6 -4.5 dBV 45 dB 0.7 1.5 % 50 -7.5 -6 -4.5 dB dBV -18 min 40 80 -7.5 -1.5 typ 50 90 -6 0 0.2 -14 max 60 100 -4.5 1.5 0.5 unit mA dBµV dBV dB % dB [Condition of input signal at pin 5] Deviation of SIF input MONO: (fm = 400Hz) 100% → 4.5MHz ± 25kHz Pre-Emphasis ON. [Output] L-ch : pin 14, R-ch : pin 13. No.A0237-2/10 LA72710V Package Dimensions unit : mm 3315 9.75 24 13 5.6 7.6 1 0.8 (0.48) 0.3 12 0.15 1.5MAX SANYO : SSOP24J(275mil) Block Diagram and Sample Application Circuit 0.1 (1.3) 0.5 No.A0237-3/10 LA72710V Pin Functions Pin No. 1 Pin Name AMDET Function Reference terminal of AM detection. DC voltage AC level Equivalent Circuit 2 3 16 DCFIL1 DCFIL1 DCFIL1 Absorbing the DC offset of signal line by external capacity. DC: 2.4V 4 FMFIL Filter terminal for making stable DC voltage of FM detection output in SIF part. Normally, use a condenser of 1µF. Increase the capacity value with concerning frequency characteristics of low level. 5 SIFIN Input terminal for SIF. The input impedance is about 5kΩ. Be care for about pattern layout of the input circuit, because of causing buzz-beat and buzz by leaking noise signal into the input terminal. (The noise signal depending on sound is particularly video signal and chroma signal and so on. VIF carrier becomes noise signal.) 6 7 GND JCKO 20dB amplifier output for JUST CLOCK. DC: 3.8V 8 CMPIN Comparator input for JUST CLOCK. DC: 3.8V Continued on next page No.A0237-4/10 LA72710V Continued from preceding page. Pin No. 9 Pin Name JCKRWO Function Rectangle wave output for JUST CLOCK. (OPEN Collector) 5V DC voltage AC level Equivalent Circuit 0V 10 MUTE MUTE control terminal. MUTE: 2.8V to 11 SDA Serial data input / output terminal. High: 3.5V to 5V Low: 0V to 1.5V 5V 0V 12 SCL Serial clock input terminal High: 3.5V to 5V Low: 0V to 1.5V 5V 0V 13 RCH Line Out (R) terminal. DC: 3.8V AC: -6dBV 14 LCH Line Out (L) terminal. 15 ALCDET ALC detection terminal. 17 REGFIL Filter terminal of reference voltage source. DC: 4.5V Continued on next page No.A0237-5/10 LA72710V Continued from preceding page. Pin No. 18 Pin Name PCREG Function Band gap source terminal block. DC voltage AC level DC: 1.2V Equivalent Circuit 19 20 VCC MODE Power supply terminal. Detection output for M.T.S. signal. BILINGUAL: 3.0V STEREO: MONO: 2.0V 1.0V DC: 9V 21 FSCIN Input terminal for FSC (3.58MHz). AC: 200mVp-p 22 PLLFIL Loop filter terminal. Automatic adjusting for PLL. 23 ST PHASE COMPARATOR input (STEREO). This detection pin becomes High (6.6V or more) when ST signal is input. 24 BIL PHASE COMPARATOR input (BILINGAL). This detection pin becomes High (6.6V or more) when BIL signal is input. No.A0237-6/10 LA72710V I2C BUS serial interface specification (1) Data Transfer Manual This IC adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL (serial clock) and SDA (serial data). At first, set up*1 the condition of starting data transfer, and after that, input 8 bit data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’ this IC pull down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 Defined by SCL rise down SDA during ‘H’ period. *2 Defined by SCL rise up SDA during ‘H’ period. (2) Transfer Data Format After transfer start condition, transfers slave address (1000 000*B) to SDA terminal, control data, then, stop condition (See figure 1). Slave address is made up of 7bits, 8th bit*3 shows the direction of transferring data, if it is ‘L’ takes write mode (As this IC side, this is input operation mode), and in case of ‘H’ reading mode (As this IC side, this is output operation mode). Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled the transfer dates. *3 It is called R/W bit. Fig.1 DATA STRUCTURE “WRITE” mode START Condition Slave Address R/WL ACK Control data ACK STOP condition Fig.2 DATA STRUCTURE “READ” mode START condition Slave Address R/WH ACK Internal Data * ACK STOP condition ∗ Output 8bits data as follows; bit8 is result of STERO DET bit7 is result of BILINGUAL DET bit6 to bit1 are fixed to ‘L’ (3) Initialize (H : STEREO) (H : BILINGUAL) This IC is initialized for circuit protection. Initial condition is “0 (All bits).” No.A0237-7/10 LA72710V I2C Timing Specifications Parameter LOW level input voltage HIGH level input voltage LOW level output current SCL clock frequency Set-up time for a repeated START condition Hold time START condition. After this period, the first clock pulse is generated LOW period of the SCL clock Rise time of both SDA and SDL signals HIGH period of the SCL clock Fall time of both SDA and SDL signals Data hold time Data set-up time Set-up time for STOP condition BUS free time between a STOP and START condition Symbol VIL VIH IOL fSCL tSU:STA tHD:STA tLOW tR tHIGH tF tHD:DAT tSU:DAT tSU:STO tBUF 0 4.7 4.0 4.7 0 4.0 0 0 250 4.0 4.7 1.0 1.0 min -0.5 3.0 max 1.5 5.5 3.0 100 unit V V mA kHz µs µs µs µs µs µs µs ns µs µs I2C Control Conditions Grp-1 D8 D7 D6 D5 D4 D3 D2 0 * 0 1 1 * 0 1 * 0 1 * 0 1 * 0 1 * 0 1 * 0 1 *:Initial condition D1 0 1 0 1 (SLAVE ADDRESS 80H) Condition Bilingual Main Sub (Prohibit) Normal Forced MONO Normal (MUTE Off) MUTE ALC Off (Through) ALC On JUST CLOCK Off JUST CLOCK On SIF Mode BASE BAND Mode Fix Prohibit (TEST Mode) Read out data D8 D7 D6 0 0 1 0 1 D5 0 D4 0 D3 0 D2 0 D1 0 Condition Fixed Normal Bilingual det Normal Stereo det No.A0237-8/10 LA72710V Mode Select (pin & I2C setting) Broadcast signal Bilingual MUTE pin10 L L L L * H STEREO L L * H MONO L * H *: Don’t care. D4 0 0 0 0 1 * 0 0 1 * 0 1 * I2C setting D3 0 0 0 1 * * 0 1 * * * * * D2 0 0 1 * * * * * * * * * * D1 0 1 0 * * * * * * * * * * LCH (pin14) MAIN MAIN SUB MAIN MUTE MUTE L L+R MUTE MUTE L+R MUTE MUTE MATRIX OUT RCH (pin13) SUB MAIN SUB MAIN MUTE MUTE R L+R MUTE MUTE L+R MUTE MUTE MODE BOTH MAIN SUB MONO MUTE MUTE STEREO MONO MUTE MUTE MONO MUTE MUTE READ MODE OUT D8 L L L L L L H H H H L L L D7 H H H H H H L L L L L L L 1V 2V MODE OUT Pin20 3V Serial Data Specification (I2C bus communication) MSB D8 TEST D7 SIF or BASE BAND D6 JUST CLK D5 ALC D4 NORMAL OUT MUTE D3 Forced MONO D2 LSB D1 MULTIPLEX mode select 0:OFF 1:ON 0:SIF 1:BASE BAND 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 00:BILINGUAL 01:MAIN 10:SUB 11:Unusable Note: Underline shows default setting. No.A0237-9/10 LA72710V Test Circuits Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. 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Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 2006. Specifications and information herein are subject to change without notice. PS No.A0237-10/10