LA73024AV

Ordering number : ENA0238 Monolithic Linear IC LA73024AV Overview Double Scart Interface IC This LA73024AV is a double scart interface IC. Functions • AV switches, • Changeable Gain AMP • 6dB AMP+driver • FSS output Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Symbol VCCV max VCCA max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg 24, 29 pin 14 pin Ta ≤ 80°C∗ Conditions Ratings 6.0 13.0 760 -20 to +80 -55 to +150 Unit V V mW °C °C ∗ When mounted on a 114.3×76.1×1.6mm3 glass epoxy board. Operating Conditions at Ta = 25°C Parameter Recommending operation voltage Symbol VCCV VCCA Operating voltage range VCCV op VCCA op Conditions pins 24 and 29 pin 14 pins 24 and 29 pin 14 Ratings 5.0 12.0 4.5 to 5.5 11.5 to 12.5 Unit V V V V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 83006 / 60206 MS OT B8-6818 No.A0238-1/12 LA73024AV Electrical Characteristics at Ta = 25°C, VCC = ±5.0V, VCCA = 12.0V Ratings Parameter Current dissipation 1 Current dissipation 2 Current dissipation 3 FSS output H voltage FSS output M voltage FSS output L voltage FSS output cut off current Symbol ICCV1 ICCV2 ICCA VHFSS VMFSS VLFSS ICUTOFF Conditions Pin 24 Flow in current when non-signal Pin 29 Flow in current when non-signal Pin 14 Flow in current when non-signal Serial control select FSS OUT H Serial control select FSS OUT M Serial control select FSS OUT L Flow out current when Pin 20 connecting to GND. External control terminal H voltage External control terminal L voltage VEXTH VEXTL RL = 1.8kΩ, VCC3 < 13V RL = 1.8kΩ, VCC3 = 5V RL = 10kΩ, VCC3 = 5V External control terminal drive current External mute control H External mute control L VMUTECTLH VMUTECTLL IDR RL = 1.8kΩ, VCC3 = 5V RL = 10kΩ, VCC3 = 5V External mute H, control voltage of Pin 9. External mute L, control voltage of Pin 9. M H min 16.0 12.0 17.0 VCCA-1.0 5.0 0 2.0 2.0 VCC3-0.2 0 0 2.2 400 4.0 0 typ 24.0 18.0 25.0 VCCA-0.5 6.0 0.1 3.61 3.78 VCC3 0.7 0.15 2.4 485 1.0 1.0 2.78 500 VCCV 1.0 max 32.0 24.0 33.0 VCCA 7.0 0.5 10.0 10.0 Unit mA mA mA V V V mA mA V V V mA µA V V Video switches part Voltage gain V1 Voltage gain V2 Voltage gain V3 Frequency characteristics DG differential gain DP differential phase Output voltage VG1V VG2V VG3V VF DG DP VOUT Pins 25 and 26 output, 100% white Pin 5 output G2 D6-L, 100% white Pin 5 output G2 D6-H,100% white f = 100kHz/7MHz VIN = 1Vp-p VIN = 1Vp-p Pins 25 and 26 DC voltage when non-signal. 5.6 -0.4 5.6 -0.5 -1.0 -1.5 6.1 0.1 6.1 -0.0 0.0 0.0 1.15 6.6 0.6 6.6 0.5 1.0 1.5 2.0 dB dB dB dB % deg V Audio switches part Voltage gain 1A Voltage gain 2A Voltage gain 3A Voltage gain 4A Voltage gain 5A Maximum output level Total harmonic distortion Output noise voltage Cross talk between channel Mute attenuation Input impedance Output off set voltage VG1A VG2A VG3A VG4A VG5A VOMAX THD VONOISE VCTKA VMUTEA ZIN VOFSET Off set voltage at the time of changeover SW. Serial control select 0dB. Serial control select 2dB. Serial control select 4dB. Serial control select 6dB. Serial control select 6dB. Output level at the time of f = 1kHz, THD = 2% VIN = 1Vrms, f = 1kHz, AMP 0dB Rg = 1kΩ, JIS-A FILTER VIN = 1Vrms, f = 1kHz VIN = 1Vrms, f = 1kHz 40 -20 0.06 -100 -90 -90 50 0 0.20 -90 -75 -75 60 20 % dBm dB dB kΩ mV -0.3 1.7 2.7 5.7 11.7 2 0.2 2.2 4.2 6.2 12.2 3.0 0.7 2.7 4.7 6.7 12.7 dB dB dB dB dB Vrms Design guarantee Items Ratings Parameter Mute attenuation Cross-talk between channel Symbol VMUTEV VCTKV Conditions VIN = 1Vp-p, f = 4.43MHz VIN = 1Vp-p, f = 4.43MHz Driver output terminated with 75Ω. min typ -60 -60 max -50 -50 Unit dB dB No.A0238-2/12 LA73024AV Package Dimensions unit : mm 3277 15.0 44 23 5.6 7.6 1 (0.68) 0.65 22 0.22 0.2 SANYO : SSOP44(275mil) 0.1 (1.5) 1.7max 0.5 No.A0238-3/12 LA73024AV Block Diagram and Sample Application Circuit No.A0238-4/12 LA73024AV Pin Functions Pin No. 1 2 10 11 15 16 33 34 36 37 3 4 19 35 Pin name AIN1R AIN1L AIN2R AIN2L AIN3R AIN3L AIN4L AIN4R AIN5L AIN5R EXTCTL1 EXTCTL2 EXTCTL3 EXTCTL4 OFF General purpose output. Open collector. 2.5mA, ON Function Audio input terminal. DC voltage 5.58V Equivalent circuit → 0.75V → OPEN 5 VOUT Video output terminal. Push-pull output Low-impedance. 1.10V 6 17 27 32 38 GND GND GND GND GND (EXT-75Ω Driver) (DEC-75Ω Deiver) 0V Continued on next page. No.A0238-5/12 LA73024AV Continued from preceding page. Pin No. 7 13 18 23 28 Pin name VIN1 VIN2 VIN3 VIN4 VIN5 Function Video input terminal. Sync-tip clamp input Hi-impedance. DC voltage 1.8V Equivalent circuit 8 PWRSAV Power save mode select pin. OPEN: L 0.2V 9 AUMUTE Control terminal for audio mute. OPEN: LOW 0.05V 12 REFFIL Terminal for Ref_DC ripple removing. 4.94V 14 VCC12 VCC for audio. Continued on next page. No.A0238-6/12 LA73024AV Continued from preceding page. Pin No. 20 Pin name FSSOUT Function FSS control terminal. Output H, M, L 3 values with serial control. M: 6V L: 0V DC voltage H: VCC-0.5V Equivalent circuit 21 DATA Serial data input terminal. Conformed to I2C BUS. 22 CLOCK Serial clock input terminal. Conformed to I2C BUS. 24 25 26 VCC5A VOUT75A VOUT75B Control VCC for Video. Power save → open Video driver output terminal. Push-pull output Low-impedance. 1.10V 29 VCC5B Always VCC for Video. Continued on next page. No.A0238-7/12 LA73024AV Continued from preceding page. Pin No. 30 31 42 43 Pin name AOUT2L AOUT2R AOUT3L AOUT3R Function Audio output terminal Push-pull output Low-Impedance DC voltage 4.91V Equivalent circuit 39 40 AOUT1L AOUT1R Audio output terminal Push-pull output Low-Impedance 4.91V 41 44 PWRMUTE1 PWRMUTE2 Output terminal of audio muting 0V Power Save LA73024AV has two supplies 5V for Video part and 12V for audio part and FSS output. LA73024AV separates perfectly 5V system from 12V system, so it can be individually movement. For example when in the stand-by mode, if you open 14 pins but 5V supplies 24 and 29 pins, Video part and serial control part work normally. In this case audio part and FSS output don’t work normally. And when you pull up 8pin and open 24 pin , IC chooses automatically video sw3-B.Consequently Ext input and Decoder output only move , you can save more power dissipation . Audio Mute LA73024AV builds in two mute transistors for reduce audio pop-noise when occur at power on and off. You can control both on serial control and on external parallel control for audio mute. No.A0238-8/12 LA73024AV Serial Control Specification Slave address MSB 1 0 0 1 0 0 0 LSB 0 ↑ Slave receiver A Data address (8bit) AP ↑ Stop condition Data format S Slave address (8bit) ↑ Start condition A Sub address (8bit) ↑ Acknowledge Sub address and data byte table Sub address Hexadecimal D8 SW1 00: C 01 (0000 0001) 01: B 10: A 11: A EXT CTL1 02 (0000 0010) 0: L 1: H EXT CTL2 0: L 1: H AMP GAIN VPS OUT 0: 0dB 1: 6dB D7 D6 SW2 00: D 01: C 10: B 11: A Data byte (Underline is initial setting.) D5 D4 SW3 00: C 01: B 10: A 11: * AUDIO AMP GAIN1 (DEC OUT) 000: 0dB 001: 2dB 010: 4dB 011: 6dB 100:12dB MUTE1 VSW1 OUT 03 (0000 0011) 0: through 1: MUTE 0: through 1: MUTE 0: through 1: MUTE 0: through 1: MUTE 0: through 1: MUTE 0: through 1: MUTE 0: L 1: H 0: L 1: H MUTE2 VSW2 OUT MUTE3 VSW3 OUT MUTE4 ASW1 OUT MUTE5 ASW2 OUT MUTE6 ASW3 OUT EXT CTL3 EXT CTL4 D3 D2 FSSOUT 00: HIGH 01: HIGH 10: MID 11: LOW AUDIO AMP GAIN2 (EXT OUT) 00: 0dB 01: 2dB 10: 4dB 11: 6dB D1 Data transfer I2C-BUS control system is adopted in SW IC and SW IC is controlled by SCL (Serial Clock) and SDA (Serial Data) At first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input the 8bits data which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data transfer order (MSB → LSB). The 9th bit is called as ACK (Acknowledge), SW IC sends [0] to the SDA terminal during SCL [1] period. So, please open the port of micro-processor during this period. LA73024AV adopt auto-increment, so you input only first sub-address data (called as Group) and you can transfer data in order. As thus the Data transfer Stop condition*2 is finished. *1 SDA rise up during SCI is [1] *2 SDA fall down during SCL is [1] No.A0238-9/12 LA73024AV Transfer data format The transfer data is composed by START condition, Slave address data*3, and STOP condition. After setting up the START condition, please transfer the Slave Address (regulated as “1001000” in SW IC). Group and next control data (Please see the Fig. 1) Slave Address is composed by 7bits, and this bit 8th bit*4 should be set as [0]. But SW IC is not equipped with such a data out function, please keep this bit as [0]. The both of Group data and control data are composed by 8bits, and the one control action is defined with combination of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by sending some control data together. The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. But LA73024AV adopt auto-increment, for example you can stop to transfer STOP condition after group 2 data . If you want to stop transfer action, please transfer the STOP condition without fail. *3 There are 3 control groups. *4 This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept mode with SW IC) and [1] means accept mode (send mode with SW IC) fundamentally. Data structure START condition Initialize SW IC is initialized as the following mode for circuit protection. Please see “Sub address and data byte table” on page 9. Characteristics of the SDA and SCL 1/0 stages for SW IC Parameter LOW level input voltage HIGH level input voltage LOW level output current SCL clock frequency Set-up time for a repeated START condition Hold time START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock Rise time of both SDA and SDL signals HIGH period of the SCL clock Fall time of both SDA and SDL signals Data hold time Data set-up time Set-up time for STOP condition BUS free time between a STOP and START condition Symbol VIL VIH IOL fSCL tSU: STA tHD: STA tLOW tR tHIGH tF tHD: DAT tSU: DAT tSU: STO tBUF 4.7 4.0 4.7 0 4.0 0 0 250 4.0 4.7 1.0 1.0 min 0 3.5 max 1.5 5.0 3.0 100 unit V V mA kHz Slave Address R/W ACK Group ACK Control data ACK … STOP condition µs µs µs µs µs µs µs ns µs µs Definition of timing No.A0238-10/12 LA73024AV Test Circuit No.A0238-11/12 LA73024AV Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 2006. Specifications and information herein are subject to change without notice. PS No.A0238-12/12