LA74308LP

Ordering number : ENA0898 LA74308LP Overview Monolithic Linear IC Audio Interface for DSC The LA74308LP is a SPEAKER AMP and MIC AMP built-in audio interface for DSC. It incorporates an 8/16kHz trap and supports CODECs with a sampling rate of 8kHz or 16kHz. Features • Three-wire type SERIAL communication • MIC AMP • MIC power supply incorporated (with built-in pull-up resistor) • ALC AMP • 4th order LPF + trap (compatible with REC/PB changeover, trap frequency selectable from 8kHz and 16kHz) • SPEAKER AMP (The BEEP signal can be mixed.), with electronic VOLUME (controlled by serial communication) • LINE output (with SERIAL MUTE and MUTE transistor) • STANDBY control Specifications Maximum Ratings at Ta=25°C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Ta≤85°C * Conditions Ratings 5.0 500 -10 to +85 -55 to +150 Unit V mW °C °C * Printed circuit board mounting condition (40mm × 50mm × 0.8mm: glass epoxy) 2S2P (Four layers printed circuit board) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 82907 TI IM 20060927-S00005 No.A0898-1/16 LA74308LP Operating Conditions at Ta = 25°C Parameter Recommended operating voltage Symbol VCCA VCCSP Allowable operating voltage range VCCAop VCCSPop Take care not to exceed Pd max. Conditions Ratings 3.0 3.3 2.7 to 3.6 2.7 to 3.6 Unit V V V V Electrical Characteristics at Ta=25°C, VCCA=3.0V, VCCSP=3.3V, f=1kHz, with the VREF capacitance charging circuit in the OFF MODE Parameter Circuit current VCCA current dissipation at no signal 1 VCCA current dissipation at no signal 2 VCCA standby current dissipation 1 VCCA standby current dissipation 2 VCCSP current dissipation at no signal 1 VCCSP current dissipation at no signal 2 VCCSP standby current dissipation 1 VCCSP standby current dissipation 2 REC output system REC reference output LEVEL REC reference output distortion ALC characteristics ALC distortion ALC IN max input level REC output noise voltage VOR HDR1 ALM ALMD VINRMX VNOR ALC IN, VIN=-53dBV ALC IN, VIN=-53dBV, THD: from 2nd to 5th harmonic ALC IN, VIN=-20dBV ALC IN, VIN=-20dBV, THD: from 2nd to 5th harmonic ALC IN LEVEL at which REC output THD (from 2nd to 5th harmonic) becomes 3% or less. ALC IN, no input, JIS-A Filter -70 LINE output system (LINE load = as measured at the 22kΩ end) LINE reference output LEVEL LINE reference output distortion LINE reference output noise voltage PB IN max input LEVEL LINE output frequency characteristics 1 LINE output frequency characteristics 2 LINE output frequency characteristics 3 SP output system (SP load = as measured at the 8Ω end) SP reference output LEVEL1 (Vol.MAX) SP reference output distortion SP reference output LEVEL2 (Vol.TYP) SP reference output LEVEL3 (Vol.MIN) SP reference output noise voltage SP maximum ratings output VNOSP VOMSP VOSP3 PB IN, VIN=-17dBV,Vol=MIN (EVR DATA=0) JIS-A Filter PB IN no input, Vol=MAX, JIS-A Filter PB IN, Vol=MAX, LEVEL at which THD=10% 200 THDSP VOSP2 PB IN, VIN=-17dBV, Vol=MAX, THD: from 2nd to 5th harmonic PB IN, VIN=-17dBV, Vol=TYP (EVR DATA=14) -18 VOSP1 PB IN, VIN=-17dBV, Vol=MAX (EVR DATA=31) -6 -3 0.4 -12 -80 -70 320 0 1 -6 -70 -64 dBV % dBV dBV dBV mW FEQP3 PB IN, VIN=-10dBV, comparison of f=8kHz/1kHz FEQP2 PB IN, VIN=-10dBV, comparison of f=4kHz/1kHz VOL HDL VNOL VINPMX FEQP1 PB IN, VIN=-17dBV PB IN, VIN=-17dBV, THD: from 2nd to 5th harmonic PB IN, no input, JIS-A Filter PB IN LEVEL at which LINE output THD (from 2nd to 5th harmonic) becomes 1% or less. PB IN, VIN=-10dBV, comparison of f=3kHz/1kHz -3.5 -2 -10 -55 -6 -30 -11 -9.5 0.1 -77 -8 0.2 -69 -9 dBV % dBV dBV dB dB dB -3 -11 -9.5 0.1 -1.8 0.3 1 -7 -60 -8 0.2 dBV % dBV % dBV dBV ICCA1 ICCA2 ICCAS1 ICCAS2 ICCS1 ICCS2 ICCSS1 ICCSS2 VCCA=3.0V:REC BLOCK(MIC/ALC/REC AMP) POWER SAVE MODE VCCA=3.0V, LINE/SP AMP POWER SAVE MODE VCCA=3.0V, during standby control V3=0V VCCA=3.0V, BIAS MODE VCCSP=3.3V, SPK POWER ON MODE VCCSP=3.3V, SPK POWER SAVE MODE VCCSP=3.3V, during standby control (0V applied to pin 3) VCCSP=3.3V, BIAS MODE 1 2 0.05 4.9 6.2 6.6 8.3 8.3 10.4 1 800 4 0.1 9 9 mA mA µA µA mA mA µA µA Symbol Conditions min Ratings typ max Unit Continued on next page. No.A0898-2/16 LA74308LP Continued from preceding page. Parameter MIC output system MIC voltage gain MIC output distortion MIC output noise voltage MIC IN max input level MIC VCC output voltage Control system Serial CLOCK frequency Serial input LOW level Serial input HIGH level FCLK SERLO SERHI 0 2.3 0.1 1 0.7 3.5 MHz V V VGMIC HDMIC VNOMIC VINMMX VMIC MIC IN, VIN=-36dBV MIC IN, VIN=-36dBV, THD: from 2nd to 5th harmonic MIC IN, no input, JIS-A Filter MIC IN LEVEL at which the MIC output THD (from 2nd to 5th harmonic) becomes 3% or less. At 6.2kΩ load 1.5 1.7 16 17 0.05 -94 18 0.1 -83 -25 1.9 dB % dBV dBV V Symbol Conditions min Ratings typ max Unit Package Dimensions unit : mm (typ) 3321 TOP VIEW 3.5 13 12 3.5 0.4 BOTTOM VIEW 0.35 0.35 18 19 24 7 6 0.2 1 0.75 TOP VIEW 0.0NOM 0.85MAX SANYO : VQLP24(3.5X3.5) 0.75 No.A0898-3/16 LA74308LP Description of the Content of Serial Communication DATA No. LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MSB 15 LINE MUTE Tr. VREF capacitance charging circuit SW MIC AMP POWER SW ALC AMP POWER SW REC/PB changeover SW LPF characteristics (TRAP) changeover SW REC AMP POWER SW LINE OUT POWER SW LINE MUTE SW SPK POWER SW DATA=1 DATA=2 DATA=4 DATA=8 DATA=16 BIAS MODE Parameter 0:OFF, 1:ON 0:OFF, 1:ON 0:ON, 1:OFF 0:ON, 1:OFF 0:PB, 1:REC 0:16kHz, 1:8kHz 0:ON, 1:OFF 0:ON, 1:OFF 0:OFF, 1:ON 0:ON, 1:OFF 1 1 1 1 1:VOL MAX Default 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0:VOL MIN (MUTE) * EVR setting (the numeral shown in the left is decimal. For characteristics, see P12.) 0:ACTIVE MODE, 1:BIAS MODE ∼ Serial Transmission Timing VIH CS tCS CLOCK tDS DATA LSB MSB tDH VIH VIL fMAX tWH tWL tCH tWC VIH VIL VIL • fMAX • tWL • tWH • tCS • tCH • tDS • tDH • tWC • VIH • VIL (Max clock frequency) (Clock pulse width: Low) (Clock pulse width: High) (Chip enable setup time) (Chip enable hold time) (Data setup time) (Data hold time) (Chip enable pulse width) (High voltage lower limit) (Low voltage upper limit) 1.0MHz 500ns or more 500ns or more 500ns or more 500ns or more 500ns or more 500ns or more 500ns or more 2.3V to 3.5V 0.0V to 0.7V No.A0898-4/16 LA74308LP POWER ON RESET Condition (SERIAL communication) H Power Supply L H STANDBY control (Pin 3) L HIGH period for about 2ms H POWER ON PULSE (Signal inside IC) L (First C.S.) Dummy communication H C.S. (Pin 6) L Dummy Data H Data (Pin 8) L First Data (Second C.S.) First DATA communication HIGH to cancel STANDBY H Clock (Pin 7) L Delay of several hundreds ns H POWER ON RESET (IC inside) L POWER ON RESET (default) state SERIAL communication condition (First DATA hold) The POWER ON RESET state covers a period up to the rise of the second C.S. input after fall of POWER ON PULSE generated inside IC when the power is supplied and the STANDBY control is canceled. is the dummy communication. Actually, because of delay of several hundreds ns in the IC, the first DATA condition begins in and the normal SERIAL communication condition begins after . No.A0898-5/16 LA74308LP BIAS MODE Canceling State (SERIAL communication) H Power Supply L Normally HIGH H STANDBY control (Pin 3) L HIGH period for about 5µs H POWER ON PULSE (Signal inside IC) L BIAS mode canceling H C.S. (Pin 6) L Data15=0 H Data (Pin 8) L (First C.S.) Dummy communication (Second C.S.) First DATA communication Normally HIGH Dummy Data First Data H Clock (Pin 7) L Delay of several hundreds ns H POWER ON RESET (IC inside) L POWER ON RESET (default) state SERIAL communication condition (First DATA hold) The POWER ON RESET state from the BIAS MODE covers the period from the rise of C.S for communication of canceling of the BIAS MODE to the second rise of CS input after the fall of POWER ON PULSE generated inside IC. is the dummy communication. Actually, because of delay of several hundreds ns in the IC, the first DATA condition begins in and the normal SERIAL communication condition begins after . No.A0898-6/16 Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output STANDBY pin Serial control setting No. Symbol Pin Conditions Pin Major conditions (for the serial control setting, see the table in the right) 0:OFF 1:ON 0:OFF 1:ON 0:ON 1:OFF 0:ON 1:OFF 0:PB 1:REC 0:16kHz 1:8kHz 0:ON 1:OFF 0:ON 1:OFF 0:OFF 1:ON 0:ON 1:OFF 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON LINE Voltage applied to Mute Tr. pin 3 VREF charging SW MIC P SW ALC P SW LPF TRAP REC P SW LINE P SW LINE Mute SPK P SW EVR1 DATA EVR2 DATA EVR4 DATA EVR8 DATA EVR16 DATA REC /PB SW BIAS MODE 0:ACTIVE 1:BIAS Circuit current 1 ICCA1 T11 VCCA=3.0V T11 No input 3.3V 0 0 1 1 0 1 1 0 1 0 0 0 0 3.3V 0 0 0 0 1 1 0 1 1 1 0 0 0 VREF capacitance charging circuit in the OFF MODE MIC/ALC/REC AMP POWER SAVE MODE 0 0 0 2 ICCA2 T11 VCCA=3.0V T11 No input VREF capacitance charging circuit in the OFF MODE LINE/SP AMP POWER SAVE MODE 0 0 0 3 ICCAS1 T11 VCCA=3.0V T11 No input 0V 0 0 0 0 0 1 0 0 1 0 0 With the STANDBY pin V3=0V 0 0 0 0 0 4 3.3V ICCAS2 T11 VCCA=3.0V T11 No input 0 0 0 0 0 1 0 0 1 0 3.3V 0 0 1 1 0 1 1 0 1 0 BIAS MODE 0 0 0 0 0 1 5 ICCS1 T22 VCCSP=3.3V No input T22 VREF capacitance charging circuit in the OFF MODE SPK POWER ON MODE 0 0 0 0 0 0 LA74308LP 6 0 0 ICCS2 T22 VCCSP=3.3V No input 3.3V 1 1 0 1 1 0 0V 0 0 1 1 0 1 1 0 T22 VREF capacitance charging circuit in the OFF MODE SPK POWER SAVE MODE 1 1 0 0 0 0 0 0 7 ICCSS1 T22 VCCSP=3.3V No input 3.3V 0 0 1 1 0 1 1 T22 With the STANDBY pin V3=0V 1 0 0 0 0 0 0 0 8 ICCSS2 T22 VCCSP=3.3V No input T22 BIAS MODE 0 1 0 0 0 0 0 0 1 REC output system 3.3V 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 9 VOR T14 VIN=-53dBV f=1kHz 3.3V 0 0 0 0 1 T12 400 to 20kHz LPF used SW14=A, SW16=B 10 HDR1 T14 VIN=-53dBV f=1kHz 3.3V 0 0 0 0 T12 400 to 20kHz LPF used, SW14=A SW16=B, THD: from 2nd to 5th harmonic 1 0 1 1 1 0 0 0 0 0 0 11 ALM T14 VIN=-20dBV f=1kHz 3.3V 0 0 0 T12 400 to 20kHz LPF used, SW14=A, SW16=B 1 1 0 1 1 1 0 0 0 0 0 0 12 ALMD T14 VIN=-20dBV f=1kHz T12 400 to 20kHz LPF used, SW14=A SW16=B, THD: from 2nd to 5th harmonic 0 1 1 0 1 1 1 0 0 0 0 0 0 Electrical Characteristics Measurement Method at Ta=25°C, VCCA=3.0V, VCCSP=3.3V, f=1kHz with the VREF capacitance charging circuit in the OFF MODE 13 VINRMX T14 3.3V 0 0 f=1kHz T12 400 to 20kHz LPF used, SW16=B Pin 14 level at which pin 12 becomes THD = 3% from 2nd to 5th harmonic) 3.3V 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 No.A0898-7/16 14 VNOR T14 No input T12 JIS-A FILTER used SW14=B, SW16=B 0 0 1 1 0 1 1 1 0 0 0 0 0 0 Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output STANDBY pin Serial control setting No. Voltage applied to pin 3 0:OFF 1:ON 0:OFF 1:ON 0:ON 1:OFF 0:ON 1:OFF 0:PB 1:REC 0:16kHz 1:8kHz 0:ON 1:OFF 0:ON 1:OFF 0:OFF 1:ON 0:ON 1:OFF 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON MIC P SW ALC P SW LPF TRAP REC P SW LINE P SW LINE Mute SPK P SW EVR1 DATA EVR2 DATA EVR4 DATA EVR8 DATA EVR16 DATA Symbol Pin Conditions Pin Major conditions (for the serial control setting, see the table in the right) LINE Mute Tr. VREF charging SW REC /PB SW BIAS MODE 0:ACTIVE 1:BIAS LINE output system 15 0 1 1 0 1 1 0 0 1 0 0 VOL1 T10 VIN=-17dBV f=1kHz 3.3V 0 3.3V 0 1 1 0 1 1 0 0 1 0 0 0 T5 400 to 20kHz LPF used SW10=A, SW16=A 0 0 0 0 16 HDL T10 VIN=-17dBV f=1kHz 3.3V 0 0 1 1 0 1 1 0 0 1 0 T5 400 to 20kHz LPF used, SW10=A SW16=A, THD: from 2nd to 5th harmonic 0 0 0 0 17 VNOL T10 No input T5 JIS-A FILTER used, SW10=B, SW16=A 3.3V 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 18 VINPMX T10 f=1kHz T5 400 to 20kHz LPF used, SW10=A, Pin 10 level at which pin 5 becomes THD = 3% (from 2nd to 5th harmonic) 3.3V 3.3V 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 19 FEQP1 T10 VIN=-10dBV f=3kHz 0 T5 f=3kHz/1kHz level ratio SW10=A, SW16=A 0 0 0 0 0 0 20 FEQP2 T10 VIN=-10dBV f=4kHz 3.3V 0 0 1 1 0 1 1 0 T5 f=4kHz/1kHz level ratio SW10=A, SW16=A 1 0 0 0 0 0 0 LA74308LP 21 FEQP3 T10 VIN=-10dBV f=8kHz T5 f=8kHz/1kHz level ratio SW10=A, SW16=A 0 1 0 0 0 0 0 0 SPK output system (SPK end: measured with 8Ω ) 3.3V 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 0 22 VOSP1 T10 VIN=-17dBV f=1kHz 3.3V 0 0 1 1 0 1 T21 T23 400 to 20kHz LPF used Vol.=MAX (EVR DATA=31) 23 THDSP T10 VIN=-17dBV f=1kHz T21 T23 400 to 20kHz LPF used, Vol.=MAX THD: from 2nd to 5th harmonic 1 1 1 0 1 1 1 1 1 0 24 3.3V 0 0 1 1 VOSP2 T10 VIN=-17dBV f=1kHz T21 T23 400 to 20kHz LPF used Vol.=TYP (EVR DATA=14) 0 1 1 1 1 0 0 1 1 1 0 0 25 3.3V 0 VOSP3 T10 VIN=-17dBV f=1kHz 0 1 T21 T23 JIS-A FILTER used Vol.=MIN (EVR DATA=0) 1 0 1 1 1 1 0 0 0 0 0 0 0 26 3.3V 0 VNOSP T10 No input T21 T23 JIS-A FILTER used Vol.=MAX (EVR DATA=31) 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 No.A0898-8/16 3.3V 0 27 VOSSP T10 f=1kHz T21 T23 400 to 20kHz LPF used Vol.=MAX (EVR DATA=31) Level at which Vol.=MAX and THD=10% (from 2nd to 5th harmonic) 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output STANDBY pin Serial control setting No. Voltage applied to pin 3 0:OFF 1:ON 0:OFF 1:ON 0:ON 1:OFF 0:ON 1:OFF 0:PB 1:REC 0:16kHz 1:8kHz 0:ON 1:OFF 0:ON 1:OFF 0:OFF 1:ON 0:ON 1:OFF 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON Symbol Pin Conditions Pin Major conditions (for the serial control setting, see the table in the right) LINE Mute Tr. MIC P SW ALC P SW LPF TRAP REC P SW LINE P SW LINE Mute SPK P SW EVR1 DATA EVR2 DATA EVR4 DATA EVR8 DATA EVR16 DATA VREF charging SW REC /PB SW BIAS MODE 0:OFF 1:ON 0:ACTIVE 1:BIAS MIC Output system 28 0 VGMIC T17 VIN=-36dBV T16 f=1kHz 3.3V 0 0 0 1 1 0 1 1 1 0 0 400 to 20kHz LPF used, SW17=A 0 0 0 0 29 3.3V 0 0 0 1 1 0 1 1 1 0 HDMIC T17 VIN=-36dBV T16 f=1kHz 400 to 20kHz LPF used, SW17=A THD: from 2nd to 5th harmonic 0 0 0 0 0 0 30 VNOMIC T17 3.3V 0 0 0 1 1 0 1 1 No input T16 JIS-A FILTER used, SW17=B 0 1 0 0 0 0 0 0 LA74308LP 31 0 VINMMX T17 3.3V 0 0 0 1 1 0 f=1kHz T16 400 to 20kHz LPF used, SW17=A Pin 17 level at which pin 16 becomes THD = 3% (from 2nd to 5th harmonic) 1 1 1 0 0 0 0 0 0 32 VMIC 0 0 T17 No input T18 Pin 18 Measurement of output voltage (under 6.2kΩ load) SW18=ON 3.3V 0 0 1 1 0 1 1 1 0 0 0 0 0 0 No.A0898-9/16 LA74308LP Description of Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Speaker input EVR output STANDBY control LINE output LINE MUTE Tr. output C.S. input CLOCK input DATA input GND PB input VCCA REC output ALC detection ALC input 2nd order HPF MIC output MIC input INT power supply for MIC Ripple rejection for VREFL SPK GND Speaker positive-phase output VCCSP Speaker negative-phase output SPK GND Pin Description No.A0898-10/16 LA74308LP Block Diagram T16 T17 600Ω A SW17 0.01µF SW18 6.2kΩ 19 VREF + T21 21 VCCSP T22 3.3V 1µF T23 +8dB 24 3 0.1µF T2 T5 22kΩ V3 T3 STANDBY CTL LINE OUT 2kΩ 1 2 4 5 6 T6 C.S LOGIC MIC IN MIC OUT A B T14 ALC IN SW16 0.1µF SW14 B Rg=1kΩ + 0.47µF A ∼ ∼ B 6.2kΩ 18 17 +17dB + R 16 15 100kΩ P 14 13 DET 2.2kΩ MIC VCC VREF +17dB ALC +18dB 12 +9dB 11 + T12 REC OUT T11 VCCA 0.1µF B SW10 A GND Rg=1kΩ DATA ∼ 20 P LPF R 4.7µF REC:50kΩ/PB:200kΩ VREF charging circuit T10 10 PB IN A SPK8Ω + 22 EVR 9 +10Ω MUTE CTL 23 +8dB MUTE 8 7 T7 (CLOCK) SPK GND 0.1µF No.A0898-11/16 LA74308LP LPF Characteristics LA74308LP LPF characteristics 2.00E+01 0.00E+00 -2.00E+01 Response [dB] fs=8kHz mode -4.00E+01 fs=16kHz mode -6.00E+01 -8.00E+01 -1.00E+02 1.00E+02 1.00E+03 Frequency [Hz] 1.00E+04 1.00E+05 EVR Characteristics LA74308LP EVR characteristics (At PB IN reference input = -9dBV) 0 -10 -20 -30 GAIN [ dB ] -40 -50 -60 -70 -80 -90 0 5 10 15 20 25 30 35 5-bit data (decimal) SPK Output Level & Distortion Rate LA74308LP SPK output & THD characteristics (PB IN Max input -9dBV) 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 5 10 15 20 25 30 35 5-bit data (decimal) 14 12 10 8 6 4 2 0 THD: from 2nd to 5th harmonic [ % ] SPK output THD SPK8 Ω output [ W ] No.A0898-12/16 LA74308LP LA74308LP Input/output Pattern Table PIN 1 Pin Name SP IN DC voltage 1.27V AC voltage At PB reference input Output level = -9dBV (EVR MAX) Description of functions Speaker input pin Equivalent circuit diagram in pin VCCSP(=3.3V) 400Ω 11kΩ 1 23 SPK OUT1.27V At PB reference input Output level = -9dBV (EVR MAX) Speaker negative-phase output pin 23 2 EVR OUT 1.5V EVR output pin VCC(=3.0V) 10kΩ 2 35kΩ 12.5kΩ VREFL 3 STANDBY L STANDBY control pin 2V or more: STANDBY canceled 70kΩ 3 50kΩ 4 LINE OUT LINE output pin VCC(=3.0V) 4 2kΩ 26kΩ 14kΩ VREFL 5 LINE MUTE 1.5V At PB reference input Output level = -9dBV LINE output mute transistor 5 10 Ω 6 CS CS input pin 6 7 7 CLOCK CLOCK input pin 60kΩ Ω 50kΩ 8 8 DATA DATA input pin Continued on next page. No.A0898-13/16 LA74308LP Continued from preceding page. PIN 9 10 Pin Name GND PB IN DC voltage 0V 1.5V Reference input level =-17dBV AC voltage Description of functions GND pin PB input pin Equivalent circuit diagram in pin VCC(=3.0V) 10 49.5kΩ 500Ω 11 12 VCC REC OUT 3V 1.5V Reference input level =-9dBV Power supply pin R output pin VCC(=3.0V) 12 500Ω 11kΩ 6k Ω VREF 13 ALC DET ALC detection pin VCC(=3.0V) 1k Ω 13 500Ω 14 ALC IN (REC) 1.5V Reference input level =-53dBV Max input level =-8dBV ALC input pin VCC(=3.0V) 14 EVR IN (PB) 1.5V EVR input pin 500Ω REC:50kΩ PB:200kΩ VREF 15 HPF 1.5V Used when forming the 2nd order HPF VCC(=3.0V) 15 100kΩ Continued on next page. No.A0898-14/16 LA74308LP Continued from preceding page. PIN 16 Pin Name MIC OUT (REC) DC voltage 1.5V AC voltage Description of functions MIC output pin (for REC mode) Equivalent circuit diagram in pin VCC(=3.0V) LPF OUT (PB) LPF output pin (for PB mode) 16 500Ω 17 MIC IN 1.5V Reference input level =-70dBV Max input level =-25dBV MIC input pin VCC(=3.0V) 500Ω 17 70kΩ VREFL 18 MIC VCC 2.30V MIC power pin VCC(=3.0V) 18 2.2kΩ 28kΩ 19 VREFL 2.30V MIC VCC and VREFL ripple rejection pin VCC(=3.0V) 400Ω 19 500Ω 200kΩ 20 24 21 SP GND SPK OUT+ 0V 1.27V At PB reference input Output level = -9dBV (EVR MAX) Speaker GND pin Speaker positive-phase output pin VCCSP(=3.3V) 21 10kΩ 10.7kΩ 23 22 VCCSP 3.3V Speaker power pin No.A0898-15/16 LA74308LP Application Circuit MIC IN 0.01µF 0.01µF 0.47µF 18 4.7µF + 2.2kΩ 19 MIC VCC VREF 20 SPK 8Ω 21 17 + - 16 15 14 13 DET 0.1µF 12 REC OUT R P ALC P R LPF 11 VREF CHARGE REC: 50kΩ / PB: 200kΩ + VCCA 1µF 3.0V PB IN 10 0.1µF VCCSP + 3.3V 1µF 22 EVR +23 MUTE MUTE CTL 9 8 DATA 24 LOGIC 7 CLOCK 1 0.1µF 2 0.1µF 3 0.1µF 4 5 6 C. S. BEEP IN STAND-BY LOW LINE OUT SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2007. Specifications and information herein are subject to change without notice. PS No.A0898-16/16