LA74310LP

Ordering number : ENA0904 Monolithic Linear IC LA74310LP Overview Audio Interface for DSC + Video Driver The LA74310LP is an AV interface IC for digital still cameras (DSCs). It incorporates all the functions necessary for analog audio signal processing for microphone and loudspeaker amplifiers. It also incorporates video output drivers that require no output coupling capacity. The IC is ideal for reducing the number of components and further miniaturization of digital still cameras. Features AUDIO INTERFACE block • Three-wire type SERIAL communication • MIC AMP, MIC power supply incorporated (with built-in pull-up resistor) • ALC • PB input method: Analog or digital for inputting (ΔΣ) signal • 3rd order LPF (for REC/PB switching control, option of fc=4kHz or 11kHz) • SPEAKER AMP (The BEEP signal can be mixed.), with electronic VOLUME (controlled by Serial communication) • LINE output (with SERIAL MUTE) • STANDBY control (current drain < 10μA) VIDEO DRIVER block • Not requires output coupling capacity • Low voltage drive (VCC=2.7V to 3.6V) • V sag does not occur • 6th order LPF (fc=9MHz) is built-in. • 0μA current dissipation on standby mode. • 3 ways amplifier gains (6, 12, 16dB) can be selected. (Pin control (GND/Open/VCC)) • The video output has the capacity where one load of 75Ω impedance can be driven. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 91207 TI IM B8-9167 No.A0904-1/22 LA74310LP Specifications Maximum Ratings at Ta=25°C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Ta≤80°C * Conditions Ratings 4.0 550 -10 to +80 -55 to +150 Unit V mW °C °C * Substrate mounting condition (40mm × 50mm × 0.8mm: glass epoxy) 2S2P (Four layers substrate) Operating Conditions at Ta = 25°C Parameter Recommended supply voltage Symbol VCC VCCA VCCSP Allowable operating voltage range VCC VCCA VCCSP Take care not to exceed Pd max. Conditions Ratings 3.1 3.0 3.3 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 Unit V V V V V V Electrical Characteristics of AUDIO Block at Ta=25°C, VCCA=3.0V, VCCSP=3.3V, f=1kHz, with the VREF capacitance charging circuit in the OFF MODE Parameter Circuit current VCCA current dissipation at no signal 1 VCCA current dissipation at no signal 2 VCCA current dissipation at no signal 3 VCCA standby current dissipation Current dissipation at no signal 5 Current dissipation at no signal 6 VCCSP standby current dissipation REC output system REC reference output LEVEL REC reference output distortion ALC characteristics 1 ALC distortion 1 ALC characteristics 2 ALC distortion 2 ALC IN max input level REC output noise voltage REC output frequency characteristics 1 REC output frequency characteristics 2 REC output frequency characteristics 3 VOR HDR ALM1 ALMD1 ALM2 ALMD2 VINRMX VNOR FEQR1 FEQR2 FEQR3 ALC IN, VIN=-49dBV ALC IN, VIN=-49dBV, THD: from 2nd to 5th harmonic ALC IN, VIN=-33dBV (standard+16dB) ALC IN, VIN=-33dBV (standard+16dB), THD: from 2nd to 5th harmonic ALC IN, VIN=-17dBV (standard+32dB) ALC IN, VIN=-17dBV (standard+32dB), THD: from 2nd to 5th harmonic ALC IN LEVEL at which REC output THD (from 2nd to 5th harmonic) becomes 3% or less. ALC IN, no input, JIS-A Filter ALC IN, VIN=-33dBV, comparison of f=4kHz/1kHz ALC IN, VIN=-33dBV, comparison of f=22kHz/1kHz ALC IN, VIN=-33dBV, comparison of f=100kHz/1kHz -5 -77 -3.5 -33 -60 -11 -11 -16.5 -15.5 0.05 -8 0.15 -8 0.2 -14.5 0.1 -5 0.5 -5 1 -10 -68 -2 -25 -55 dBV % dBV % dBV % dBV dBV dB dB dB ICCA1 ICCA2 ICCA3 ICCAS ICCSP1 ICCSP2 ICCSPS VCCA=3.0V VCCA=3.0V: REC BLOCK (MIC/ALC/REC AMP) POWER SAVE MODE VCCA=3.0V: LINE AMP POWER SAVE MODE VCCA=3.0V: during standby control (23PIN=0V application) VCCSP=3.3V: SPK POWER ON MODE VCCSP=3.3V: SPK POWER SAVE MODE VCCSP=3.3V: during standby control (23PIN=0V application) 1.2 2.5 0.05 5.5 7 5 6.5 9.4 6.7 8.7 11.8 8.4 10.9 1 5 0.1 10 mA mA mA μA mA mA μA Symbol Conditions min Ratings typ max Unit Continued on next page. No.A0904-2/22 LA74310LP Continued from preceding page. Parameter LINE output system LINE reference output LEVEL LINE reference output distortion rate LINE reference output noise voltage PB IN max input LEVEL LINE output frequency characteristics 1 LINE output frequency characteristics 2 LINE output frequency characteristics 3 LINE output level (ΔΣ mode) VOL HDL VNOL VINPMX FEQP1 FEQP2 FEQP3 VIDVOL PB IN, VIN=-15dBV PB IN, VIN=-15dBV, THD: from 2nd to 5th harmonic PB IN, no input, JIS-A Filter PB IN LEVEL at which LINE output THD (from 2nd to 5th harmonic) becomes 3% or less. PB IN, VIN=-8dBV, comparison of f=4kHz/1kHz PB IN, VIN=-8dBV, comparison of f=22kHz/1kHz PB IN, VIN=-8dBV, comparison of f=100kHz/1kHz PB IN, PWM signals, digital input MODE (see supplements: p.8 Note26) SP output system (SP load = as measured at both ends of 8Ω) SP reference output LEVEL1 (Vol.MAX) SP reference output distortion SP reference output LEVEL2 (Vol.TYP) SP reference output LEVEL3 (Vol.MIN) SP reference output noise voltage SP maximum ratings output MIC output system MIC voltage gain MIC output distortion MIC output noise voltage MIC IN max input level MIC VCC output voltage Control system Serial CLOCK frequency Serial input LOW level Serial input HIGH level FCLK SERLO SERHI 0 2.3 1.25 1.5 0.7 3.5 MHz V V VGMIC HDMIC VNOMIC VINMMX VMIC MIC IN, VIN=-39dBV MIC IN, VIN=-39dBV, THD: from 2nd to 5th harmonic MIC IN, no input, JIS-A Filter MIC IN LEVEL at which the MIC output THD (from 2nd to 5th harmonic) becomes 3% or less. At 6.2kΩ load 1.5 1.7 19 20 0.02 -94 21 0.1 -83 -22 1.9 dB % dBV dBV V VOSP1 THDSP VOSP2 VOSP3 VNOSP VOMSP PB IN, VIN=-15dBV, Vol=MAX (Serial DATA=31) PB IN, VIN=-15dBV, Vol=MAX, THD: from 2nd to 5th harmonic PB IN, VIN=-15dBV, Vol=TYP (Serial DATA=17) PB IN, VIN=-15dBV, Vol=MIN (Serial DATA=0), JIS-A Filter PB IN, no input, Vol=MAX, JIS-A Filter PB IN, Vol=MAX, LEVEL at which THD=10% 200 -19 -5 -2 0.4 -13 -80 -76 340 1 1 -7 -70 -70 dBV % dBV dBV dBV mW -13 -5 -3.5 -33 -65 -11.5 -12 -11 0.1 -85 -10 0.2 -77 -5 -2 -25 -60 -10 dBV % dBV dBV dB dB dB dBV Symbol Conditions min Ratings typ max Unit No.A0904-3/22 LA74310LP Electrical Characteristics of VIDEO Block at Ta=25°C, VCC=3.1V Parameter Circuit current VCC current dissipation 1 (VIN =White50%) VCC current dissipation 2 (Non-signal mode) VCC current dissipation 3 (Standby mode) VIDEO block Voltage gain V6 Voltage gain V12 Voltage gain V16 Frequency characteristics DG / Differential Gain DP / Differential Phase Control pin block Standby control pin H voltage (SET=STANDBY MODE) Standby control pin L voltage (SET=ACTIVE MODE) Gain selection control pin H voltage (SET=16dB) Gain selection control pin M voltage (SET=12dB) Gain selection control pin L voltage (SET=6dB) Vth-G-L Vth-G-M Vth-G-H Vth-Stby-L Voltage range of the pin 34 to achieve active mode Voltage range of the pin 32 to achieve an amp. gain of 16dB Voltage range of the pin 32 to achieve an amp. gain of 12dB Voltage range of the pin 32 to achieve an amp. gain of 6dB Vth-Stby-H Voltage range of the pin 34 to achieve ICC≤5μA VCC-0.5 GND VCC-0.3 1.0 GND 1.2 (Open) VCC 0.3 VCC 1.4 0.3 V V V V V Vg-L Vg-M Vg-H Vf Dg Dp VIN=1Vpp 100% White, 32PIN=Low (GND) VIN=0.5Vpp 100% White, 32PIN=MID (Open) VIN=0.317Vpp 100% White, 32PIN=High (VCC) f=100kHz/5MHz VOUT=2Vpp (Modulated Ramp) VOUT=2Vpp (Modulated Ramp) 5.7 11.7 15.7 -1.5 -2.0 -2.0 6.2 12.2 16.2 -0.5 0.0 0.0 6.7 12.7 16.7 +0.5 +2.0 +2.0 dB dB dB dB % Deg ICC ICC2 ICC-Stby Input=White50%, 34PIN=Low Input=no input, 34PIN=Low 34pin=Open (High) 14 7 22 11.5 0 30 15 5 mA mA μA Symbol Conditions min Ratings typ max Unit Package Dimensions unit : mm (typ) 3302A Top View Bottom View 0.35 5.0 21 20 5.0 30 0.35 (0.7) 31 0.4 40 11 10 0.85MAX 0.2 1 (0.7) 0.05 0 NOM SANYO : VQLP40(5.0X5.0) No.A0904-4/22 LA74310LP Description of the Content of Serial Communication DATA No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DUMMY LPF Cut-off frequency SW VREF capacitor charging circuit control SW MIC AMP POWER SW ALC AMP POWER SW LPF1 MODE SW LPF1/LPF2 selection SW REC BLOCK POWER SW LINE OUT POWER SW LINE MUTE SW SPK POWER SW DATA=1 DATA=2 DATA=4 DATA=8 DATA=16 0:11kHz, 1:4kHz 0:ON, 1:OFF 0:ON, 1:OFF 0:ON, 1:OFF 0:PB MODE1, 1:REC MODE 0:LPF1, 1:LPF2 0:ON, 1:OFF 0:ON, 1:OFF 0:ON, 1:OFF 0:ON, 1:OFF 1 1 1 1 1: VOL MAX to 0 0 0 0 0: VOL MIN (MUTE) * EVR setting (the numeral shown in the left is decimal. For characteristics, see P12.) Parameter Default 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 Serial Transmission Timing VIH CS tCS CLOCK tDS DATA LSB MSB tDH VIH VIL fMAX tWH tWL tCH tWC VIH VIL VIL • fMAX • tWL • tWH • tCS • tCH • tDS • tDH • tWC • VIH • VIL (Max clock frequency) (Clock pulse width: Low) (Clock pulse width: High) (Chip enable setup time) (Chip enable hold time) (Data setup time) (Data hold time) (Chip enable pulse width) (High voltage lower limit) (Low voltage upper limit) 1.5MHz 333ns or more 333ns or more 333ns or more 333ns or more 333ns or more 333ns or more 333ns or more 2.3V to 3.5V 0V to 0.7V No.A0904-5/22 LA74310LP POWER ON Condition (SERIAL communication) H Power Supply L H ↑ HIGH to cancel STANDBY STANDBY control (Pin No 23) L H HIGH period for about 2ms POWER ON PULSE (IC inside) L H C.S. L Dummy communication H POWER ON RESET (IC inside) ← First DATA → communication ← → Delay of several hundreds ns L POWER ON RESET state → ←SERIAL communication condition ↑ First DATA hold The POWER ON RESET state covers a period up to the rise of the second C.S. input after fall of POWER ON PULSE generated inside IC when the power is applied and the STANDBY control is canceled. is the dummy communication. Actually, because of delay of several hundreds ns in the IC, the first DATA condition begins in and the normal SERIAL communication condition begins after . No.A0904-6/22 Input 0 DMY (1,*):REC (0,0):PB Analog (0,1):PB Digital 0:ON 1:OFF 0:ON 1:OFF 0:ON 1:OFF 0:ON 1:OFF 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON * * 0:11kHz 1:4kHz 0:ON 1:OFF 0:ON 1:OFF 0:ON 1:OFF LPF MODESW REC P SW LINE P SW LINE Mute SPK P SW EVR1 DATA EVR2 DATA EVR4 DATA EVR8 DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output STANDBY pin Serial control setting No. Symbol Voltage applied to pin 23 LPF C SW CHRG P SW MIC P SW ALC P SW Pin Conditions Pin Major conditions (for the serial control setting, see the table in the right) EVR16 DATA 0:OFF 1:ON Circuit current 3.3V 3.3V 3.3V 0V 3.3V 3.3V 0V 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ICCA1 29 VCCA=3.0V No input 29 VREF capacitance charging circuit in the OFF MODE 2 ICCA2 29 VCCA=3.0V No input 29 VREF capacitance charging circuit in the OFF MODE MIC/ALC/REC AMP POWER SAVE MODE 3 ICCA3 29 VCCA=3.0V No input 29 VREF capacitance charging circuit in the OFF MODE LINE AMP POWER SAVE MODE 4 ICCAS 29 VCCA=3.0V No input 29 With the STANDBY pin (23PIN)=0V 5 ICCS1 16 VCCSP=3.3V No input 16 VREF capacitance charging circuit in the OFF MODE SPK AMP ON MODE 6 ICCS2 16 VCCSP=3.3V No input 16 VREF capacitance charging circuit in the OFF MODE SPK AMP POWER SAVE MODE 7 ICCSPS 16 VCCSP=3.3V No input 16 With the STANDBY pin (23PIN)=0V REC output system 3.3V 0 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 8 VOR 7 VIN=-49dBV f=1kHz 3.3V 0 1 1 0 0 1 0 0 1 5 400 to 20kHz LPF used LA74310LP 9 HDR1 7 VIN=-49dBV f=1kHz 3.3V 0 1 1 0 0 1 0 0 5 400 to 20kHz LPF used THD: from 2nd to 5th harmonic 0 1 0 0 0 0 0 10 ALM1 7 VIN=-33dBV f=1kHz 3.3V 0 1 1 0 0 1 0 5 400 to 20kHz LPF used 1 0 1 0 0 0 0 0 11 ALMD1 7 VIN=-33dBV f=1kHz 3.3V 0 1 1 0 0 1 5 400 to 20kHz LPF used THD: from 2nd to 5th harmonic 0 1 0 1 0 0 0 0 0 12 ALM2 7 VIN=-17dBV f=1kHz 3.3V 0 1 1 0 0 5 400 to 20kHz LPF used 0 0 1 0 1 0 0 0 0 0 13 ALMD2 7 VIN=-17dBV f=1kHz 3.3V 0 1 1 0 0 5 400 to 20kHz LPF used THD: from 2nd to 5th harmonic 1 0 0 1 0 1 0 0 0 0 0 14 VINRMX 7 f=1kHz 5&7 400 to 20kHz LPF used Pin 7 level at which pin 5 becomes THD = 3% (from 2nd to 5th harmonic) 3.3V 0 1 1 0 1 0 0 1 0 1 0 0 0 0 0 15 VNOR 7 No input 5 JIS-A FILTER used 0 1 0 0 1 0 1 0 0 0 0 0 16 FEQR1 7 1 VIN=-33dBV f=4kHz 3.3V 0 3.3V 0 1 5 f=4kHz/1kHz level ratio 1 0 0 1 0 0 1 0 1 0 0 0 0 0 17 FEQR2 7 VIN=-33dBV f=22kHz 3.3V 0 5 f=22kHz/1kHz level ratio 1 0 0 1 0 0 1 0 1 0 0 0 0 0 Method of Measuring Electric Characteristics of AUDIO Block at Ta=25°C, VCCL=3.0V, VCCSP=3.3V, f=1kHz VREF capacitor charging circuit OFF MODE No.A0904-7/22 1 18 FEQR3 7 VIN=-33dBV f=100kHz 5 f=100kHz/1kHz level ratio 1 0 0 1 0 0 1 0 1 0 0 0 0 0 Input 0 LPF MODESW (1,*):REC (0,0):PB Analog (0,1):PB Digital 0:ON 1:OFF 0:ON 1:OFF 0:ON 1:OFF 0:ON 1:OFF 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON REC P SW 0:OFF 1:ON LINE P SW LINE Mute SPK P SW EVR1 DATA EVR2 DATA EVR4 DATA EVR8 DATA DMY LPF C SW 0:11kHz 1:4kHz 0:ON 1:OFF 0:ON 1:OFF 0:ON 1:OFF CHRG P SW MIC P SW ALC P SW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EVR16 DATA 0:OFF 1:ON Output STANDBY pin Serial control setting No. Symbol Pin * * Conditions Pin Major conditions (for the serial control setting, see the table in the right) Voltage applied to pin 23 LINE output system 3.3V 3.3V 3.3V 0 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 1 1 0 0 0 0 0 3.3V 3.3V 3.3V 3.3V 3.3V 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 VOL1 2 24 400 to 20kHz LPF used 20 HDL 2 VIN=-15dBV f=1kHz VIN=-15dBV f=1kHz 24 400 to 20kHz LPF used THD: from 2nd to 5th harmonic 21 VNOL 2 No input 24 JIS-A FILTER used 22 VINPMX 2 f=1kHz 24 & 2 400 to 20kHz LPF used Pin 2 level at which pin 24 becomes THD = 3% (from 2nd to 5th harmonic) 23 FEQP1 2 24 f=4kHz/1kHz level ratio 24 FEQP2 2 24 f=22kHz/1kHz level ratio 25 FEQP3 2 24 f=100kHz/1kHz level ratio 26 VIDVOL 2 VIN=-8dBV f=4kHz VIN=-8dBV f=22kHz VIN=-8dBV f=100kHz Input PWM signal shown in Figure 26 24 400 to 20kHz LPF used SPK output system (both ends of SPK: measured with 8Ω) 3.3V 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 LA74310LP 27 VOSP1 2 VIN=-15dBV f=1kHz 3.3V 0 1 1 1 1 0 0 1 15 17 400 to 20kHz LPF used Vol.=MAX 28 THDSP 2 VIN=-15dBV f=1kHz 3.3V 0 1 1 1 1 0 0 15 17 400 to 20kHz LPF used Vol.=MAX, THD: from 2nd to 5th harmonic 1 0 0 1 1 1 1 1 29 VOSP2 2 VIN=-15dBV f=1kHz 3.3V 0 1 1 1 1 0 15 17 400 to 20kHz LPF used Vol.=TYP 1 1 0 0 1 0 0 0 1 30 VOSP3 2 VIN=-15dBV f=1kHz 3.3V 0 1 1 1 1 0 15 17 JIS-A FILTER used Vol.=MIN 0 1 1 0 0 0 0 0 0 0 31 VNOSP 2 No input 15 17 3.3V 0 1 1 1 1 JIS-A FILTER used Vol.=MAX 0 1 1 0 0 1 1 1 1 1 32 VOSSP 2 f=1kHz 15 17 400 to 20kHz LPF used Level at which Vol=MAX and THD=10% (from 2nd to 5th harmonic) 0 0 1 1 0 0 1 1 1 1 1 MIC output system 3.3V 0 0 0 0 0 1 1 1 1 1 1 1 1 3.3V 3.3V 3.3V 3.3V 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 VGMIC 10 VIN=-39dBV f=1kHz 8 400 to 20kHz LPF used 34 HDMIC 10 VIN=-39dBV f=1kHz 8 400 to 20kHz LPF used THD: from 2nd to 5th harmonic 35 VNOMIC 10 No input 8 JIS-A FILTER used 36 VINMMX 10 f=1kHz 8 & 10 400 to 20kHz LPF used Pin 10 level at which pin 8 becomes THD = 3% (from 2nd to 5th harmonic) No.A0904-8/22 37 VMIC 10 No input 11 PIN 18:Measurement of output voltage (under 6.2kΩ load) Supplements: (Note 26) The line out signal level shall be VIDVOL when inputting the PWM waveform in Figure 26 into the pin 2. LA74310LP 100% 15% 1kHz sine wave 4 3 Voltage [V] 2 1 0 -1 0.E+00 2.E-04 4.E-04 PWM waveform input into the pin 2 3.3V 0V 6.E-04 8.E-04 1.E-03 1.E-03 1.E-03 2.E-03 2.E-03 2.E-03 Time [s] Figure 26. PWM waveform input into the pin 2 when measuring VIDVOL No.A0904-9/22 LA74310LP Description of Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VCC (Power source for VIDEO) PB input A GND NC REC output ALC detection ALC input MIC output MIC GND MIC input INT power supply for MIC Ripple rejection for VREFL NC SPK GND Speaker positive-phase output VCCSP Speaker negative-phase output SPK GND NC Speaker input MIX output BEEP input STANDBY control LINE output C.S. input CLOCK input DATA input NC VCCA Analog GND NC Gain select pin Video input Power save mode select pin GND NC CLOCK output Charge transfer Negative VCC Video output For VIDEO For VIDEO For VIDEO For VIDEO For VIDEO For VIDEO For VIDEO For VIDEO For VIDEO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO For AUDIO Pin Description Pin purpose For VIDEO For AUDIO For AUDIO No.A0904-10/22 LA74310LP LA74310LP Internal Equivalent Diagram and Recommended Circuit Diagram To MCOM VDD LINE STANDBY LOW OUT BEEPIN 0.01μF 24 23 22 21 0.047μF VCCA 1μF NC 30 29 28 DATA CLOCK CS 0.1μF 27 26 25 LOGIC NC 31 MUTE TO VCC From DAC STANDBY HIGH GAIN CTL 1μ F 33 34 35 NC 36 LPF1 CLOCKOUT 2.2μF ND VCCN 2.2μF 40 75Ω 38 39 DET ALC 37 Minus Voltage Generator LPF2 +16dB LPF 32 EVR -+ 18 17 16 15 14 13 NC 12 4.7μF 11 2.2kΩ MIX ratio + 1:1 20 19 NC SPK 8Ω VCCSP 1μ F See Table 2 See Table 1 CBA CHARGE VREF Input Zo=50kΩ + 70kΩ Video OUT MIC VCC 8 9 10 0.01μF MIC IN 1 VCC 4.7μF 2 3 4 NC 5 6 7 0.47μF 1BiT DA IN REC OUT 0.01μF ILA07164 NC PIN handling This pin is electrically open and can be connected to GND with no problem. However, we recommend you to make a foot pattern of a form similar to other pins to assure good balance after mounting. Table 1: Logic of external capacitor charging circuit SERIAL ON OFF No.2 0 1 Initially “ON” Table 2: LPF SW control logic SERIAL A B C No.5 1 0 0 No.6 * 0 1 *) Don’t care. No.A0904-11/22 LA74310LP LA74310LP EVR characteristics 10 0 -10 -20 EVR attenuation (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 30 Serial data set value (decimal numbers) Table of Input/Output Forms of LA74310LP (Audio Block) Pin No. 2 Pin Name PB IN DC voltage 1.64V AC voltage Reference input level =-15dBV Maximum input level = -5dBV In analog input mode = 3.465Vpp In ΔΣ input mode Description of functions PB input pin Equivalent circuit diagram in pin VCCA(=3.0V) ΔΣSignal input MODE 2 7.5kΩ 17.5kΩ 25kΩ VREFL Analog Signal Input MODE 3 4 5 A GND NC REC OUT 0V GND pin for analog signal part NC pin 1.50V At PB reference input Output level = -15dBV REC output pin VCCA(=3.0V) 5 500Ω 20kΩ 3k Ω VREF Continued on next page. No.A0904-12/22 LA74310LP Continued from preceding page. Pin No. 6 Pin Name ALC DET DC voltage AC voltage Description of functions ALC detection pin Equivalent circuit diagram in pin VCCA(=3.0V) 1k Ω 6 500Ω 7 ALC IN 1.64V At MIC reference input Output level = -49dBV ALC input pin VCCA(=3.0V) Max input level =-10dBV 7 500Ω 50kΩ VREF 8 MIC OUT 1.6V At MIC reference input Output level = -49dBV MIC output pin VCCA(=3.0V) 8 500Ω 9.7kΩ 1kΩ VREF 9 10 MIC GND MIC IN 0V 1.64V Reference input level =-69dBV Maximum input level =-30dBV For MIC Amp blocking GND pin MIC input pin VCCA(=3.0V) 500Ω 10 70kΩ VREFL 11 MIC VCC 2.30V MIC power pin VCCA(=3.0V) 11 2.2kΩ 23kΩ Continued on next page. No.A0904-13/22 LA74310LP Continued from preceding page. Pin No. 12 Pin Name VREFL DC voltage 2.30V AC voltage Description of functions MIC VCC and VREFL ripple rejection pin Equivalent circuit diagram in pin VCCA(=3.0V) 400Ω 12 500Ω 200kΩ 13 14 15 NC SP GND SPK OUT+ 0V 1.27V At PB reference input Output level = -8dBV (EVR MAX) NC pin Speaker GND pin Speaker positive-phase output pin VCCSP(=3.3V) 15 10kΩ 10.7kΩ 17 16 17 VCCSP SP OUT- 3.3V 1.27V At PB reference input Output level = -8dBV (EVR MAX) Speaker power pin Pin for output of speaker reversed phase VCCSP(=3.3V) 10kΩ 11kΩ 20 20 SPK IN 1.27V At PB reference input Output level = -8dBV (EVR MAX) Speaker input pin 17 18 19 21 SP GND NC MIX OUT 0V Speaker GND pin NC pin 1.58V At PB reference input Output level = -8dBV EVR output pin VCCA(=3.0V) 400Ω 21 35kΩ 3.9kΩ VREFL 22 BEEP IN 1.64V Maximum input level = -8dBV VCCA(=3.0V) 2kΩ 22 2k Ω VREFL Continued on next page. No.A0904-14/22 LA74310LP Continued from preceding page. Pin No. 23 Pin Name STANDBY L DC voltage AC voltage Description of functions STANDBY control pin 2V or more: STANDBY canceled Equivalent circuit diagram in pin 45kΩ 23 40kΩ 24 LINE OUT 1.52V At PB reference input Output level = -11dBV LINE output pin VCCA(=3.0V) 232kΩ 24 500Ω 26kΩ 10.5kΩ VREFL 25 CS CS input pin 26 CLOCK CLOCK input pin 25 26 500Ω 27 DATA DATA input pin 27 28 29 NC VCCA 3.0V NC pin Power pin for analog signal part Table of Input/Output Forms of LA74310LP (Video Block) Pin No. 1 Pin Name VCC DC voltage 2.7V to 3.6V 30 31 32 A-GND NC GAIN CTL 1.2V 0V Analog GND NC pin Gain select pin 1 VCC Description of functions Equivalent circuit diagram in pin Control of Pin2 H (VCC) M (OPEN) L (GND) ⇒ ⇒ ⇒ GAIN 16dB 12dB 6dB 2kΩ 32 0.72V REF 1.2V BUF 2.16V 100kΩ 35 GND Continued on next page. No.A0904-15/22 LA74310LP Continued from preceding page. Pin No. 33 Pin Name VIN DC voltage 1.1V Description of functions Video input terminal (Sync-tip clamp (input High-impedance)) GAIN SET: 6dB 1.0Vpp GAIN SET: 12dB 500mVpp GAIN SET: 16dB 317mVpp 1 VCC Equivalent circuit diagram in pin 2kΩ 2kΩ 200Ω 33 VIN 200Ω 2kΩ Active:On Standby:Off 26kΩ 35 GND 1.05V 34 PSAVCTL VCC or 0V Power save mode select pin 1 VCC 50kΩ Control of Pin4 OPEN H (VCC) L (GND) or VCC±0.5V 0V to 0.3V ⇒ ⇒ MODE 50kΩ 50kΩ STANDBY PSAVCTL 4kΩ ACTIVE 34 35 GND 35 36 37 GND NC CLKOUT 0V NC pin +3.0V ↑↓ 0V Pin37: Clock output terminal VCC=3.1V 3V 2V 37pin 1V 0V GND 37 CLKOUT 50kΩ 50kΩ 2.4V 1 VCC 50kΩ 35 VCC 38 ND +0.5V ↑↓ -2.6V (-VCC) -1V 38pin 39pin -2V -3V 1 35 GND Pin38: The terminal which transmits an electric charge 100kΩ 39 VCCN 0V ↑↓ -2.5V (-VCC) Pin39: Negative VCC VCCIN 39 50kΩ 38 GND 40 VOUT 0V Video output terminal (Push-pull output Low-impedance) 1.4V 1 VCC 50kΩ ACTIVE:Low-impedance STANDBY:High-impedance 500Ω 2Vpp 0V -0.6V 40 VOUT 35 GND + - 100kΩ 50kΩ 39 VCCIN No.A0904-16/22 LA74310LP POP Sound Avoiding Sequence 1Upon STANDBY cancellation & control (PBMODE) Power Supply (VCCA & VCCSP) STANDBY pin (23PIN) CS CLOCK =Don’t care =CLOCK DATA sending timing Optional After 10ms After 20ms After 50ms T0 T1 T2 T3 T4 After 200ms Before 10ms After 150ms (When pin 24 capacitance is 0.1μF) T5 T6 T7 T8 Recommended serial control settings 0 1 LPF Timing Communication content DMY * C SW 2 3 4 ALC 5 6 7 8 LINE 9 LINE 10 11 12 13 14 15 CHRG MIC LPF MODESW REC SPK EVR1 EVR2 EVR4 EVR8 EVR16 P SW P SW P SW (1, *): REC (0, 0): PB Analog (0, 1): PB Digital P SW P SW MUTE P SW DATA DATA DATA DATA DATA 0:ON 0:ON 0:ON 0:ON 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:11kHz 0:ON 0:ON 0:ON * T1 T2 (only CS) T3 T4 T5 T6 T7 VREF charging circuit: OFF Speaker AMP: ON Line AMP: ON Return to the initial state Standby control 0 0 0 0 Standby cancellation Dummy communication 1:4kHz 1:OFF 1:OFF 1:OFF 1:OFF 1:OFF 1:OFF 1:OFF 1:ON 1:ON 1:ON 1:ON 1:ON DATA unnecessary 0/1 0/1 0/1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0/1 0/1 0/1 0 1 1 1 0 1 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA unnecessary No.A0904-17/22 LA74310LP 2Upon STANDBY cancellation & control (RECMODE) Power Supply (VCCA & VCCSP) STANDBY pin (23PIN) CS CLOCK =Don’t care =CLOCK DATA sending timing T0 T1 T2 Optional After 10ms After 20ms After 30ms T3 T4 T5 T6 T7 After 200ms Before 10ms Recommended serial control settings 0 1 LPF Timing Communication content DMY * C SW 2 3 4 ALC 5 6 7 8 LINE 9 LINE 10 11 12 13 14 15 CHRG MIC LPF MODESW REC SPK EVR1 EVR2 EVR4 EVR8 EVR16 P SW P SW P SW (1, *): REC (0, 0): PB Analog (0, 1): PB Digital P SW P SW MUTE P SW DATA DATA DATA DATA DATA 0:ON 0:ON 0:ON 0:ON 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:11kHz 0:ON 0:ON 0:ON * T1 T2 (only CS) T3 T4 T5 T6 Charging circuit & ALC: OFF, LPF: REC ALC: ON Return to the initial state Standby control 0 0 0 Standby cancellation Dummy communication 1:4kHz 1:OFF 1:OFF 1:OFF 1:OFF 1:OFF 1:OFF 1:OFF 1:ON 1:ON 1:ON 1:ON 1:ON DATA unnecessary 0/1 0/1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA unnecessary No.A0904-18/22 LA74310LP 3REC → PB (SPK) Switching CS 4PB (SPK) → REC Switching CLOCK =Don’t care =CLOCK Optional DATA sending timing T0 T1 T2 After 20ms or more (Capacitance between pins 20&21: 0.1μF) T3 T4 After 20ms or more (Capacitance between pins 20&21: 0.1μF) Recommended serial control settings 0 1 LPF Timing Communication content DMY * C SW 2 3 4 ALC 5 6 7 8 LINE 9 LINE 10 11 12 13 14 15 CHRG MIC LPF MODESW REC SPK EVR1 EVR2 EVR4 EVR8 EVR16 P SW P SW P SW (1, *): REC (0, 0): PB Analog (0, 1): PB Digital P SW P SW MUTE P SW DATA DATA DATA DATA DATA 0:ON 0:ON 0:ON 0:ON 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:11kHz 0:ON 0:ON 0:ON * T0 T1 T2 T3 T4 Speaker AMP: ON PBMODE: switching EVR: setting Speaker AMP: ON RECMODE: switching EVR: MUTE Speaker AMP: OFF Speaker AMP: ON 0 0 0 0 0 1:4kHz 1:OFF 1:OFF 1:OFF 0/1 0/1 0/1 0/1 0/1 1 1 1 1 1 0 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1:OFF 1:OFF 1:OFF 1:OFF 1:ON 1:ON 1:ON 1:ON 1:ON 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 a a 0 0 0 a a 0 0 0 a a 0 0 0 a a 0 0 0 a a 0 0 0/1 0/1 0/1 0/1 0/1 5REC → PB (LINE) Switching CS 6PB(LINE) → REC Switching CLOCK =Don’t care =CLOCK DATA sending timing After 5ms or more T0 T1 T2 Recommended serial control settings 0 1 LPF Timing Communication content DMY * C SW 2 3 4 ALC 5 6 7 8 LINE 9 LINE 10 11 12 13 14 15 CHRG MIC LPF MODESW REC SPK EVR1 EVR2 EVR4 EVR8 EVR16 P SW P SW P SW (1, *): REC (0, 0): PB Analog (0, 1): PB Digital P SW P SW MUTE P SW DATA DATA DATA DATA DATA 0:ON 0:ON 0:ON 0:ON 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:11kHz 0:ON 0:ON 0:ON * T0 T1 T2 PBMODE: switching Line AMP: ON Line MUTE: OFF RECMODE: switching Line AMP: ON Line MUTE: OFF 0 0 0 1:4kHz 1:OFF 1:OFF 1:OFF 0/1 0/1 0/1 1 1 1 1 1 0 1 1 0 0 0 1 1:OFF 1:OFF 1:OFF 1:OFF 1:ON 1:ON 1:ON 1:ON 1:ON 1 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0/1 0/1 No.A0904-19/22 LA74310LP 7EVR Switching (min → max) 0.25ms/CS CS DATA sending timing T0 T1 T2 T3 T4 T5 T6 T19 T20 T21 T22 T23 T24 T25 Recommended serial control settings 0 1 LPF Timing Communication content DMY * C SW 2 3 4 ALC 5 6 7 8 LINE 9 LINE 10 11 12 13 14 15 CHRG MIC LPF MODESW REC SPK EVR1 EVR2 EVR4 EVR8 EVR16 P SW P SW P SW (1, *): REC (0, 0): PB Analog (0, 1): PB Digital P SW P SW MUTE P SW DATA DATA DATA DATA DATA 0:ON 0:ON 0:ON 0:ON 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:11kHz 0:ON 0:ON 0:ON * T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 EVRDATA=0 EVRDATA=7 EVRDATA=8 EVRDATA=9 EVRDATA=10 EVRDATA=11 EVRDATA=12 EVRDATA=13 EVRDATA=14 EVRDATA=15 EVRDATA=16 EVRDATA=17 EVRDATA=18 EVRDATA=19 EVRDATA=20 EVRDATA=21 EVRDATA=22 EVRDATA=23 EVRDATA=24 EVRDATA=25 EVRDATA=26 EVRDATA=27 EVRDATA=28 EVRDATA=29 EVRDATA=30 EVRDATA=31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1:4kHz 1:OFF 1:OFF 1:OFF 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1:OFF 1:OFF 1:OFF 1:OFF 1:ON 1:ON 1:ON 1:ON 1:ON 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Note) DATA1 to 6 are the mute area of EVR characteristics and jumped due to no generation of POP noise. No.A0904-20/22 LA74310LP 8EVR Switching (max → min) 0.25ms/CS CS DATA sending timing T0 T1 T2 T3 T4 T5 T6 T19 T20 T21 T22 T23 T24 T25 Recommended serial control settings 0 1 LPF Timing Communication content DMY * C SW 2 3 4 ALC 5 6 7 8 LINE 9 LINE 10 11 12 13 14 15 CHRG MIC LPF MODESW REC SPK EVR1 EVR2 EVR4 EVR8 EVR16 P SW P SW P SW (1, *): REC (0, 0): PB Analog (0, 1): PB Digital P SW P SW MUTE P SW DATA DATA DATA DATA DATA 0:ON 0:ON 0:ON 0:ON 0:OFF 0:OFF 0:OFF 0:OFF 0:OFF 0:11kHz 0:ON 0:ON 0:ON * T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 EVRDATA=31 EVRDATA=30 EVRDATA=29 EVRDATA=28 EVRDATA=27 EVRDATA=26 EVRDATA=25 EVRDATA=24 EVRDATA=23 EVRDATA=22 EVRDATA=21 EVRDATA=20 EVRDATA=19 EVRDATA=18 EVRDATA=17 EVRDATA=16 EVRDATA=15 EVRDATA=14 EVRDATA=13 EVRDATA=12 EVRDATA=11 EVRDATA=10 EVRDATA=9 EVRDATA=8 EVRDATA=7 EVRDATA=0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1:4kHz 1:OFF 1:OFF 1:OFF 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1:OFF 1:OFF 1:OFF 1:OFF 1:ON 1:ON 1:ON 1:ON 1:ON 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Note) DATA1 to 6 are the mute area of EVR characteristics and jumped due to no generation of POP noise. No.A0904-21/22 LA74310LP SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of September, 2007. Specifications and information herein are subject to change without notice. PS No.A0904-22/22