LA75501V

Ordering number : ENA0224 Monolithic Linear IC LA75501V Overview For Use in TV/VTR Applications VIF/SIF Signal Processing IC The LA75501V is an adjustment free VIF/SIF signal processing IC for PAL TV/VCR. It supports 38MHz, 38.9MHz, and 39.5MHz as the IF frequencies, as well as PAL sound multi-system (M/N,B/G, I, D/K), and contains an on-chip sound carrier trap and sound carrier BPF. To adjust the VCO circuit, AFT circuit, and sound filter, 4MHz external crystal or 4MHz external signal is needed. Function • VIF Block: VIF Amplifier, PLL Detector, IF AGC, RF AGC, Equalizer, amplifier, Buzz Canceller, SIF Trap, Digital AFT, FLL, 4MHz X’tal oscillation • 1st SIF Block: 1st SIF Amplifier, 1st SIF Detector, 1st SIF AGC • SIF Block: Limiter Amplifier Down Converter, PLL FM Detector SIF PLL SIF VCO, SIF BPF • Others: IF SW (38.9MHz, 38MHz), SIF4 System SW (B/G, I, D/K, M/N), IFAGC 2nd filter Specifications Maximum Ratings at Ta = 25°C Parameter Maximum Supply voltage Circuit voltage Symbol VCC V16 V18 Circuit Current I30 I17 I6 I4 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg Ta≤80°C * Conditions Ratings 7 VCC VCC -1 +0.5 -10 -3 500 -20 to +85 -55 to +150 Unit V V V mA mA mA mA mW °C °C * Mounted on a board : 65×72×1.6mm3,paper phenol board. Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 92706 / 22706 MS OT B8-4910 No.A0224-1/10 LA75501V Operating Ranges at Ta = 25°C Parameter Recommended supply voltage Operating supply voltage Symbol VCC VCC op Conditions Ratings 5.0 4.5 to 6.0 Unit V V Electrical Characteristics at Ta = 25°C, VCC = 5V, fp = 38.9MHz VIF Block Parameter Circuit current Maximum RF AGC voltage Minimum RF AGC voltage Input sensitivity AGC range Maximum allowable input No-signal video output voltage Sync. Signal tip voltage Video output amplitude Video S/N C-S best Differential gain Differential phase Black noise threshold voltage Black noise clamp voltage VIF input resistance VIF input capacitance Maximum AFT voltage Minimum AFT voltage AFT tolerance 1 AFT tolerance 2 ATF detection sensitivity AFT Dead Zone APC pull-in range (U) APC pull-in range (L) VCO maximum variable range (U) VCO maximum variable range (L) VCO control sensitivity N Trap 1 (4.5M) N Trap 2 (4.8M) B/G Trap 1 (5.5M) B/G Trap 2 (5.85M) I Trap 1 (6.0M) I Trap 2 (6.55M) D/K Trap1 (6.5M) Group delay 1 NTSC (3.0M) Group delay 1-1 NTSC (3.5M) Group delay 2 B/G (4M) Group delay 2-1 B/G (4.4M) Group delay 3 I (4M) Group delay 3-1 I (4.4M) Group delay 4 D/K (4M) Group delay 4-1 D/K (4.4M) β NT1 NT1-1 BT1 BT1-1 IT1 IT1-1 DT1 ngd1 ngd1-1 bgd2 bgd2-1 bgd3 bgd3-1 bgd4 bgd4-1 2.0 -30 -19 -27 -20 -25 -15 -25 30 160 70 160 20 60 0 10 4.0 -35 -24 -32 -25 -30 -20 -30 60 230 100 230 50 90 30 40 90 300 130 300 80 120 60 70 8.0 kHz/mV dB dB dB dB dB dB dB ns ns ns ns ns ns ns ns dfl 1.5 2.0 MHz Symbol I21 V17H V17L vi GR Vi max V6 V6tip VO S/N IC-S DG DP VBTH VBCL Ri Ci V16H V16L dfa1 dfa2 sf fda fpu fpl dfu 1.5 1.5 1.5 f = 38.9MHz f = 38.0MHz RL = 100k//100KΩ 30 4.3 0 B/G PS = 10dB 80dBµ, 87.5% MOD 80dBµ, 87.5% MOD Collector load 30k VC2 = 9V 8.5 0.0 33 58 92 2.9 0.9 1.5 48 26 97 3.3 1.2 1.8 52 32 5 2 0.7 1.8 2.5 3 4.7 0.2 ±35 ±35 55 30 2.0 2.0 2.0 3.0 6 5.0 0.7 ±70 ±70 80 60 38 10 10 3.7 1.5 2.1 Conditions min Ratings typ 64.0 9 0.3 39 0.7 45 max 73.6 mA V V dBµV dB dBµV V V Vp-p dB dB % °C V V kΩ PF V V KHz KHz mV/kHz MHz MHz MHz MHz Unit No.A0224-2/10 LA75501V 1st SIF Block Parameter Conversion gain SIF carrier output level 1st SIF maximum input 1st SIF input resistance 1st SIF input capacitance Symbol VG So Si max R is C is Conditions min fp-5.5MHz,Vi = 500µV Vi = 10mV So±2dB 26 Ratings typ 32 100 106 2.0 3 2.4 6 max 36 dB mVrms dBµV KΩ PF Unit SIF Block Parameter Limiting sensitivity FM detector output voltage AM rejection ratio Distortion FM detector output S/N BPF 3dB band width PAL de-emphasis NTSC de-emphasis PAL/NT Audio voltage gain difference Symbol Vi (lim) VO (FM) AMR THD S/N (FM) BW Pdeem Ndeem GD fm = 3kHz fm = 2kHz f = 5.5MHz ∆F = ±30kHz at 400Hz AM = 30% at 400Hz f = 5.5MHz ∆F = ±30kHz DIN. Audio 55 Conditions min 46 480 50 Ratings typ 52 600 60 0.3 60 ±100 -3 -3 6 1.0 max 58 750 dBµV mVrms dB % dB kHz dB dB dB Unit Others Parameter Minimum 4MHz level (at external input) SIF system SW threshold voltage V13 V14 IF system SW threshold voltage Split/Inter SW V15 V20 0.5 270 KΩ V 1.4 V Symbol X4MIN Conditions min Terminal value 80 Ratings typ 86 max 92 dBµ Unit System Changeover SW/SIF system SW The SIF system can be changed over by setting A (pin 13) and B (pin 14) to GND and the open state respectively. A GND GND OPEN OPEN B GND OPEN GND OPEN O O O B/G I D/K M/N O FM DET LEVEL 6dB 0dB 0dB 0dB De-emphasis 75µs 50µs 50µs 50µs Note: ‘O’ indicates that the system is selected. IF system SW The IF frequency is selected 38.9MHz mode with the pin 15 (crystal oscillation) open. The IF frequency is selected 38MHz mode by adding 220KΩ between the pin 15 and GND. Inter carrier SW Inter-carrier is selected by setting the 1st SIF input (pin 20) to GND. No.A0224-3/10 LA75501V Package Dimensions unit : mm 3191B 9.75 30 16 5.6 7.6 1 0.65 (0.33) 0.22 15 0.15 1.5max SANYO : SSOP30(275mil) Pin Assignment 0.1 (1.3) 0.5 No.A0224-4/10 LA75501V Block Diagram and AC Characteristics Test Circuit Input Impedance Test Circuit LA75510V No.A0224-5/10 LA75501V Test Conditions V1. Circuit current [I21] (1) External AGC (V18 = 1.5V) (2) RF AGC VR MAX (3) Connect an ammeter to the VCC and measure the incoming current to pin 17. V2. V3. Maximum RF AGC voltage, Minimum RF AGC voltage [V17H, V17L] (1) Internal AGC (2) Input a 38.9MHz, 10mVrms, continuous wave to the VIF input pin. (3) Adjust the RF AGC VR (resistance max.) and measure the maximum RF AGC voltage. (4) Adjust the RF AGC VR (resistance min.) and measure the minimum RF AGC voltage. (3), (4) Measuring point F V4. Input sensitivity [Vi] (1) Internal AGC (2) fp = 38.9MHz 400Hz 40% AM (VIF input) (3) Turn off the SW1 and put 100kΩ through. (4) Measure the VIF input level at which the 400Hz detection output level at test point A becomes 0.7Vp-p. V5. AGC range [GR] (1) Apply the VCC voltage to the external AGC, If AGC (pin 18). (2) In the same manner under the same conditions as for V4 (input sensitivity), measure the VIF input level at which the detection output level becomes 0.7Vp-p. ····· Vil *Vi: Input sensitivity (3) GR = 20log Vil dB Vi V6. Maximum allowable input [Vi max] (1) Internal AGC (2) fp = 38.9MHz 15kHz 78% AM (VIF input) (3) VIF input level at which the detection output level at test point A becomes video output (VO) ±1dB. V7. No-signal video output voltage [V6] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 18). (2) Measure the DC voltage of VIDEO output (A). V8. Sync. signal tip voltage [V6tip] (1) Internal AGC (2) Input a 38.9MHz, 10mVrms, continuous wave to the VIF input pin. (3) Measure the DC voltage of VIDEO output (A). V9. Video output level [VO] (1) Internal AGC (2) fp = 38.9MHz 15kHz 78% AM Vi = 10mVrms (VIF input) (3) Measure the peak value of the detection output level at test point A. (Vp-p) V10. Video S/N [S/N] (1) Internal AGC (2) fp = 38.9MHz CW = 10mVrms (VIF input) (3) Measure the noise voltage at test point A in RMS volts through a 10kHz to 4MHz band-pass filter. ····· Noise voltage (N) (4) S/N = 20log Video voltage (Vp-p) = 20log 1.12Vp-p N (Vrms) N(Vrms) (dB) No.A0224-6/10 LA75501V V11. C/S beat [Ics] (1) Apply DC voltage to the external AGC IF AGC (pin 18) and vary it. (2) fp = 38.9MHz CW;10mVrms fc = 34.47MHz CW;10mVrms − 10dB fs = 33.4MHz CW;10mVrms − 10dB (3) Adjust the IF AGC (pin 18) voltage so that the output level at test point A becomes 1.3Vp-p. (4) Measure the difference between the levels for 4.43MHz and 1.07MHz components at test point A. V12.V13. Differential gain, differential phase [DG, DP] (1) Internal AGC (2) fp = 38.9MHz APL50% 87.5% Modulation video signal Vi = 10mVrms (3) Measure the DG and DP at test point A. V14.V15. Black noise threshold and clamp voltage [VBTH, VBCL] (1) Apply DC voltage (1 to 3V) to the external AGC, IF AGC (pin 18) and adjust the voltage. (2) fp = 38.9MHz 400Hz 40% AM 10mVrms (VIF input) (3) Adjust the IF AGC (pin 18) voltage to operate the noise canceller. Measure the VBTH, VBCL at test point A. V16. V17. VIF input resistance, input capacitance [Ri, Ci] (1) External AGC (V18 = 2V) (2) Referring to the Input Impedance Test Circuit, measure Ri and Ci with an impedance analyzer. No.A0224-7/10 LA75501V V18. V19. Maximum, minimum AFT voltage, AFT detection sensitivity [V16H, V16L] (1) Internal AGC (2) fp = 38.9MHz ±1.5MHz Vi = 10mVrms (VIF input) (3) Measure maximum and minimum AFT output voltage (at the measuring point B) by changing the input frequency. (4) Maximum voltage: V16H, minimum voltage: V16L. V20.V21.V22.V23. AFT tolerance 1,2,AFT detector sensitivity, AFT Dead Zone [dfa, Sf, fda] (1) Measure the frequency deviation when the voltage at the measuring point B changes from V1 to V2. ·····∆f Sf (mV/kHz) = V1−V2 ∆f (2) Measure the width in which the voltage at the measuring point B does not change. (3) Calculate as follows: fda (kHz) = f2 − f1 (4) Calculate as follows: IF Center frequency: 38.9MHz, 38MHz dfa (kHz) = fc− f1 + f2 2 V24.V25. APC pull-in range [fpu, fpl] (1) Internal AGC (2) FLL: Free (3) fp = 33MHz to 44MHz CW;10mVrms (4) Adjust the SG signal frequency to be higher than fp = 38.9MHz to bring the PLL to unlocked state. Note; The PLL is taken as in unlocked state when a beat signal appears at test point A. (5) When the SG signal frequency is lowered, the PLL is brought to locked state again. ····· f1 (6) Lower the SG signal frequency to bring the PLL to unlock state. (7) When the SG signal frequency is raised, the PLL is brought to locked state again. ····· f2 (8) Calculate as follows: fpu = f1 − 38.9MHz fpl = f2 − 38.9MHz V26.V27. VCO maximum variable range (U, L) [dfu, dfl] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 18). (2) fl is taken as the frequency when 1V is applied to the APC pin (pin 9). In the same manner, fu is taken as the frequency when 5V is applied to the APC pin (pin 9). dpu = fu − 38.9MHz dfl = fl − 38.9MHz No.A0224-8/10 LA75501V V28. VCO control sensitivity [β] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 18). (2) Apply the 3V to the external FLL, FLL (pin 10). (3) Pick up the VCO oscillation frequency from the VIDEO output (A), GND, etc. And adjust the VCO coil so that the frequency becomes 38.9MHz. (4) f1 is taken as the frequency when 2.8V is applied to the APC pin (pin 9). In the same manner, f2 is taken as the frequency when 3.2V is applied to the APC pin (pin 9). β = f2− f1 − f2 400 (kHz/mV) F1. 1st SIF conversion gain [VG] (1) Internal AGC (2) fp = 38.9MHz CW;10mV (VIF input) fs = 33.4MHz CW;500µV (1st SIF input) ····· V1 (3) measure the detection output level at test point C (5.5MHz) ····· V2 (4) VG = 20log V2 dB V1 F2. 5.5MHz output level [So] (1) Internal AGC (2) fp = 38.9MHz CW; 10mV (VIF input) fs = 33.4MHz CW; 10mV (1st SIF input) ····· V1 (3) Measure the detection output level at test point C (5.5MHz). ····· So (mVrms) F3. 1st maximum input [Si max] (1) Internal AGC (2) fp = 38.9MHz CW; 10mV (VIF input) fs = 33.4MHz CW; Variable (1st SIF input) (3) Input level at which the detection output (5.5MHz) at test point C becomes So ±2dB. ····· Si max F4.F5. 1st SIF input resistance, input capacitance [Ri (SIF1), Ci (SIF1)] (1) Referring to the Input Impedance Test Circuit, measure Ri and Ci with an impedance analyzer. S1. SIF Limiting sensitivity [Vi (lim)] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 18). (2) fs = 5.5MHz fm = 400Hz ∆F = ±300kHz (SIF input) (3) Set the SIF input level to 31.6mVrms and measure the level at test point D. ····· V1 (4) Lower the SIF input level and measure the input level which becomes V1. ····· 3dB. S2.S4. FM detection output voltage, total harmonics distortion [VO(FM), THD] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 18). (2) fs = 5.5MHz fm = 400Hz ∆f = ±30kHz (SIF input Vi = 31.6mVrms) (3) Measure the FM detection output voltage, total harmonics distortion at test point D. S3. AM rejection ratio [AMR] (1) External AGC (V18 =VCC) (2) fs = 5.5MHz fm = 400Hz AM = 30% (SIF input Vi = 31.6mVrms) (3) Measure the output level at test point D. ····· VAM V (DET) (4) AMR = 20log O dB VAM S5. SIF S/N [S/N (FM)] (1) External AGC (V15 = VCC) (2) fs = 5.5MHz NO MOD Vi = 31.6mVrms (3) Measure the output level at test point D. ····· Vn (4) S/N = 20log VO (DET) dB Vn No.A0224-9/10 LA75501V S7.S8. PAL, NT de-emphasis [Pdeem, Ndeem] (1) External AGC (V18 = VCC) (2) fs = 5.5MHz fm = 3kHz ∆F = ±30kHz (SIF input Vi = 31.6mVrms) (3) Open system switches (A (pin 13) and B (pin 14)). (BG mode) (4) Measure the FM detector output voltage at test point D. ····· Vp (5) Calculate as follows: Pdeem (dB) = Vp − VO (FM) (6) fs = 4.5MHz fm = 2kHz ∆F = ±30kHz (SIF input Vi = 31.6mVrms) (7) Set system switches [A (pin 13) and B (pin 14)] to GND. (NT mode) (8) Measure the FM detector output voltage at test point D. ····· Vp (9) Calculate as follows: Ndeem (dB) = Vnt − VO (FM) S9. PAL/NT Audio voltage gain difference [GD] (1) External AGC (V18 =VCC) (2) fs = 4.5MHz fm = 400Hz ∆F = ±30kHz (SIF input Vi = 31.6mVrms) (3) Set system switches [A (pin 13) and B (pin 14)] to GND. (4) Measure the FM detector output voltage at test point D. ····· Vnt (5) Calculate as follows: GD (db) = Vnt − VO (FM) Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. 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Specifications and information herein are subject to change without notice. PS No.A0224-10/10