LA76850

Ordering number : ENA0017 LA76850 Overview Monolithic Linear IC Black & White Television IC LA76850 is a Black & White Television IC. Functions • I2C Bus Control VIF/SIF/Y/Deflection/Implemented in a Single Chip Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Symbol V8 max V27 max Maximum supply current I16 max I20 max Allowable power dissipation Operating temperature Storage temperature Pd max Topg Tstg Ta ≤ 65°C * Conditions Ratings 7.0 7.0 14 35 1.1 -10 to +65 -55 to +150 Unit V V V V mW °C °C * Provided with a glass epoxy board (114.3×76.1×1.6 mm) Operating Conditions at Ta = 25°C Parameter Recommended supply voltage Symbol V8 V27 Recommended supply current I16 I20 Operating supply voltage range V8 op V27 op Operating supply current range I16 op I20 op Conditions Ratings 5.0 5.0 9 29 4.7 to 5.3 4.7 to 5.3 7 to 11 24 to 33 Unit V V mA mA V V mA mA Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2206 / N1105 MS OT B8-7024 No.A0017-1/31 LA76850 Electrical Characteristics Ta = 25°C, VCCL = V8 = V27 = 5.0V, ICC = I16 = 9mA, ICC = I20 = 27mA Parameter [Circuit voltage, current] IF supply current RGB supply voltage Horizontal supply voltage Video supply current [VIF block] Maximum RFAGC voltage Minimum RFAGC voltage RF AGC Delay Pt (@DAC = 0) RF AGC Delay Pt (@DAC = 63) Input sensitivity No-signal video output voltage Sync signal tip level Video output amplitude Video S/N C-S beat level Differential gain Differential phase Maximum AFT output voltage Minimum AFT output voltage AFT detection sensitivity APC pull-in range (U) APC pull-in range (L) NT Trap1 (4.5MHz) NT Trap1 (4.8MHz) BG Trap1 (5.5MHz) BG Trap2 (5.85MHz) I Trap1 (6.0MHz) I Trap1(6.55MHz) DK Trap1(6.5MHz) [SIF block] FM detection output voltage FM limiting sensitivity FM detection output f characteristics FM detection output distortion AM rejection ratio SIF S/N PAL de-emph time constant PAL/NT Difference of voltage gain NT de-emph time constant SNTC 1.9 2.5 3.1 dB STHD SAMR SSN SPTC SGD FM = ±30kHz AM = 30% DIN.Andio 40 51.5 2.4 -1.5 3.0 0.0 3.6 +1.5 1.0 % dB dB dB dB SOADJ SLS SF FM = ±30kHz Output -3dB fm = 100kHz -0.5 5.0 245 310 390 53 8.0 mVrms dBµ dB Vi VOn VOtip VO S/N IC-S DG DP VAFTH VAFTL VAFTS fPU fPL NTR1 NTR2 BTR1 BTR2 ITR1 ITR2 DTR1 Output-3dB No signal CW = 80dBµ 80dBµ, AM = 78%, fm = 15kHz CW = 80dBµ V4.43MHz/V1.07MHz 80dBµ, 87.5% Video MOD 80dBµ, 87.5% Video MOD CW = 80dBµ, frequency variations CW = 80dBµ, frequency variations CW = 80dBµ, frequency variations 4.3 0.0 8.0 1.5 1.5 -30 -20 -30 -20 -30 -17 -30 3.4 1.1 1.57 40 35 5.0 1.0 4.7 0.3 15.0 10.0 10.0 5 0.7 22.0 3.7 1.4 2.05 45 46 4.0 1.7 2.52 dBµ Vdc Vdc Vp-p dB dB % deg Vdc Vdc mV/kHz MHz MHz dB dB dB dB dB dB dB VRFH VRFL RFAGC0 RFAGC63 CW = 80dBµ, DAC = 0 CW = 80dBµ, DAC = 63 DAC = 0 DAC = 63 8.5 0 90 80 9 0.3 0.7 Vdc Vdc dBµ dBµ I8 V16 V20 I27 V8 = 5V, V3 = 2.5V I16 = 9mA I25 = 27mA I27 = 5V 67 8.0 5.0 65 mA V V mA Symbol Conditions min typ max unit Continued on next page. No.A0017-2/31 LA76850 Continued from preceding page. Parameter [AUDIO block] Maximum gain Variable range Frequency characteristics Mute Distortion S/N Crosstalk [Video block] Video signal input 1DC voltage Video signal input 1AC voltage Video overall gain (Contrast max) Contrast adjustment characteristics (Normal/max) Contrast adjustment characteristics (Min/max) Video frequency Characteristics 1 NTSC Video frequency characteristics 2 PAL Chroma trap amount PAL Chroma trap amount NTSC DC transmission amount Sharpness variability range (trap 2 mid) (trap 2 max) (trap 2 min) Sharp63T5 Sharp0T5 Y gamma effective point 1 Y gamma effective point 2 Y gamma effective point 3 Horizontal/vertical blanking output level [OSD block] OSD Fast SW threshold OSD output level [RGB output (cutoff drive) block] Brightness control (Normal) Brightness control (Normal-H) Hi brightness (max) Low brightness (min) Bright control Resolution Sub-bias control Resolution BRT63 BRT63H BRT127 BRT0 Vbiassns Vsbiassns 2.3 3.0 20 -30 2.8 3.3 25 -25 16 7 3.3 3.6 30 -20 V V IRE IRE mV /Bit mV /Bit Continued on next page. FSTH OSDH Digital osd = 1 Osd cont = 63 0.7 140 0.9 175 1.1 210 V IRE YG1 YG2 YG3 RGBBLK F = 3.0MHz, FILTER SYS = 0000 Y APF = 1 F = 3.0MHz, FILTER SYS = 0000 Y APF = 1 YGAMMA = 01 YGAMMA = 10 YGAMMA = 11 89.0 85.0 80.0 0.1 93.0 89.0 84.0 0.4 97.0 93.0 88.0 0.7 % % % V -6.5 -3.5 -0.5 dB CtrapP CtrapN ClampG1 Sharp32T2 Sharp63T2 Sharp0T2 F = 2.7MHz, FILTER SYS = 0010 F = 2.7MHz, FILTER SYS = 0010 F = 2.7MHz, FILTER SYS = 0010 BW2 BW1 1.8MHz/100kHz Filter sys = 0000 2.2MHz/100kHz Filter sys = 0010 -36.0 -36.0 95.0 5.0 8.5 -6.5 8.5 -26.0 -26.0 100.0 8.0 11.5 -3.5 11.5 -22.0 -22.0 105.0 11.0 13.5 -0.5 13.5 dB dB % dB dB dB dB -6.0 -3.0 0.0 dB -6.0 -3.0 0.0 dB CONT0 -18.0 -15.0 -12.0 dB CONT63 -6.5 -5.0 -3.5 dB VIN1DC VIN1AC CONT127 12.0 2.2 2.5 1 14.0 16.0 2.8 V Vp-p dB AGMAX ARANGE AF AMUTE ATHD ASN ACT 20kHz 20kHz 1kHz, 500mVrms, Vol: MAX DIN. Audio 1kHz 65 70 73 1kHz500mVrms -2.0 60 -3.0 70 0.5 0.5 74 0.0 3.0 +3.0 dB dB dB dB % dB dB Symbol Conditions min typ max unit No.A0017-3/31 LA76850 Continued from preceding page. Parameter [Deflection block] Horizontal free-running frequency Horizontal pull-in range Horizontal output pulse width Horizontal output pulse saturation voltage Vertical free-running cycle 50 Vertical free-running cycle 60 Horizontal output pulse phase Horizontal output pulse phase Horizontal position adjustment range Horizontal position adjustment maximum variability width Horizontal blanking left @0 Horizontal blanking left @7 Horizontal blanking right @0 Horizontal blanking right @7 Sand castle pulse crest value H Sand castle pulse crest value M1 Sand castle pulse crest value M2 Sand castle pulse crest value L Burst gate pulse width Burst gate pulse phase Horizontal output stop voltage Vertical ramp output amplitude PAL@64 Vertical ramp output amplitude NTSC@64 Vertical ramp output amplitude PAL@0 Vertical ramp output amplitude NTSC@0 Vertical ramp output amplitude PAL@127 Vertical ramp output amplitude NTSC@127 Continued on next page. Vspal127 VSIZE: 1111111 1.15 1.30 1.45 Vp-p Vspal127 VSIZE: 1111111 1.15 1.30 1.45 Vp-p vsnt0 VSIZE: 0000000 0.41 0.51 0.61 Vp-p Vspal0 VSIZE: 0000000 0.41 0.51 0.61 Vp-p Vsnt64 VSIZE: 1000000 0.85 0.95 1.05 Vp-p Vspal64 VSIZE: 1000000 0.85 0.95 1.05 Vp-p BLKL0 BLKL7 BLKR0 BLKR7 SANDH SANDM1 SANDM2 SANDL BGPWD BGPPH Hstop BLKL:000 BLKL:111 BLKR:000 BLKR:111 7500 10800 1800 -1100 5.3 3.7 1.7 0.1 2.5 4.9 3.30 8300 11600 2600 -300 5.6 4.0 2.0 0.4 3.0 5.4 3.60 9100 12400 3400 500 5.9 4.3 2.3 0.7 3.5 5.9 3.90 ns ns ns ns V V V V µs µs V HPHstep 350.0 ns VFR50 VFR60 HPHCENpal HPHCENnt HPHrange 5bit 312.0 262.0 9.5 9.5 312.5 262.5 10.5 10.5 ±2.4 313.0 263.0 11.5 11.5 H H µs µs µs fH PULL Hduty V Hsat ±400 36.1 0 37.6 0.2 39.1 0.4 Hz µs V FH 15500 15670 15900 Hz Symbol Conditions min typ max unit No.A0017-4/31 LA76850 Continued from preceding page. Parameter Symbol Conditions min typ max unit Vertical size correction @0 Vertical ramp DC voltage PAL@32 Vertical ramp DC voltage NTSC@32 Vertical ramp DC voltage PAL@0 Vertical ramp DC voltage NTSC@0 Vertical ramp DC voltage PAL@63 Vertical ramp DC voltage NTSC@63 Vertical linearity @16 Vertical linearity @0 Vertical linearity @31 Vertical S-shaped correction @16 Vertical S-shaped correction @0 Vertical S-shaped correction @31 Vlin16 Vlin0 Vlin31 Vscor16 Vscor0 Vscor31 VLIN: 10000 VLIN: 00000 VLIN: 11111 VSC: 10000 VSC: 00000 VSC: 11111 0.85 1.17 0.57 0.75 1.08 0.49 1.00 1.32 0.72 0.90 1.23 0.64 1.15 1.47 0.87 1.05 1.38 0.79 ratio ratio ratio ratio ratio ratio Vdcpal63 VDC:111111 2.65 2.80 2.95 Vdc Vdcpal63 VDC: 111111 2.65 2.80 2.95 Vdc Vdcpal0 VDC: 000000 1.85 2.00 2.15 Vdc Vdcpal0 VDC: 000000 1.85 2.00 2.15 Vdc Vdcnt32 VDC: 100000 2.25 2.40 2.55 Vdc Vdcpal32 VDC: 100000 2.25 2.40 2.55 Vdc Vsizecomp VCOMP: 000 0.89 0.93 0.97 ratio Package Dimensions unit : mm 3170A No.A0017-5/31 LA76850 Application Circuit Example No.A0017-6/31 LA76850 Test Conditions Ta = 25°C, VCC = V8 = V31 = V43 = 5.0V, l18 = 19mA, ICC = l25 = 27mA Parameter [Circuit voltage, current] RGB supply voltage (pin 20) V20 No signal Apply a current of 27mA to pin 20 and measure the voltage at pin 20. No signal Apply a current of 19mA to pin 16 and measure the voltage at pin 16. No signal Apply a voltage of 5.0V to pin 8 and measure the incoming DC current (mA). (IF AGC 2.5V applied) Video/vertical supply current (pin 27) I27 (DEFICC) No signal Apply a voltage of 5.0V to pin 27 and measure the incoming DC current (mA). Initial Initial Initial Initial Symbol Test point Input signal Test method Bus conditions 20 RGB supply voltage (pin 16) V16 16 IF supply current (pin 8) I8 (CDDICC) 8 27 NoA0017-7/31 LA76850 VIF Block Input Signals 1. Input signals must all be input to the PIF IN (pin 6) in the Test Circuit. 2. All input signal voltage values are the levels at the VIF IN (pin 6) in the Test Circuit. 3. Signal contents and signal levels 4. Bus conditions: VIF SYS = "01", S.TRAP.SW = "1", OVER.MOD.SW = "0" Input signal SG1 CW Waveform 38.9MHz Conditions SG2 CW 34.47MHz SG3 CW 33.4MHz SG4 CW Frequency variable SG5 38.9MHz 87.5% Video Mod. 10-stairstep wave (Subcarrier: 4.43MHz) SG6 38.9MHz fm = 15kHz, AM = 78% SG7 38.9MHz, 80dBµ 50IRE 87.5% Video Mod. 50IRE Luma (Carrier: variable) 50IRE Luma NoA0017-8/31 LA76850 VIF Block Test Conditions Input signal Maximum RF AGC voltage Minimum RF AGC voltage RF AGC Delay Pt (@DAC = 0) RF AGC Delay Pt (@DAC = 63) Input sensitivity Vi RFAGC63 RFAGC0 VRFL Symbol VRFH Test point Input signal SG1 80dBµ SG1 80dBµ SG1 SG1 SG6 Obtain the input level at which the DC voltage at pin 4 becomes 4.5V. Obtain the input level at which the DC voltage at pin 4 becomes 4.5V. Using an oscilloscope, observe the level at pin 29 and obtain the input level at which the waveform's p-p value becomes 1.4Vp-p. No-signal video output voltage Sync signal tip level Video output amplitude Video S/N S/N VO VOtip VOn No signal Set IF AGC = “1” and measure the DC voltage at pin 29. SG1 80dBµ SG6 80dBµ SG1 80dBµ SG1 SG2 SG3 Using an oscilloscope, observe the level at pin 29 and measure the waveform’s p-p value. Measure the noise voltage (Vsn) at pin 29 with an RMS voltmeter through a 10kHz to 5.0MHz band-pass filter and calculate 20 log (1.43/Vsn). C-S beat level IC-S Input a 80dBµ SG1 signal and measure the DC voltage (V3) at pin 3. Mix SG1 = 74dBµ, SG2 = 64 dBµ, and SG3 = 64 dBµ to enter the mixture in the VIF IN. Apply V3 to pin 3 from an external DC power supply. Using a spectrum analyzer, measure the difference between pin 29’s 4.43MHz component and 1.07MHz component. Differential gain Differential phase Maximum AFT output voltage Minimum AFT output voltage AFT detection sensitivity VAFTS VAFTL DG DP VAFTH SG5 80dBµ SG5 80dBµ SG4 80dBµ SG4 80dBµz SG4 80dBµz Set and input the SG4 frequency to 37.9MHz to be input. Measure the DC voltage at pin 10 at that moment. Set and input the SG4 frequency to 39.9MHz to be input. Measure the DC voltage at pin 10 at that moment. Adjust the SG4 frequency and measure frequency deviation ∆f when the DC voltage at pin 10 changes from 1.5V to 3.5V. VAFTS = 2000/∆f [mV/kHz] Continued on next page. Using a vector scope, measure the level at Pin 29. Using a vector scope, measure the level at Pin 29. Measure the DC voltage at pin 29. RF.AGC = "111111" RF.AGC = "000000" Measure the DC voltage at pin 4. RF.AGC = "111111" Test method Measure the DC voltage at pin 4. Bus conditions RF.AGC = "000000" 4 4 4 4 29 29 29 29 29 29 29 29 10 10 10 NoA0017-9/31 LA76850 Continued from preceding page. Input signal APC pull-in range (U), (L) Symbol fPU, fPL Test point Input signal SG4 80dBµ Test method Connect an oscilloscope to pin 29 and adjust the SG4 frequency to a frequency higher than 38.9MHz to bring the PLL into unlocked mode. (A beat signal appears.) Lower the SG4 frequency and measure the frequency at which the PLL locks again. In the same manner, adjust the SG4 frequency to a lower frequency to bring the PLL into unlocked mode. Higher the SG4 frequency and measure the frequency at which the PLL locks again. NT Trap1 (4.5MHz), 2 (4.8MHz) BG Trap1 (5.5MHz), 2 (5.85MHz) I Trap1 (6.0MHz) 2 (6.55MHz) DK Trap1 (6.5MHz) NTR1 NTR2 BTR1 BTR2 ITR1 ITR2 DTR1 SG7 Determine the output level difference between carrier frequencies of 1Mhz, 4.5MHz and 4.8MHz. (Reference:1MHz) SG7 Determine the output level difference between carrier frequencies of 1Mhz, 5.5MHz and 5.85MHz. (Reference:1MHz) SG7 Determine the output level difference between carrier frequencies of 1MHz, 6.0MHz and 6.55MHz. (Reference:1MHz) SG7 Determine the output level difference between carrier frequencies of 1MHz and 6.5MHz. (Reference:1MHz) SIF.SYS = "11" SIF.SYS = "10" SIF.SYS = "01" SIF.SYS = "00" Bus conditions 29 29 29 29 29 NoA0017-10/31 LA76850 SIF Block (FM block) Input Signals and Test Conditions Unless otherwise specified, the following conditions apply when each measurement is made. 1. Bus control condition: IF.AGC.SW = "1", SIF.SYS = "01", DEEM-TC = "0", FM.GAIN = "0", A.MONI.SW = "0", A2.SW = "0" 2. SW:IF1 = "ON", 24pin = 5V 3. Input signals are input to pin 54 and the carrier frequency is 5.5MHz. Input signal FM detection output voltage Symbol SOADJ Test point Input signal 90dBµ, fm = 400Hz, FM = ±30kHz FM limiting sensitivity FM detection output f characteristics (fm=100kHz) FM detection output distortion STHD SF SLS fm = 400Hz, FM = ±30kHz 90dBµ, fm = 100kHz FM = ±30kHz 90dBµ, fm = 400Hz, FM = ±30kHz AM rejection ratio SAMR 90dBµ, fm = 400Hz, AM = 30% Measure the 400Hz component (SV3: mVrms) of the FM detection output at pin 2. Assign the measured value to SV3 and calculate as follows: SAMR = 20*log (SV1/SV3) [dB] SIF.S/N SSN 90dBµ, CW 90dBµ, fm = Measure the noise level (DIN AUDIO, SV4: mVrms) at pin 2. Calculate as follows: SSN=20*log(SV1/SV4) [dB] PAL de-emph time constant SPTC Measure the 3.18kHz component (SV5: mVrms) of the FM detection output at pin 2 and calculate as follows: SNTC = 20*LOG (SV1/SV5) [dB] Measure the 400Hz component (SV6: mVrms) of the FM detection output at pin 2 and calculate as follows: SNTC = 20*LOG (SV1/SV6) [dB] Measure the 2.12kHz component (SV7: mVrms) of the FM detection output at pin 2 and calculate as follows: SNTC = 20*LOG (SV6/SV7) [dB] SIF.SYS = "00" DEEM-TC = "1" FM.GAIN = "1" SIF.SYS = "00" DEEM-TC = "1" FM.GAIN = "1" Measure the input level (dBµ) at which the 400Hz component of the FM detection output at pin 2 becomes -3dB relative to SV1. Set SW: IF1 = "OFF". Measure (SV2: mVrms) the FM detection output of pin 2. Calculate as follows: SF = 20*LOG (SV1/SV2) [dB] Measure the distortion factor of the 400Hz component of the FM detection output at pin 2. Test method Measure the 400 Hz component (SV1: mVrms) of the FM detection output at pin 2. Bus conditions 2 2 2 2 2 2 2 3.18KHz FM = ±30KHz PAL/NT Difference of voltage gain SGD fo = 4.5MHz 2 90dBµ, fm = 400Hz FM = ±15KHz NT de-emph time constant SNTC fo = 4.5MHz 2 90dBµ, fm = 2.12kHz FM = ±15kHz NoA0017-11/31 LA76850 Audio Block Input Signals and Test Conditions Unless otherwise specified, the following conditions apply when each measurement is made. 1. Bus control condition: AUDIO.MUTE = "0", A.MONI.SW = "0", AUDIO.SW = "1", VOL.FIL = "0", SIF.SYS = "01", IF.AGC.SW = "1" 2. Input 5.5MHz, 90dBµ and CW at pin 54. 3. Enter an input signal from pin 51. Input signal Maximum gain Symbol AGMAX Test point Input signal 1kHz, CW 500mVrms 1kHz, CW Test method Measure the 1kHz component (V1: mVrms) at the pin 1 and calculate as follows: AGMAX = 20*LOG(V1/500) [dB] Variable range ARANGE Measure the 1kHz component (V2: mVrms) at the pin 1 and calculate as follows: ARANGE = 20*LOG(V1/V2) [dB] Frequency characteristics Mute AMUTE AF Measure the 20kHz component (V3: mVrms) at the pin 1 and calculate as follows: AF = 20*Log(V3/V1) [dB] Measure the 20kHz component (V4: mVrms) at the pin 1 and calculate as follows: AMUTE = 20*Log(V3/V4) [dB] Distortion S/N ATHD ASN Measure the distortion of the 1kHz component at the pin 1. Measure the noise level (DIN AUDIO, V5: mVrms) at the pin 1 and calculate as follows: ASN = 20*log(V1/V5) [dB] Crosstalk ACT 1kHz, CW 500mVrms Measure the 1kHz component (V6: mVrms) at the pin 1 and calculate as follows: ACT = 20*LOG(V1/V6) [dB] VOLUME = "0000000" VOLUME = "1111111" VOLUME = "1111111" AUDIO.MUTE = ”1” VOLUME = "1111111" VOLUME = "1111111" VOLUME = "1111111" AUDIO.SW = "0" Bus conditions VOLUME = "1111111" 1 1 500mVrms 20kHz, CW 500mVrms 20kHz, CW 500mVrms 1kHz, CW 500mVrms No signal 1 1 1 1 1 NoA0017-12/31 LA76850 Video Block Input Signals Y IN inpt signal 100IRE: 714mV Bus control bit conditions: Initial test state 0IRE signal (L-0): NTSC standard sync signal PEDESTAL LEVEL H SYNC 4.7µs (H/V SYNC:40IRE: 286mV) XIRE signal (L-X) XIRE (X = 0 to 100) 0IRE CW signal (L-CW) 20IRE CW signal 50IRE BLACK STRETCH 0IRE signal (L-BK) 50µs 100IRE 5µs (Point A) OSD IN Input signal OSD Input signal 1 (0-1) to each 20µs 0.35V AB 0.7V 0.0VDC OSD Input signal 2 (0-2) 20µs 30µs 1.0VDC 0.0VDC NoA0017-13/31 LA76850 Video Block Test Conditions Input signal Video signal input 1DC voltage Video signal input 1 AC voltage Video overall gain (Contrast max) Contrast adjustment characteristics (normal/max) Contrast adjustment characteristics (min/max) Video frequency Characteristics 1 (NTSC) BW1 L-CW With the input signal’s continuous Wave = 100kHz, measure the output signal’s continuous wave amplitude (PEAKDC Vp-p). With the input signal’s continuous wave = 1.8MHz, measure the output signal’s continuous wave amplitude (CW1.8 Vp-p). Calculate BW1 = 20Log (CW1.8/PEAKDC). Video frequency Characteristics 2 (PAL) Chroma trap amount PAL CtraPP L-CW BW2 L-CW With the input signal’s continuous wave = 2.2MHz, measure the output signal’s continuous wave amplitude (CW2.2 Vp-p). Calculate BW2 = 20Log (CW2.2/PEAKDC). With the input signal’s continuous wave = 4.43MHz, measure the output signal’s continuous wave amplitude (F0P Vp-p). Calculate CtraP = 20Log (F0P/PEAKDC). Chroma trap amount NTSC CtraPN L-CW With the input signal’s continuous wave = 3.58MHz, measure the output signal’s continuous wave amplitude (F0N Vp-p). Calculate CtraN = 20Log (F0N/PEAKDC). DC transmission amount ClampG1 L-0 Measure the output signal’s 0IRE DC level (BRTPL V). Brightness: 0000000 CONTRAST: 1111111 L-100 Measure the output signal’s 0IRE DC level (DRVPH V) and 100IRE amplitude (DRVH Vp-p) and calculate ClampG = 100 × (1+(DRVPH - BRTPL)/DRVH). Brightness: 0000000 Contrast: 1111111 DCREST = 00 BLK.ST.DEF = 1 WPL = 0 Sharpness variable range (PAL) Sharp32T2 L-CW With the input signal’s continuous wave = 2.7MHz, measure the output signal’s continuous wave amplitude (F02S32 Vp-p). Calculate Sharp32T3 = 20Log (F02S32/PEAKDC). (max) Sharp63T2 L-CW With the input signal’s continuous wave = 3MHz, measure the output signal’s continuous wave amplitude (F02S63 Vp-p). Calculate Sharp63T2 = 20Log (F02S63/PEAKDC). (min) Sharp0T2 L-CW With the input signal’s continuous wave = 3MHz, measure the output signal’s continuous wave amplitude (F02S0 Vp-p). Calculate Sharp0T2 = 20Log (F02S0/PEAKDC). Continued on next page. Filter Sys:0010 Sharpness: 000000 Filter Sys:0010 Sharpness: 111111 Filter Sys:0010 Sharpness: 100000 FILTER SYS: 000 Sharpness: 000000 FILTER SYS: 010 Sharpness: 000000 FILTER SYS: 0010 SHARPNESS: 000000 FILTER SYS: 0000 SHARPNESS: 000000 CONT0 L-50 Measure the output signal’s 50IRE amplitude (CNTLB Vp-p) and calculate CONT0 = 20log (CNTLB/0.357). CONTRAST: 0000000 CONT63 CONT127 VIN1AC Symbol VIN1DC Test point Input signal L-100 the pedestal. Pin 28 recommended input level Test method Input signals to pin 28 and measure the voltage of Bus conditions VIDEO SW:1 28 28 L-50 Measure the output signal’s 50IRE amplitude (CNTHB Vp-p) and calculate CONT127 = 20log (CNTHB/0.357). L-50 Measure the output signal’s 50IRE amplitude (CNTCB Vp-p) and calculate CONT63 = 20log (CNTCB/0.357). CONTRAST: 0111111 CONTRAST: 1111111 17 17 17 17 17 17 17 17 17 17 17 NoA0017-14/31 LA76850 Continued from preceding page. Input signal Y gamma effective point1 Symbol YG1 Test point Input signal L-100 Test method Measure the output amplitude (0 to 100 IR) when the Y gamma is 0 (GAM0). Then set Y gamma to 1 and measure the output amplitude (0 to 100 IR) again (GAM1). Calculate YG1 = (GAM1/GAM0) × 100. Y gamma effective point12 YG2 L-100 Measure the output amplitude (0 to 100 IR) when the Y gamma is 0 (GAM0). Then set Y gamma to 2 and measure the output amplitude (0 to 100 IR) again (GAM2). Calculate YG2 = (GAM2/GAM0) × 100. Y gamma effective point1 YG3 L-100 Measure the output amplitude (0 to 100 IR) when the Y gamma is 0 (GAM0). Then set Y gamma to 3 and measure the output amplitude (0 to 100 IR) again (GAM3). Calculate YG3 = (GAM3/GAM0) × 100. Horizontal/vertical blanking output level [OSD block] Bus control bit conditions: Contrast = 63, Brightness = 63 Contrast: 0111111 Brightness: 0111111 OSD Fast SW threshold OSD output level OSDH FSTH L-0 Apply voltage to pin 15 and measure the voltage at pin 15 at the point where the output signal switches to the OSD signal. L-50 Measure the output signal’s 50IRE amplitude (CNTCB Vp-p). L-0 O-2 Measure the OSD output amplitude (OSDHB Vp-p). Calculate OSDH = 50 × (OSDHB/CNTCB) [Y output block] (Cutoff, drive block) Brightness control (normal) Brightness control (normal-H) Brightness control (max) BRT127 BRT63H BRT63 L-0 Bus control bit conditions: Contrast = 127 Measure the 0IRE DC levels of the respective output signals of Y output (17) L-0 Measure the 0IRE DC level of the output Signal of Y output (17) and assign the Measured value to BRTPC. L-0 Measure the 0IRE DC level of the output Signal of Y output (17) and assign the Measured value to BRTPH. Calculate BRT127 = 50×(BRTPH-BRTPC)/CNTHB. Brightness control (min) BRT0 L-0 Measure the 0IRE DC level of the output Signal of Y output (17) and assign the Measured value to BRTPL. Calculate BRT0 = 50× (BRTPL-BRTPC)/CNTHB. Bright control resolution Vsiassns L-50 Measure the 0IRE DC levels (BTPM V) of the respective output signals of Y output (17). Vbiassns = (BRTPH-BTPM)/127 Sub-bias control resolution Vsbiassns L-50 Measure the 0IRE DC levels (SBTPM V) of the respective output signals of Y output (17). Vsbiassns = (BRTPCH-SBTPM)/127 Brightness: 0000000 Sub Bias: 1111111 Brightness: 0111111 Sub Bias: 0000000 Brightness: 0000000 Sub Bias: 1111111 Brightness: 0111111 Sub Bias: 1111111 Brightness: 1111111 Sub Bias: 1111111 Contrast: 1111111 Brightness: 01111111 Osd cont = 0111111 Digital osd = 1 Pin 15: 3.5V Pin 14A: O-2 applied Pin 14A: O-2 applied RGBBLK L-100 Measure the DC level (RGBBLK V) for the output signal’s blanking period. Y GAMMA = 3 Y GAMMA = 2 Bus conditions Y GAMMA = 1 17 17 17 17 17 O-2 17 17 17 17 17 17 17 NoA0017-15/31 LA76850 Deflection Block Input Signals Unless otherwise specified, the following conditions apply when each measurement is made. 1. VIF, SIF blocks: No signal 2. C input: No. signal 3. Sync input: A horizontal/vertical composite sync signal PAL: NTSC: 43IRE, horizontal sync signal (15.625kHz) and vertical sync signal (50kHz) 40IRE, horizontal sync signal (15.734264kHz) and vertical sync signal (59.94kHz) Note: No burst signal, chroma signal shall exist below the pedestal level. Signal unsuitable for Y input Signal suitable for Y input Chroma signal Burst signal 4. Bus control conditions: Initial conditions unless otherwise specified. 5. The delay time from the rise of the horizontal output (pin 22 output) to the fall of the FBP IN (pin 23 input) is 9µs. 6. Pin 13 (vertical size correction circuit input terminal) is connected to VCC (5.0V). NoA0017-16/31 LA76850 Deflection Block Test Conditions Input signal Horizontal free-running frequency Horizontal output pulse length Hduty Symbol fH Test point Input signal Y IN: No signal Y IN: Test method Connect a frequency counter to the output of pin 22 (H out) and measure the horizontal free-running frequency. Measure the voltage for the pin 22 horizontal output pulse’s low-level period. Bus conditions 22 22 Horizontal/ vertical sync signal PAL Horizontal output pulse saturation voltage V Hsat Y IN: Measure the voltage for the pin 22 horizontal output pulse’s low-level period. 22 Horizontal/ vertical sync signal PAL Vertical free-running period 50 (PAL) Vertical free-running period 60 (NTSC) VFR50 VFR60 Y IN: Measure the vertical output period T at pin 18 T×15.625kHz (PAL) T×15.734kHz (NTSC) CDMODE: 001 (PAL) CDMODE: 002 (NTSC) 18 No signal Vertical output 2.5V T Horizontal output pulse HPHCEN (PAL) (NTSC) Y IN: Measure the delay time from to the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal. 22 Horizontal/ vertical sync signal PAL NTSC 28 HPHCEN 20IRE 2.5V Horizontal output Horizontal position adjustment range HPHrange Y IN: With H PHASE: 0 and 31, measure the delay time from the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal and calculate the difference from H PHCEN. H PHASE: 00000 H PHASE: 11111 22 Horizontal/ vertical sync signal PAL 28 Measuring 20IRE 2.5V Horizontal output Continued on next page. NoA0017-17/31 LA76850 Continued from preceding page. Input signal Horizontal position adjustment maximum variable width Symbol HPHstep Test point Input signal Y IN: Horizontal/ vertical sync signal Test method With H PHASE: 0 to 31 varied, measure the delay time from to the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal and calculate the variation at each step. Retrieve data for maximum variation. to H PHASE: 11111 Bus conditions H PHASE: 00000 22 28 PAL Measuring 20IRE 2.5V Horizontal output Horizontal blanking left variable range@0 BLKL0 Y IN: Measure the time T from the left end of Hsync at pin 28 Y IN to the left end of blanking at pin 17 BlueOUT with BLKL = 000. BLKL: 000 22 Horizontal/ vertical sync signal 28 PAL Y IN Hsync T Blue Horizontal blanking left variable range@7 BLKL7 Y IN: Measure the time T from the left end of Hsync at pin 28 Y IN to the left end of blanking at pin 17 BlueOUT with BLKL = 111. BLKL:111 17 Horizontal/ vertical sync signal PAL 28 Y IN Hsync T Blue Continued on next page. NoA0017-18/31 LA76850 Continued from preceding page. Input signal Horizontal blanking right variable range@0 Symbol BLKR0 Test point Input signal Y IN: Test method Measure the time T from the left end of Hsync at pin 28 Y IN to the left end of blanking at pin 17 BlueOUT with BLKR = 000. Bus conditions BLKR:000 17 Horizontal/ vertical sync signal PAL 28 Y IN T Hsync Blue Horizontal blanking right variable range@7 BLKR7 17 Y IN: Horizontal/ vertical sync signal PAL Measure the time T from the left end of Hsync at pin 28 Y IN to the left end of blanking at pin 17 BlueOUT with BLKR = 111. BLKR:111 28 Y IN T Hsync Blue Sand castle pulse crest value H SANDH Y IN: Measure the supply voltage at point H of the pin 23 FBP IN wave form for Hsync period. 23 Horizontal/ vertical sync signal PAL H Sand castle pulse crest value M1 SANDM1 Y IN: Measure the supply voltage at point M1 of the pin 23 FBP IN wave form for Hsync period. 23 Horizontal/ vertical sync signal PAL M1 Sand castle pulse crest value L SANDL Y IN: Measure the supply voltage at point L of the pin 23 FBP IN wave form for Hsync period. 23 Horizontal/ vertical sync signal PAL L Sand castle pulse crest value M2 SANDM2 Y IN: Measure the supply voltage at point M2 of the pin 23 FBP IN wave form for Vsync period. 23 Horizontal/ vertical sync signal PAL L Continued on next page. NoA0017-19/31 LA76850 Continued from preceding page. Input signal Burst gate pulse length Symbol BGPWD Test point Input signal Y IN: Horizontal/ vertical sync signal PAL Test method Measure the BGP width T of the pin 28 FBP IN wave form for Hsync period. Bus conditions 23 T Burst gate pulse I phase BGPPH Y IN: Measure the time from the left end of Hsync at pin 42 Y IN to the left end of the pin 23 FBP IN wave form for Hsync period. 23 Horizontal/ vertical sync signal Hsync Y IN 42 PAL T FBPIN Horizontal output stop voltage Hstop Y IN: Decrease the current from a source connected to pin 20 and measure the pin 20 voltage at which HOUT stops. 20 Horizontal/ vertical sync signal 22 Continued on next page. NoA0017-20/31 LA76850 Continued from preceding page. Input signal Symbol Test point Input signal Test method Bus conditions Vertical ramp output Amplitude PAL@64 NTSC@64 Vspal64 Vsnt64 Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at line 24 (22:NTSC) and line 310 (262:NTSC). Calculate as follows: Vspal64 = Vline310-Vline24 Vsnt64 = Vline262-Vline22 Vertical ramp output 18 Horizontal/ vertical sync signal PAL NTSC Line 310 Line 24 Vertical ramp output amplitude PAL@0 NTSC@0 Vspal0 Vsnt0 Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at line 24 (22:NTSC) and line 310 (262:NTSC). Calculate as follows: Vspal0 = Vline310-Vline24 Vsnt0 = Vline262-Vline22 Vertical ramp output VSIZE: 0000000 18 Horizontal/ vertical sync signal PAL NTSC Line 310 Line 24 Vertical ramp output amplitude PAL@127 NTSC@127 Vspal127 Vsnt127 Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at line 24 (22: NTSC) and line 310 (262: NTSC). Calculate as follows: Vspal27 = Vline310-Vline24 Vsnt127 = Vline262-Vline22 Vertical ramp output VSIZE: 1111111 18 Horizontal/ vertical sync signal PAL NTSC Line 310 Line 24 Vertical size correction@0 Vsizecomp Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at the line 24 and line 310 with VCOMP = 000. Calculate as follows: Va = Vline310-Vline24 Apply 4.1V to pin 13 and measure the voltage at the line 24 and line 310 again. Calculate as follows: Va = Vline310-Vline24 Calculate as follows: Vsizecomp = Vb/Va Vertical ramp output VCOMP: 000 18 Horizontal/ vertical sync signal PAL Line 310 Line 24 Continued on next page. NoA0017-21/31 LA76850 Continued from preceding page. Input signal Symbol Test point Input signal Test method Bus conditions Vertical ramp DC voltage PAL@32 NTSC@32 Vdcpal32 Vdcnt32 Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at line 167. (PAL) Monitor the pin 18 vertical ramp output and measure the voltage at line 142. (NTSC) Vertical ramp output 18 Horizontal/ vertical sync signal PAL NTSC Line 167 Vertical ramp DC voltage PAL@0 NTSC@0 Vdcpal0 Vdcnt0 Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at line 167. (PAL) Monitor the pin 18 vertical ramp output and measure the voltage at line 142. (NTSC) Vertical ramp output VDC: 000000 18 Horizontal/ vertical sync signal PAL NTSC Line 167 Vertical ramp DC voltage PAL@63 NTSC@63 Vdcpal63 Vdcnt63 Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at line 167. (PAL) Monitor the pin 18 vertical ramp output and measure the voltage at line 142. (NTSC) Vertical ramp output VDC: 111111 18 Horizontal/ vertical sync signal PAL NTSC Line 167 Continued on next page. NoA0017-22/31 LA76850 Continued from preceding page. Input signal Vertical linearity@16 Symbol Vlin16 Test point Input signal Y IN: Horizontal/ vertical sync signal PAL Test method Monitor the pin 18 vertical ramp output and measure the voltage at line 24, line 167 and 310. Assign the respective measured values to Va, Vb and Vc. Calculate as follows: Vlin16 = (Vb-Va)/(Vc-Vb) Vertical ramp output Line 310 Bus conditions 18 Line 167 Line 24 Vertical linearity@0 Vlin0 Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at line 24, line 167 and 310. Assign the respective measured values to Va, Vb and Vc. Calculate as follows: Vlin0 = (Vb-Va)/(Vc-Vb) Vertical ramp output Line 310 VLIN: 00000 18 Horizontal/ vertical sync signal PAL Line 167 Line 24 Vertical linearity@31 Vlin31 Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at line 24, line 167 and 310. Assign the respective measured values to Va, Vb and Vc. Calculate as follows: Vlin31 = (Vb-Va)/(Vc-Vb) VLIN: 11111 18 Horizontal/ vertical sync signal PAL Vertical ramp output Line 310 Line 167 Line 24 Continued on next page. NoA0017-23/31 LA76850 Continued from preceding page. Input signal Vertical S-shaped correction @16 Symbol VScor16 Test point Input signal Y IN: Horizontal/ vertical sync signal PAL Test method Monitor the pin 18 vertical ramp output and measure the voltage at line 36, line 60, line 155, line 179, line 274 and 298. Assign the respective measured values to Va, Vb, Vc, Vd, Ve and Vf. Calculate as follows: VScor16 = 0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc) Line 298 Vertical ramp output Line 179 Line 60 Line 274 Line 155 Line 36 Vertical S-shaped correction @0 VScor0 Y IN: Horizontal/ vertical sync Monitor the pin 18 vertical ramp output and measure the voltage at the line 36, line 60, line 155, line 179, line 274 and line 298 with VSC = 00000. Assign the respective measured values to Va, Vb, Vc, Vd, Ve and Vf. Calculate as follows: VScor0 = 0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc) Line 298 Vertical ramp output Line 179 Line 60 Line 274 Line 155 Line 36 Vertical S-shaped correction @31 VScor31 Y IN: Monitor the pin 18 vertical ramp output and measure the voltage at line 36, line 60, line 155, line 179, line 274 and 298. Assign the respective measured values to Va, Vb, Vc, Vd, Ve and Vf. Calculate as follows: VScor16 = 0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc) Line 298 Vertical ramp output Line 179 Line 60 Line 274 Line 155 Line 36 VSC: 11111 Bus conditions VS: 10000 18 18 signal PAL 18 Horizontal/ vertical sync signal PAL NoA0017-24/31 LA76850 Control Register Bit Allocation Map Control Register Bit Allocations (continued) Sub Address DA0 00010000 OSD Cnt.Test 0 10001 1 0 Sharpness 0 * (0) * (0) Trap Test 1 Cross B/W 0 FBPBLK. SW 0 10111 0 11000 * (0) 11001 Cont. Test 0 11010 * (0) 11011 * (0) 11100 * (0) 11101 OVER. MOD.SW 0 11110 FM.Mute 0 11111 1 0 deem.TC 0 VIDEO.LEVEL 0 0 0 1 VIF.Sys.SW 1 * (0) 0 * (0) 0 0 SIF.Sys.SW 1 * (0) 0 0 FM.Gain 0 * (0) 0 IF.AGC 0 * (0) 0 VOL.FIL 0 0 1 Y Gamma Start 0 * (0) Digital OSD 0 * (0) * (0) (0) * (0) * (0) Brt.Abl. Def 0 * (0) * (0) 0 * (0) * (0) 0 * (0) * (0) Mid.Stp.Def 0 * (0) * (0) RGB Temp SW 0 * (0) * (0) Volume 0 RF.AGC 0 0 0 1 * (0) * (0) 0 * (0) * (0) 0 * (0) * (0) 0 * (0) * (0) (0) * (0) * (0) Bright.Abl.Threshold (0) * (0) * (0) 0 * 0 0 * (0) Y_APF 0 * (0) * (0) 0 * (0) * (0) Filter.Sys 0 * (0) 0 * (0) 1 * (0) * 0 * (0) * 0 * (0) * (0) 0 * (0) * (0) 0 * (0) * (0) 0 0 0 0 0 DA1 MSB DA2 DA3 DA4 OSD Contrast DATA BITS DA5 DA6 LSB DA7 Coring Gain(W/Defeat) 0 0 * (0) * (0) 10010 * (0) 10011 * (0) 10100 * (0) 10101 Gray Mode 0 10110 VBLK SW Pre/Over-shoot adj. (Bits are transmitted in this order.) NoA0017-25/31 LA76850 Control Register Truth Table Register Name T.Disable AFC gain&gate 0 HEX Tset Enable Auto (Gain) Auto (Gate) V Reset Timing Audio.Mute Video.Mute Sync.Kill Vsepup V.KILL Vertical Test Drive.Test Half Tone Half Tone Def Blank.Def S.TRAP.SW OSD Cnt.Test Coring Gain(w/Defeat) Color.Test Video.SW Gray Mode Cross B/W G-Y Angle VBLK SW Normal Active Active Sync active normal Vrt active Normal Normal Min (Dark) Half Tone on Blanking Bypass ON Normal Defeat Normal Internal Mode Normal Normal 240deg 24H to 262H (NTSC) 25H to 309H (PAL) FBPBLK.SW Y APF Pre/Over-shoot adj. Y Gamma Start Digital OSD Brt.ABL.Def Mid.Stp.Def RGB Temp SW OVER.MOD.(circuit)SW VOL.FIL FM.Mute de-em TC. VIF.Sys.SW FM Gain IF.AGC Pre/Over SW Hlock.Vdet VIDEO.LEVEL.OFFSET FBP not or Y Trap Normal Y Gamma off Analogue Brt ABL On Mid Stp On -1Vbe circuit OFF Normal Active 50µs 38.0MHz 50kHz dev. AGC active Pre-shoot Adj. Individual Operation direction: Minus 1 HEX Test Disable Gain:Fast Non-Gate 1/4H Shift Mute Mute Sync killed Vsepup Vrt killed Vrt S Corr Test Mode → Half Tone off No Blank Bypass OFF Test Mode Min Test Mode External Mode Gray OSD Black 253deg 29H to 256H (NTSC) 30H to 304H (PAL) FBP or Y APF +10ns Min Digital Brt ABL Off Mid Stp Off Flat circuit ON Filte OFF Mute 75µs 38.9MHz 25kHz dev AGC defeat Over-shoot Adj. Normal Center direction: Plus 45.75MHz 39.5MHz +20ns → +30ns Max White Cross → Max → Max Vrt Lin Vrt Size 2 HEX 3 HEX NoA0017-26/31 LA76850 Control Register Truth Table COUNT DOWN MODE 50Hz/60Hz MODE 0 HEX 1 HEX 2 HEX 3 HEX 4 HEX 5 HEX 6 HEX 7 HEX Auto 50Hz 60Hz Auto Auto 50Hz 60Hz Auto Standard/Non-Standard MODE Auto Auto Auto Auto Non-Standard Non-Standard Non-Standard Non-Standard Filter System Y Filter 0 HEX 1 HEX 2 HEX 3 HEX 4 HEX 5 HEX 6 HEX 7 HEX 8-15HEX 3.58MHz Trap 3.58MHz Trap 4.43MHz Trap 4.43MHz Trap 6.0MHz Trap 6.0MHz Trap 6.0MHz Trap 6.0MHz Trap 4.286MHz Trap Chroma Filter Peaked 3.58MHz BPF Symmetrical 3.58MHz BPF Peaked 4.43MHz BPF Symmetrical 4.43MHz BPF Peaked 3.58MHz BPF Symmetrical 3.58MHz BPF Peaked 4.43MHz BPF Symmetrical 4.43MHz BPF Symmetrical 4.43MHz BPF Snd.Trap & FM.Det A2.SW 0 HEX SIF.Sys.SW 0 HEX 1 HEX 2 HEX 3 HEX 1 HEX 0 HEX 1 HEX 2 HEX 3 HEX Snd.Trap 4.5MHz 5.5MHz 6.0MHz 6.5MHz ----------5.5NHz --------------------FM.det 4.5MHz 5.5MHz 6.0MHz 6.5MHz ----------5.74MHz --------------------- Audio Monitor Output A.MONI.SW 0 HEX AUDIO.SW 0 HEX 1 HEX 1 HEX 0 HEX 1 HEX 1pin Output Internal External Internal External Internal External (before VOLUME) 2pin Output Internal Status Byte Truth Table Register RF.AGC IF.LOCK V.TRI 50/60 ST/NONST 0 HEX RF.AGC.OUT = "L" IF.PLL Lock V.Triger Undetected 50 Non-Standard 1 HEX RF.AGC.OUT = "H" IF.PLL Unlock V.Triger Detected 60 Standard NoA0017-27/31 LA76850 Initial Conditions Initial Test Conditions Register Name T.Disable AFC gain&gate H.FREQ V Reset Timing Audio.Mute Video.Mute H.PHASE Sync.Kill V.SIZE VSEPUP V.KILL V.POSI H BLK L H BLK R V.LIN V.SC V.TEST V.COMP COUNT.DOWN.MODE RGB Test 4 Half Tone Half Tone Def A2 SW Blank.Def Sub.Bias A.MONI.SW Bright S.TRAP.SW Contrast OSD Cnt.Test OSD Contrast Value 1 HEX 0 HEX 3F HEX 0 HEX 0 HEX 0 HEX 10 HEX 0 HEX 40 HEX 0 HEX 0 HEX 20 HEX 4 HEX 4 HEX 10 HEX 00 HEX 0 HEX 7 HEX 0 HEX 0 HEX 1 HEX 1 HEX 0 HEX 0 HEX 40 HEX 0 HEX 40 HEX 1 HEX 40 HEX 0 HEX 0 HEX VBLK SW FBPBLK.SW Y_APF Pre/Over-shoot Adj. Y Gamma Digitsl OSD Brt.Abl.Def Mid.Stp.Def RGB Temp SW Bright.Abl.Threshold Volume OVER.MOD.SW VOL.FIL RF.AGC FM.Mute deem.TC VIF.Sys.SW SIF.Sys.SW FM.Gain IF.AGC VIDEO.LEVEL Pre/Over SW H lock.Vdet VIDEO.LEVEL.OFFSET IF.TEST1 OVER.MOD.LEVEL Coring Gain (w/Defeat) Sharpness Trap.Test Filter.Sys Gray Mode Cross B/W Initial Test Conditions (continued) Register Name Value 0 HEX 1 HEX 0 HEX 0 HEX 0 HEX 0 HEX 0 HEX 0 HEX 0 HEX 4 HEX 00 HEX 0 HEX 0 HEX 20 HEX 0 HEX 0 HEX 1 HEX 1 HEX 0 HEX 0 HEX 4 HEX 0 HEX 0 HEX 1 HEX 0 HEX 8 HEX 0 HEX 00 HEX 4 HEX 2 HEX 0 HEX 0 HEX NoA0017-28/31 LA76850 Control Register Descriptions Register Name T Disable AFC Gain & gate H Freq. V Reset Timing Audio Mute Video Mute H PHASE Sync Kill Vertical Size Vsep.up Vertical Kill V POSI (Vertical DC) H BLK L H BLK R V LIN (Vertical Linearity) Vertical S-Correction Vertical Test Vertical Size Compensation Count Down Mode Half Tone Half Tone Defeat A2.SW Blank Def Sub Bias A.MONI.SW Brightness Control S.TRAP.SW Contrast Control OSD Contrast Test OSD Contrast Control Coring Gain Select (with Defeat) Sharpness Control Trap.Test Filter System Gray Mode Cross B/W Vertical Blanking SW FBPBLK.SW Y APF Enable SW Pre/Over-shoot Adjustmant Y Gamma Start DC Restoration Select Cont Test Digital OSD SW Bright ABL Defeat Bright Mid Stop Defeat RGB Temp SW Bright ABL Threshold Volume Control OVER.MOD.SW 6 3 3 1 2 1 1 1 2 2 2 1 1 1 1 1 3 7 1 Customer sharpness control Trap Test Select Y/C Filter mode OSD Gray Tone Enable Service Test Mode (normal/Black/White/Cross) Select VBLK Period Enable RGB Blanking or FBP Select the frequency caracteristic of 3.58MHzTrap. It is useful for 3.58MHzTrap or APF Select Pre-shoot Width Enable luminance coring Select Luma DC Restoration Enable contrast DAC test mode Select Digital/Analogue OSD Disable brightness ABL Disable brightness mid stop Select temprature caracteristic of RGB Output Align brightness ABL threshold Customer volume control Select overmodulation circuit ON/OFF Continued on next page. Bits 1 1 6 1 1 1 5 1 7 1 1 6 3 3 5 5 2 3 1 2 1 1 1 7 1 7 1 7 1 2 2 General Description Disable the Test SW & enable Audio/Video Mute SW Select horizontal first loop gain & H-sync gating on/off Align ES Sample horizontal frequency Select Vertical Reset Timing Disable audio outputs Disable video outputs Align sync to flyback phase Force free-run mode Align vertical amplitude Select vertical sync. separation sensitivity Disable vertical output Align vertical DC bias H-Blanking Control (Left side of the screen) H-Blanking Control (Right side of the screen) Align vertical linearity Align vertical S-correction Select vertical DAC test modes Align vertical size compensation Select vertical countdown mode Adjust half tone DC level Half tone defeat SW Select 5.74MHz FM.Det Disable RGB output blanking Align common RGB DC level Select FM Output/Selected Audio Output Customer brightness control Select Snd Trap bypass Customer contrast control Enable OSD Contrast DAC test mode Align OSD AC level Select Coring Gain (0hex: Defeat) NoA0017-29/31 LA76850 Continued from preceding page. Register Name Volume Filter Defeat RF AGC Delay FM Mute de-em TC. VIF System SW SIF System SW FM Gain IF AGC Defeat Video Level FM Level Pre/Over SW H Lock Vdet VIDEO.LEVEL.OFFSET IF TEST1 OVER.MOD.LEVEL Bits 1 6 1 1 2 2 1 1 3 5 1 1 2 1 4 Disable volume DAC filter Align RF AGC threshold Disable FM outputs Select de-emphasis Time Constant Select 38.0/38.9/39.5/45.75 Select 4.5/5.5/6.0/6.5 Select FM Output Level Disable IF and RF AGC Align IF video level Align FM output level Select control for Pre/Over-shoot Adjustmant Select vertical sync. Operation Align IF video level Select test modes Align overmodulation performance General Description NoA0017-30/31 LA76850 Read Status Description RF.AGC IF.LOCK V.TRI 0: RF AGC = low, 1: RF AGC = high. See the separately provided documentation (Application Note) for details. 0: IF.PLL = Locked, 1: IF.PLL = Unlocked Returns the output of the VCD internal vertical trigger detection circuit to the bus. The state of the internal memory is updated every vertical period. 1HEX: Detected 50/60 ST/NONST Returns the output of the VCD internal 50/60 Hz detection output to the bus. Returns to the bus whether a standard (262.5H) VCD or a nonstandard internal vertical trigger detection circuit output VCD is used. Returns the FF output determined by the VCD internal mode in real time. 1HEX: Standard H.Lock Performs FBP and Hsync phase detection, integrates that output, and detects at a point about 40H after the HVCO locks. Returns, in real time, the state with respect to bus reads. 1Hex: Locked Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2005. Specifications and information herein are subject to change without notice. This catalog provides information as of November, 2005. Specifications and information herein are subject to change without notice. PS NoA0017-31/31