LB11620T

Ordering number : ENA0662A LB11620T Overview Monolithic Digital IC Brushless Motor Driver The LB11620T is a direct PWM drive predriver IC that is optimal for three-phase power brushless motors. A motor driver circuit with the desired output capability (voltage and current) can be implemented by adding discrete transistors or other power devices to the outputs of this IC. Since the LB11620T is provided in a miniature package, it is also appropriate for use with miniature motors as well. Features • Three-phase bipolar drive • Direct PWM drive (input of either a control voltage or a variable-duty PWM signal) • Built-in forward/reverse switching circuit • Full complement of protection circuits (current limiter, low-voltage, and automatic recovery lock (motor constraint) protection circuits) • Selectable Hall sensor signal pulse output Specifications Maximum Ratings at Ta = 25°C Parameter Supply voltage 1 Output current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max IO max Pd max Topr Tstg VCC pin UL, VL, WL, UH, VH, WH pins *Mounted on a circuit board. Conditions Ratings 18 30 0.8 -20 to +100 -55 to +150 Unit V mA W °C °C * Mounted on a circuit board : 114.3mm×76.1mm×1.6mm, glass epoxy board. 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O0808 MS / 22807 MS PC 20061227-S00002 No.A0662-1/11 LB11620T Recommended Operating Ranges at Ta = 25°C Parameter Supply voltage range 1-1 Supply voltage range 1-2 Output current 5 V constant voltage output current HP pin voltage HP pin output current RD pin voltage RD pin output current Symbol VCC1-1 VCC1-2 IO IREG VHP IHP VRD IRD VCC pin VCC pin, with VCC shorted to VREG UL, VL, WL, UH, VH, WH pins Conditions Ratings 8 to 17 4.5 to 5.5 25 -30 0 to 17 0 to 15 0 to 17 0 to 15 Unit V V mA mA V mA V mA Electrical Characteristics at Ta = 25°C, VCC = 12V Parameter Supply voltage 1 Symbol ICC1 Conditions min Ratings typ 12 max 16 mA Unit 5V constant voltage output (VREG pin) Output voltage Line regulation Load regulation Temperature coefficient VREG ∆VREG1 ∆VREG2 ∆VREG3 VCC = 8 to 17V IO = -5 to -20mA Design target 4.7 5.0 40 10 0 5.3 100 30 V mV mV mV/°C Low-voltage protection circuit (VREG pin) Operating voltage Clear voltage Hysteresis Output Block Output voltage 1-1 Output voltage 1-2 Output voltage 2 Output leakage current Hall Amplifier Block Input bias current Common-mode input voltage range 1 Common-mode input voltage range 2 Hall input sensitivity Hysteresis Input voltage low → high Input voltage high → low PWM Oscillator (PWM pin) High-level output voltage Low-level output voltage External capacitor charge current Oscillator frequency Amplitude VOH (PWM) VOL (PWM) ICHG f (PWM) V (PWM) VPWM = 2.1V C = 2000pF 1.4 2.75 1.2 -120 3.0 1.35 -90 22 1.6 1.9 3.25 1.5 -65 V V µA kHz Vp-p ∆VIN (HA) VSLH (HA) VSHL (HA) IHB (HA) VICM1 VICM2 When a Hall effect sensor is used For single-sided input bias (Hall IC application) 80 15 5 -20 24 12 -12 40 20 -5 mVp-p mV mV mV -2 0.5 0 -0.5 VCC-2.0 VCC µA V V VOUT1-1 VOUT1-2 VOUT2 IOleak Low level IO = 400µA Low level IO = 10mA High level IO = -20mA VCC-1.1 0.2 0.9 VCC-0.9 10 0.5 1.2 V V V µA VSDL VSDH ∆VSD 3.5 3.95 0.3 3.7 4.15 0.45 3.9 4.35 0.6 V V V Continued on next page No.A0662-2/11 LB11620T Continued from preceding page. Parameter EI+ pin Input bias current Common-mode input voltage range Input voltage 1 Input voltage 2 Input voltage 1L Input voltage 2L Input voltage 1H Input voltage 2H HP pin Output saturation voltage Output leakage current CSD oscillator (CSD pin) High-level output voltage Low-level output voltage External capacitor charge current External capacitor discharge current Charge/discharge current ratio RD pin Low-level output voltage Output leakage current Current limiter circuit (RF pin) Limiter voltage PWMIN pin Input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current F/R pin High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current N1 pin High-level input voltage Low-level input voltage Input open voltage High-level input current Low-level input current VIH (N1) VIL (N1) VIO (N1) IIH (N1) IIL (N1) VN1 = VREG VN1 = 0V 2.0 0 VREG-0.5 -10 -130 0 -100 VREG 1.0 VREG 10 V V V µA µA VIH (FR) VIL (FR) VIO (FR) VIS (FR) IIH (FR) IIL (FR) 2.0 0 VREG-0.5 0.2 -10 -130 0.25 0 -90 VREG 1.0 VREG 0.4 10 V V V V µA µA f (PI) VIH (PI) VIL (PI) VIO (PI) VIS (PI) IIH (PI) IIL (PI) VPWMIN = VREG VPWMIN = 0V 2.0 0 VREG-0.5 0.2 -10 -130 0.25 0 -90 50 VREG 1.0 VREG 0.4 10 kHz V V V V µA µA VRF RF-GND 0.225 0.25 0.275 V VRDL IL (RD) IO = 10mA VO = 18V 0.2 0.5 10 V µA VOH (CSD) VOL (CSD) ICHG1 ICHG2 RCSD VCSD = 2V VCSD = 2V Charge current /discharge current 2.7 0.7 -3.15 0.1 15 3.0 1.0 -2.5 0.14 18 3.3 1.3 -1.85 0.18 21 V V µA µA Times VHPL IHPleak IO = 10mA VO = 18V 0.2 0.5 10 V µA IB (CTL) VICM VCTL1 VCTL2 VCTL1L VCTL2L VCTL1H VCTL2H Output duty 100% Output duty 0% Design target value. When VREG = 4.7V, 100% Design target value. When VREG = 4.7V, 0% Design target value. When VREG = 5.3V, 100% Design target value. When VREG = 5.3V, 0% 1.44 V 3.18 V 1.29 V -1 0 3.0 1.35 2.82 1 VREG-1.7 µA V V V V Symbol Conditions min Ratings typ max Unit No.A0662-3/11 LB11620T Package Dimensions unit : mm (typ) 3260A 1.2 Pd max – Ta Specified circuit board : 114.3×76.1×1.6mm3 glass epoxy board 6.5 24 13 Allowable power dissipation, Pd max – W 0.8 Mounted on a circuit board 4.4 6.4 0.5 1 0.5 (0.5) 0.22 12 0.15 0.4 0.32 (1.0) 1.2max 0 – 20 0 20 40 60 80 100 120 0.08 Ambient temperature, Ta – °C SANYO : TSSOP24(225mil) Pin Assignment VCC 24 VREG 23 EI+ 22 N1 21 HP 20 F/R 19 PWMIN CSD 18 17 RD 16 PWM 15 IN3+ 14 IN313 LB11620T 1 GND 2 RF 3 WH 4 WL 5 VH 6 VL 7 UH 8 UL 9 IN1- 10 IN1+ 11 IN2- 12 IN2+ • Three-Phase Logic Truth Table (IN = “H” indicates the state where IN+ > IN-) F/R = “L” IN1 1 2 3 4 5 6 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R=“H” IN2 H H L L L H IN3 L H H H L L PWM VH WH WH UH UH VH UL UL VL VL WL WL Output • PWMIN pin Input state High or open Low State Output off Output on If the PWM pin is not used, the input must be held at the low level. • N1 pin Input state High or open Low HP output Three Hall sensor synthesized output Single Hall sensor output No.A0662-4/11 LB11620T Pin Functions Pin No. 1 2 Pin GND RF Ground Output current detection. The current detection resistor (Rf) voltage is sensed by the RF pin to implement current detection. The maximum output current is set by RF to be IOUT = 0.25/Rf. 7 5 3 8 6 4 10, 9 12, 11 14, 13 15 16 17 18 UH VH WH UL VL WL IN1+, IN1IN2+, IN2IN3+, IN3PWM RD CSD PWMIN Outputs These are push-pull outputs. Hall sensor inputs from each motor phase. The logic high state indicates that IN+ > IN-. If inputs are provided by a Hall effect sensor IC, the common-mode input range is expanded by biasing either the + or input. Functions as both the PWM oscillator frequency setting pin and the initial reset pulse setting pin. Connect a capacitor between this pin and ground. Lock (motor constrained) detection state output. This output is turned on when the motor is turning and off when the lock protection function detects that the motor has been stopped. This is an open collector output. Sets the operating time for the lock protection circuit. Connect a capacitor between this pin and ground. Connect this pin to ground if the lock protection function is not used. PWM pulse signal input. The output goes to the drive state when this pin is low, and to the off state when this pin is high or open. To use this pin for control, a CTL amplifier input such that the TOC pin voltage goes to the 100% duty state must be provided. 19 20 21 22 23 24 F/R HP N1 EI+ VREG VCC Forward/reverse control input Hall signal output (HP output). This provides either a single Hall sensor output or a synthesized 3-sensor output. Hall signal output (HP output) selection CTL amplifier + (noninverting) input. The PWMIN pin must be held at the low level to use this input for motor control 5V regulator output (Used as the control circuit power supply. A low-voltage protection circuit is built in.) Connect a capacitor between this pin and ground for stabilization. Power supply. Connect a capacitor between this pin and ground to prevent noise and other disturbances from affecting this IC. Outputs (PWM outputs). These are push-pull outputs. Description No.A0662-5/11 LB11620T Hall Sensor Signal Input/Output Timing Chart F/R = " L " IN1 IN2 IN3 UH VH WH UL VL WL F/R = " H " IN1 IN2 IN3 UH VH WH UL VL WL Sections shown in gray are PWM output periods. No.A0662-6/11 VREG 5V + + VM RD + CSD VREG RD CSD OSC LVSD VREG CTL EI+ + Bipolar transistor drive (high side PWM) using a 5V power supply PWM VCC PWM OSC COMP PWMIN CONTROL LOGIC UH UL PRI DRIVER HALL LOGIC VH VL HP LOGIC WH WL Block Diagram and Application Example 1 LB11620T PWM IN VREG HP F/R N1 HALL HYS AMP CURR LIM RF F/R IN1 IN1+ IN1- IN2+ IN2- IN3+ IN3- GND No.A0662-7/11 VCC VREG + RD CSD VM(12V) + RD VREG Tr CSD OSC LVSD VREG Application Example 2 - EI+ + 54 MOS transistor drive (low side PWM) using a 12V single-voltage power supply PWM VCC PWM OSC COMP PWMIN CONTROL LOGIC UL UH PRI DRIVER HALL LOGIC VL VH HP LOGIC WL WH LB11620T PWM IN Tr VREG HP Tr F/R N1 HALL HYS AMP CURR LIM RF F/R IN1 IN1+ IN1- IN2+ IN2- IN3+ IN3- GND No.A0662-8/11 VCC VREG + RD VCC(12V) + RD VREG CSD OSC LVSD VREG VM(24V) + CSD Application Example 3 - EI+ + MOS transistor drive (low side PWM) using a VCC = 12V, VM = 24V power supply system PWM VCC PWM OSC COMP PWMIN CONTROL LOGIC UL UH PRI DRIVER HALL LOGIC VL VH HP LOGIC WL WH LB11620T PWM IN VREG HP F/R N1 HALL HYS AMP CURR LIM RF F/R IN1 IN1+ IN1- IN2+ IN2- IN3+ IN3- GND No.A0662-9/11 VCC VREG + RD CSD VM(24V) + RD VREG CSD OSC LVSD VREG Application Example 4 - EI+ + MOS transistor drive (low side PWM) using a 24V single-voltage power supply PWM VCC PWM OSC COMP PWMIN CONTROL LOGIC UL UH PRI DRIVER HALL LOGIC VL VH HP LOGIC WL WH LB11620T PWM IN VREG HP F/R N1 HALL HYS AMP CURR LIM RF F/R IN1 IN1+ IN1- IN2+ IN2- IN3+ IN3- GND No.A0662-10/11 VCC LB11620T LB11620T Functional Description 1. Output Drive Circuit The LB11620T adopts direct PWM drive to minimize power loss in the outputs. The output transistors are always saturated when on, and the motor drive power is adjusted by changing the on duty of the output. The output PWM switching is performed on the UH, VH, and WH outputs. Since the UL to WL and UH to WH outputs have the same output form, applications can select either low side PWM or high side PWM drive by changing the way the external output transistors are connected. Since the reverse recovery time of the diodes connected to the non-PWM side of the outputs is a problem, these devices must be selected with care. (This is because through currents will flow at the instant the PWM side transistors turn on if diodes with a short reverse recovery time are not used.) 2. Current Limiter Circuit The current limiter circuit limits the output current peak value to a level determined by the equation I = VFR/Rf (VRF = 0.25V typical, Rf: current detection resistor). This circuit suppresses the output current by reducing To the RF pin Current detection the output on duty. resistor The current limiter circuit includes an internal filter circuit to prevent incorrect current limiter circuit operation due to detecting the output diode reverse recovery current due to PWM operation. Although there should be no problems with the internal filter circuit in normal applications, applications should add an external filter circuit (such as an RC low-pass filter) if incorrect operation occurs (if the diode reverse recovery current flows for longer than 1µs). 3. Notes on the PWM Frequency The PWM frequency is determined by the capacitor C (F) connected to the PWM pin. fPWM ≈ 1/(22500 × C) If a 2000pF capacitor is used, the circuit will oscillate at about 22kHz. If the PWM frequency is too low, switching noise will be audible from the motor, and if it is too high, the output power loss will increase. Thus a frequency in the range 15k to 50kHz must be used. The capacitor's ground terminal must be placed as close as possible to the IC’s ground pin to minimize the influence of output noise and other noise sources. 4. Control Methods The output duty can be controlled by either of the following methods ⋅ Control based on comparing the EI+ pin voltage to the PWM oscillator waveform The low side output transistor duty is determined according to the result of comparing the EI+ pin voltage to the PWM oscillator waveform. When the EI+ pin voltage is 1.35V or lower, the duty will be 0%, and when it is 3.0V or higher, the duty will be 100%. When EI+ pin voltage control is used, a low-level input must be applied to the PWMIN pin or that pin connected to ground. ⋅ Pulse Control Using the PWMIN Pin A pulse signal can be input to the PWMIN pin, and the output can be controlled based on the duty of that signal. Note that the output is on when a low level is input to the PWMIN pin, and off when a high level is input. When the PWMIN pin is open it goes to the high level and the output is turned off. If To the inverted input logic is required, this can be implemented with an external PWMIN pin transistor (npn). When controlling motor operation from the PWMIN pin, the EI+ pin must be connected to the VREG pin. Note that since the PWM oscillator is also used as the clock for internal circuits, Pulse input a capacitor (about 2000pF) must be connected to the PWM pin even if the PWMIN pin is used for motor control. No.A0662-11/11 LB11620T 5. Hall Input Signals A signal input with an amplitude in excess of the hysteresis (80mV maximum) is required for the Hall inputs. Considering the possibility of noise and phase displacement, an even larger amplitude is desirable. If disruptions to the output waveforms (during phase switching) or to the HP output (Hall signal output) occur due to noise, this must be prevented by inserting capacitors across the inputs. The constraint protection circuit uses the Hall inputs to discriminate the motor constraint state. Although the circuit is designed to tolerate a certain amount of noise, care is required when using the constraint protection circuit. If all three phases of the Hall input signal system go to the same input state, the outputs are all set to the off state (the UL, VL, WL, UH, VH, and WH outputs all go to the low level). If the outputs from a Hall IC are used, fixing one side of the inputs (either the + or – side) at a voltage within the common-mode input voltage range allows the other input side to be used as an input over the 0V to VCC range. 6. Under-voltage Protection Circuit The under-voltage protection circuit turns one side of the outputs (UH, VH, and WH) off when the VREG pin voltage falls below the minimum operation voltage (see the Electrical Characteristics). To prevent this circuit from repeatedly turning the outputs on and off in the vicinity of the protection operating voltage, this circuit is designed with hysteresis. Thus the output will not recover until the operating voltage rises 0.5V (typical). 7. Constraint Protection Circuit When the motor is physically constrained (held stopped), the CSD pin external capacitor is charged (to about 3.0 V) by a constant current of about 2.25µA and is then discharged (to about 1.0V) by a constant current of about 0.15µA. This process is repeated, generating a saw-tooth waveform. The constraint protection circuit turns motor drive on and off repeatedly based on this saw-tooth waveform. (The UH, VH, and WH side outputs are turned on and off.) Motor drive is on during the period the CSD pin external capacitor is being charged from about 1.0V to about 3.0V, and motor drive is off during the period the CSD pin external capacitor is being discharged from about 3.0V to about 1.0V. The IC and the motor are protected by this repeated drive on/off operation when the motor is physically constrained. The motor drive on and off times are determined by the value of the connected capacitor C (in µF). TCSD1 (drive on period) ≈ 0.89 × C (seconds) TCSD2 (drive off period) ≈ 13.3 × C (seconds) When a 0.47µF capacitor is connected externally to the CSD pin, this iterated operation will have a drive on period of about 0.4 seconds and a drive off period of about 6.3 seconds. While the motor is turning, the discharge pulse signal (generated once for each Hall input period) that is created by combining the Hall inputs internally in the IC discharges the CSD pin external capacitor. Since the CSD pin voltage does not rise, the constraint protection circuit does not operate. When the motor is physically constrained, the Hall inputs do not change and the discharge pulses are not generated. As a result, the CSD pin external capacitor is charged by a constant current of 2.5µA to about 3.0V, at which point the constraint protection circuit operates. When the constraint on the motor is released, the constraint protection function is released. Connect the CSD pin to ground if the constraint protection circuit is not used. 8. Forward/Reverse Direction Switching This IC is designed so that through currents (due to the output transistor off delay time when switching) do not flow in the output when switching directions when the motor is turning. However, if the direction is switched when the motor is turning, current levels in excess of the current limiter value may flow in the output transistors due to the motor coil resistance and the motor back EMF state when switching. Therefore, designers must consider selecting external output transistors that are not destroyed by those current levels or only switching directions after the speed has fallen below a certain speed. 9. Handling Different Power Supply Types When this IC is operated from an externally supplied 5V power supply (4.5 to 5.5V), short the VCC pin to the VREG pin and connect them to the external power supply. When this IC is operated from an externally supplied 12V power supply (8 to 17 V), connect the VCC pin to the power supply. (The VREG pin will generate a 5V level to function as the control circuit power supply.) No.A0662-12/11 LB11620T 11. Power Supply Stabilization Since this IC uses a switching drive technique, the power supply line level can be disturbed easily. Therefore capacitors with adequate capacitance to stabilize the power supply line must be inserted between VCC and ground. If diodes are inserted in the power supply lines to prevent destruction if the power supply is connected with reverse polarity, the power supply lines are even more easily disrupted, and even larger capacitors are required. If the power supply is turned on and off by a switch, and if there is a significant distance between that switch and the stabilization capacitor, the supply voltage can be disrupted significantly by the line inductance and surge current into the capacitor. As a result, the withstand voltage of the device may be exceeded. In application such as this, the surge current must be suppressed and the voltage rise prevented by not using ceramic capacitors with a low series impedance, and by using electrolytic capacitors instead. 12. VREG Stabilization To stabilize the VREG voltage, which is the control circuit power supply, a 0.1µF or larger capacitor must be inserted between the VREG pin and ground. The ground side of this capacitor must connected to the IC ground pin with a line that is as short as possible. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2008. Specifications and information herein are subject to change without notice. PS No.A0662-13/13