LB11872H

Ordering number : EN7257B Monolithic Digital IC LB11872H Overview For Polygonal Mirror Motors Three-Phase Brushless Motor Driver The LB11872H is a three-phase brushless motor driver developed for driving the motors used for the polygonal mirror in laser printers and similar applications. It can implement, with a single IC chip, all the circuits required for polygonal mirror drive, including speed control and driver functions. The LB11872H can implement motor drive within minimal drive noise due to its use of current linear drive. Features • Three-phase bipolar current linear drive + midpoint control circuit. • PLL speed control circuit. • Speed is controlled by an external clock signal. • Supports Hall FG operation. • Built-in output saturation prevention circuit. • Phase lock detection output (with masking function). • Includes current limiter, thermal protection, rotor constraint protection, and low-voltage protection circuits on chip. • On-chip output diodes. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Output current Allowable power dissipation Symbol VCC max IO max Pd max1 Pd max2 Operating temperature Storage temperature Topr Tstg T ≤ 500ms Independent IC *With specified substrate Conditions Ratings 30 1.2 0.8 2.0 -20 to +80 -55 to +150 Unit V A W W °C °C ∗ When mounted on the specified printed circuit board : 114.3mm × 76.1mm × 1.6mm, glass epoxy Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 82708 MS PC/91002AS (OT) No.7257-1/11 LB11872H Allowable Operating Conditions at Ta = 25°C Parameter Supply voltage range 6.3 V regulator-voltage output current LD pin applied voltage LD pin output current FGS pin applied voltage FGS pin output current Symbol VCC IREG VLD ILD VFG IFG Conditions Ratings 10 to 28 0 to -20 0 to 28 0 to 15 0 to 28 0 to 10 Unit V mA V mA V mA Electrical Characteristics at Ta = 25°C, VCC = VM = 24V Parameter Supply current 1 Supply current 2 Symbol ICC1 ICC2 Stop mode Start mode Conditions min Ratings typ 5 17 max 7 22 mA mA Unit Output saturation voltages VAGC = 3.5V SOURCE (1) SOURCE (2) SINK (1) SINK (2) Output leakage current 6.3V Regulator-voltage output Output voltage Voltage regulation Load regulation Temperature coefficient Hall amplifier block Input bias current Differential input voltage range Common-phase input voltage range Input offset voltage FG amplifier and schmitt block (IN1) Input amplifier gain Input hysteresis (high to low) Input hysteresis (low to high) Hysteresis width Low-voltage protection circuit Operating voltage Hysteresis width Thermal protection circuit Thermal shutdown operating temperature Hysteresis width Current limiter operation Acceleration limit voltage Deceleration limit voltage Error amplifier Input offset voltage Input bias current High-level output voltage Low-level output voltage DC bias level VIO (ER) IB (ER) VOH (ER) VOL (ER) VB (ER) IOH = -500μA IOL = 500μA -5% Design target value*1 -10 -1 VREG-1.2 VREG-0.9 0.9 1/2VREG 1.2 5% 10 1 mV μA V V V VRF1 VRF2 0.53 0.32 0.59 0.37 0.65 0.42 V V ΔTSD Design target value*1 (junction temperature) 40 °C TSD Design target value*1 (junction temperature) 150 180 °C VSD ΔVSD 8.4 0.2 8.8 0.4 9.2 0.6 V V GFG VSHL VSLH VFGL Input conversion 4 5 0 -10 7 12 Times mV mV mV IB (HA) VHIN VICM VIOH Differential input : 50mVp-p SIN wave input Differential input : 50mVp-p Design target value*1 50 2.0 -20 2 10 *600 VCC-2.5 20 μA mVp-p V mV VREG ΔVREG1 ΔVREG2 ΔVREG3 VCC = 9.5 to 28V Iload = -5 to -20mA Design target value*1 5.90 6.25 50 10 0 6.60 100 60 V mV mV mV/°C VSAT1-1 VSAT1-2 VSAT2-1 VSAT2-2 IO (LEAK) IO = 0.5A, RF = 0Ω IO = 1.0A, RF = 0Ω IO = 0.5A, RF = 0Ω IO = 1.0A, RF = 0Ω VCC = 28V 1.7 2.0 0.4 1.0 2.2 2.7 0.9 1.7 100 V V V V μA Note* : Since kickback can occur in the output waveform if the Hall input amplitude is too large, the Hall input. amplitudes should be held to under 350mVp-p. *1 : This parameter is a design target value and is not measured. Continued on next page. No.7257-2/11 LB11872H Continued from preceding page. Parameter Phase comparator output High-level output voltage Low-level output voltage Output source current Output sink current Lock detection output Output saturation voltage Output leakage current FG output Output saturation voltage Output leakage current Drive block Dead zone width Output idling voltage Forward gain 1 Forward gain 2 Reverse gain 1 Reverse gain 2 Acceleration command voltage Deceleration command voltage Forward limiter voltage Reverse limiter voltage CSD oscillator circuit Oscillation frequency High-level pin voltage Low-level pin voltage External capacitor charge and discharge current Lock detection delay count Clock cutoff protection operating count Lock protection count Initial reset voltage Clock input block External input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis width High-level input current Low-level input current S/S pin High-level input voltage Low-level input voltage Input open voltage Hysteresis width High-level input current Low-level input current *1 VIH (S/S) VIL (S/S) VIO (S/S) VIS (S/S) IIH (S/S) IIL (S/S) V (S/S) = VREG V (S/S) = 0V -185 2.0 0 2.7 0.1 3.0 0.2 140 -140 VREG 1.0 3.3 0.3 185 V V V V μA μA fCLK VIH (CLK) VIL (CLK) VIO (CLK) VIS (CLK) IIH (CLK) IIL (CLK) Design target value*1 V (CLK) = VREG V (CLK) = 0V -185 Design target value*1 Design target value*1 400 2.0 0 2.7 0.1 3.0 0.2 140 -140 10000 VREG 1.0 3.3 0.3 185 Hz V V V V μA μA CSDCT3 VRES 31 0.60 0.80 V CSDCT1 CSDCT2 7 2 fOSC VCSDH VCSDL ICHG C = 0.022μF 4.3 0.75 3 31 4.8 1.15 5 5.3 1.55 7 Hz V V μA VDZ VID GDF+1 GDF+2 GDF-1 GDF-2 VSTA VSTO VL1 VL2 Rf = 22Ω Rf = 22Ω 0.53 0.32 With phase locked With phase unlocked With phase locked With phase unlocked 0.4 0.8 -0.6 -0.8 5.0 0.5 1.0 -0.5 -1.0 5.6 0.8 0.59 0.37 1.5 0.65 0.42 With the phase is locked 50 100 300 6 0.6 1.2 -0.4 -1.2 mV mV Times Times Times Times V V V V VFG (SAT) IFG (LEAK) IFG = 5mA VFG = 28V 0.15 0.5 10 V μA VLD (SAT) ILD (LEAK) ILD = 10mA VLD = 28V 0.15 0.5 10 V μA VPDH VPDL IPD+ IPDIOH = -100μA IOL = 100μA VPD = VREG/2 VPD = VREG/2 1.5 VREG-0.2 VREG-0.1 0.2 0.3 -500 V V μA mA Symbol Conditions min Ratings typ max Unit : This parameter is a design target value and is not measured. No.7257-3/11 LB11872H Package Dimensions unit : mm (typ) 3233B 2.4 15.2 (6.2) 28 15 HEAT SPREADER Pd max – Ta Specified board : 114.3×76.1×1.6mm3 glass epoxy Allowable power dissipation, Pd max – W 2.0 1.6 (4.9) 10.5 7.9 1.2 1.12 0.8 0.65 Independent IC 1 0.8 (0.8) 2.0 0.3 14 0.25 0.4 0.45 2.45max (2.25) 0 – 20 0 20 40 60 80 100 Ambient temperature, Ta – °C 2.7 0.1 SANYO : HSOP28H(375mil) Pin Assignment VREG OUT3 OUT2 OUT1 VCC GND SUB CLK 16 28 27 26 25 24 23 22 21 20 19 18 17 15 S/S EO PD RF FC LD EI LB11872H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AGC IN2+ IN2- IN1+ IN1- IN3+ IN3- GND MN NC NC CSD NC NC FG Top view Truth Table OUT1 to OUT3 (H : Source, L : Sink) IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H OUT1 L L M H H M OUT2 H M L L M H OUT3 M H H M L L For IN1 to IN3, “H” means that IN+ is greater than IN-, and “L” means IN- is greater than IN+. For OUT1 to OUT3, “H” means the output is a source, and “L” means that it is a sink. No.7257-4/11 HSOP28H Block Diagram CLK CLK 16 6.3VREG + OSC PD CLOCK DET 15 S/S RESET PLL LOCK DET LD V-AMP 21 FC + LVSD TSD PD 18 EO 20 23 VCC EI 19 Vreg 22 + VCC CSD 12 S/S LD LD 17 LB11872H RESTRICT DET OCL 25 RF FG FILTER + + ×5 FG 14 FG 26 OUT1 OUTPUT 27 OUT2 28 OUT3 MN 9 HALL AMP & MATRIX AGC 4 IN1 5 2 3 IN2 6 7 IN3 8 AGC 24 SUB FRAME GND No.7257-5/11 LB11872H Pin Functions Pin No. 2 3 4 5 6 7 Pin name IN2+ IN2IN1+ IN1IN3+ IN3Function Hall effect sensor signal inputs. These inputs are high when IN+ is greater than IN- and low when IN- is greater than IN+. Insert capacitors between the IN+ and IN– pins to reduce noise. An amplitude of over 50mVp-p and under 350mVp-p is desirable for the Hall input signals. Kickback can occur in the output waveform if the Hall input amplitude is over 350mVp-p. Equivalent circuit VCC 3 5 7 300Ω 300Ω 2 4 6 8 AGC AGC amplifier frequency characteristics correction. Insert a capacitor (about 0.022μF) between this pin and ground. VREG 300Ω 8 9 12 MN CSD Monitor pin. This pin should be left open in normal operation. Used for both initial reset pulse generation and as the reference time for constraint protection circuits. Insert a capacitor between this pin and ground. VREG 300Ω 12 14 FG FG pulse output. This is an open-collector output. VREG 14 15 S/S Start/stop control. Low : Start 0 to 1.0V High : Stop 2.0V to VREG This pin goes to the high level when open. VREG 33kΩ 5kΩ 15 30kΩ Continued on next page. No.7257-6/11 LB11872H Continued from preceding page. Pin No. 16 Pin name CLK Clock input. Low : 0 to 1.0V High : 2.0V to VREG This pin goes to the high level when open. Function Equivalent circuit VREG 33kΩ 5kΩ 16 30kΩ 17 LD Phase locked state detection output. This output goes to the on state when the PLL locked state is detected. This is an open-collector output. VREG 17 18 PD Phase comparator output (PLL output). This pin output the phase error as a pulse signal with varying duty.The output current increases as the duty becomes smaller. VREG 18 19 EI Error amplifier in put pin. VREG 300Ω 19 20 EO Error amplifier output pin. The output current increases when this output is high. VREG 300Ω 40kΩ 20 Continued on next page. No.7257-7/11 LB11872H Continued from preceding page. Pin No. 21 Pin name FC Function Control amplifier frequency correction. Inserting a capacitor (about 5600pF) between this pin and ground will stop closed loop oscillation in the current control system. The output current response characteristics will be degraded if the capacitor is too large. Equivalent circuit VREG 21 22 VREG Stabilized power supply (6.3V) Insert a capacitor (about 0.1μF) between this pin and ground for stabilization. VCC 22 23 24 25 VCC SUB RF Power supply. SUB pin. Connect this pin to ground. Output current detection. Insert low-valued resistors (Rf) between these pins and ground. The output current will be limited to the value set by the equation IOUT = VL/Rf. VCC 26 27 28 OUT1 OUT2 OUT3 Motor drive outputs. If the output oscillates, insert a capacitor (about 0.1μF) between this pin and ground. VREG 26 27 28 300Ω 25 1 10 11 13 FRAME NC No connection (NC) pins. These pins may be used for wiring connections. GND Ground. No.7257-8/11 LB11872H LB11920 Description 1. Speed Control Circuit This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter. This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (rising edges (low to high transitions) on the IN1 input), and the IC uses the detected error to control the motor speed. During this control operation, the FG servo frequency will be the same as the CLK frequency. fFG (servo) = fCLK 2. Output Drive Circuit To minimize motor noise, this IC adopts three-phase full-wave current linear drive. This IC also adopts a midpoint control technique to prevent ASO destruction of the output transistors. Reverse torque braking is used during motor deceleration during speed switching and lock pull-in. In stop mode, the drive is cut and the motor is left in the free-running state. Since the output block may oscillate depending on the motor actually used, capacitors (about 0.1μF) must be inserted between the OUT pins and ground. 3. Hall Input Signals This IC includes an AGC circuit that minimizes the influence on the output of changes in the Hall signal input amplitudes due to the motor used. However, note that if there are discrepancies in the input amplitudes between the individual phases, discrepancies in the output phase switching timing may occur. An amplitude (differential) of at least 50mVp-p is required in the Hall input signals. However, if the input amplitude exceeds 350mVp-p, the AGC circuit control range will be exceeded and kickback may occur in the output. If Hall signal input frequencies in excess of 1kHz (the frequency in a single Hall input phase) are used, internal IC heating during startup and certain other times (that is, when the output transistors are saturated) may increase. Reducing the number of magnetic poles can be effective in dealing with problem. The IN1 Hall signal is used as the FG signal for speed control internally to the IC. Since noise can easily become a problem, a capacitor must be inserted across this input. However, since this could result in differences between the signal amplitudes of the three phases, capacitors must be inserted across all of the three input phases. Although VCC can be used as the Hall element bias power supply, using VREG can reduce the chances of problems occurring during noise testing and at other times. If VREG is used, since there is no longer any need to be concerned with the upper limit of the Hall amplifier common-mode input voltage range, bias setting resistors may be used only on the low side. 4. Power Saving Circuit This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is implemented by removing the bias current from most of the circuits in the IC. However, the 6.3V regulator output is provided in the power saving state. 5. Reference Clock Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor. This IC includes an internal clock cutoff protection circuit. If a signal with a frequency below that given by the formula below is input, the IC will not perform normal control, but rather will operate in intermittent drive mode. f (Hz) ≈ 0.64 ÷ CCSD CCSD (μF) : The capacitor inserted between the CSD pin and ground. When a capacitor of 0.022μF is used, the frequency will be about 29Hz. If the IC is set to the start state when the reference clock signal is completely absent, the motor will turn somewhat and then motor drive will be shut off. After the motor stops and the rotor constraint protection time elapses, drive will not be restarted, even if the clock signal is then reapplied. However, drive will restart if the clock signal is reapplied before the rotor constraint protection time elapses. No.7257-9/11 LB11872H 6. Rotor Constraint Protection Circuit This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is constrained physically, i.e. prevented from turning. If the FG signal (edges of one type (rising or falling edges) on the IN1 signal) does not switch within a fixed time, output drive will be turned off. The time constant is determined by the capacitor connected to the CSD pin. < time constant (in seconds) > ≈ 30.5 × 1.57 × CCSD (μF) If a 0.02μF capacitor is used, the protection time will be about 1.05 seconds. To clear the rotor constraint protection state, the IC must be set to the stopped state or the power must be turned off and reapplied. If there is noise present on the FG signal during the constraint time, the rotor constraint protection circuit may not operate normally. 7. Phase Lock Signal (1) Phase lock range Since this IC does not include a counter or similar functionality in the speed control system, the speed error range in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at startup and when unlocked due to switching clock frequencies. (2) Masking function for the phase lock state signal A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pull-in. However, this results in the lock state signal output being delayed by the masking time. The masking time is determined by the capacitor inserted between the CSD pin and ground. < masking time (seconds) > ≈ 6.5 × 1.57 × CCSD (μF) When a 0.022μF capacitor is used, the masking time will be about 225ms. In cases where complete masking is required, a masking time with fully adequate margin must be used. 8. Initial Reset To initially reset the logic circuits in start mode, the IC goes to the reset state when the CSD pin voltage goes to zero until it reaches 0.63V. Drive output starts after the reset state is cleared. The reset time can be calculated to a good approximation using the following formula. < reset time (seconds) > ≈ 0.13 × CCSD (μF) A reset time of over 100μs is required. 9. Current Limiter Circuit The current limit value is determined by the resistor Rf inserted between the RF pin and ground. ILIM = VL/Rf VL = 0.59V (typical) (during acceleration) and 0.37V (typical) (during deceleration) 10. Power Supply Stabilization An adequately large capacitor must be inserted between the VCC pin and ground for power supply stabilization. If diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be used. If high-frequency noise is a problem, a ceramic capacitor of about 0.1μF must also be inserted in parallel. 11. VREG Stabilization A capacitor of at least 0.1μF must be used to stabilize the VREG voltage, which is the control circuit power supply. The capacitor must be connected as close as possible to the pins. 12. Error Amplifier External Component Values To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC as possible. No.7257-10/11 LB11872H 13. FRAME Pin and Heat sink Area The FRAME pin and the heat sink area function as the control circuit ground terminal. It is desirable that this ground line and the Rf resistor ground line be grounded at a single point at the ground for the electrolytic capacitor. Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC package to the PCB with, for example, a solder with good thermal conductivity. 14. CSD Pin The capacitor connected to the CSD pin influences several operational aspects of this IC, including the rotor constraint protection time and the phase lock signal mask time. The following are possible ways of determining the value of this capacitor. (1) If removing chattering from the phase lock state signal is most important : Select a capacitance that can assure an adequate mask time. (2) If startup time is more important than chattering : Select a capacitance such that the rotor constraint protection circuit does not operate at startup time and verify that there are no problems with the clock cutoff protection circuit and initial reset time. Operation of the rotor constraint protection circuit may hinder the study of motor characteristics in the uncontrolled state. It is possible to only operate the initial reset function and not operate the rotor constraint protection circuit by inserting a resistor (about 390kΩ) in parallel with the capacitor between the CSD pin and ground. 15. FC Pin The capacitor connected to the FC pin is required for current limiter loop phase compensation. If the value is too low, the output will oscillate. If the value is too large, it will be easier for currents in excess of the limit value to flow during the current limit time (time before the circuit operates) in states where the output is saturated. (This is because the control response characteristics become worse.) 16. AGC Pin A capacitance that allows a certain amount of smoothing of the AGC pin voltage in the motor speed range used must be selected for the capacitor connected to the AGC pin. It is also desirable to use a capacitance that allows the AGC voltage to reach an essentially stabilized voltage before the initial reset is cleared. (If the capacitance is too large, the rate of change of the AGC voltage will become slower.) SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2008. Specifications and information herein are subject to change without notice. PS No.7257-11/11