LB11923V

Ordering number : ENN7498 Monolithic Digital IC LB11923V Three-Phase Brushless Motor Driver Overview The LB11923V is a pre-driver IC designed for variablespeed control of 3-phase brushless motors. It can be used to implement a motor drive circuit with the desired output capacity (voltage, current) by using discrete transistors for the output stage. It implements direct PWM drive for minimal power loss. Since the LB11923V includes a builtin VCO circuit, applications can control the motor speed arbitrarily by varying the external clock frequency. Package Dimensions unit: mm 3277-SSOP44 [LB11923V] 15.0 44 23 Features • • • • • • • Direct PWM drive output Speed discriminator + PLL speed control circuit Speed lock detection output Built-in crystal oscillator circuit Forward/reverse switching circuit Braking circuit (short braking) Full complement of on-chip protection circuits, including lock protection, current limiter, and thermal shutdown protection circuits. 1 (0.68) 0.65 0.22 5.6 7.6 22 (1.5) 1.7max 0.2 SANYO: SSOP44 (275 mil) Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Maximum input current Output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max IREG max IO max Pd max1 Pd max2 Topr Tstg VREG pin UH, VH, WH, UL, VL, and WL outputs Independent IC When mounted on the specified PCB (114.3 × 76.1 × 1.6 mm glass epoxy PCB) Conditions Ratings 8 2 30 0.62 1.79 –20 to +80 –55 to +150 Unit V mA mA W W °C °C Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 21604TN (OT) No. 7498-1/19 0.1 0.5 LB11923V Allowable Operating Ranges at Ta = 25°C Parameter Supply voltage Input current range FG Schmitt output applied voltage FG Schmitt output current Lock detection applied voltage Lock detection output current Symbol VCC IREG VFGS IFGS VLD ILD VREG pin (7 V) Conditions Ratings 4.4 to 7.0 0.2 to 1.5 0 to 7 0 to 5 0 to 7 0 to 20 Unit V mA V mA V mA Electrical Characteristics at Ta = 25°C, VCC = 6.3 V Parameter Symbol ICC1 Supply current ICC2 ICC3 ICC4 Output saturation voltage 1-1 Output saturation voltage 1-2 Output saturation voltage 2 [Hall Amplifier] Input bias current Common-mode input voltage range 1 Common-mode input voltage range 2 Hall input sensitivity Hysteresis Input voltage low → high Input voltage high → low [PWM Oscillator] Output high-level voltage 1 Output high-level voltage 2 Output low-level voltage 1 Output low-level voltage 2 Oscillator frequency Amplitude 1 Amplitude 2 [CSD Oscillator] Output high-level voltage 1 Output high-level voltage 2 Output low-level voltage 1 Output low-level voltage 2 External capacitor charge current External capacitor discharge current Oscillator frequency Amplitude 1 Amplitude 2 [VCO Oscillator C pin] Output high-level voltage 1 Output high-level voltage 2 Output low-level voltage 1 Output low-level voltage 2 Oscillator frequency Amplitude 1 Amplitude 2 *Note: Not tested VOH(C)1 VOH(C)2 VOL(C)1 VOL(C)2 f(C) V(C)1 V(C)2 VCC = 5 V 0.3 0.3 0.5 0.5 VCC = 5 V VCC = 5 V 2.10 2.00 1.60 1.55 2.40 2.30 1.90 1.80 2.65 2.55 2.10 2.05 1.0 0.7 0.7 V V V V MHz Vp-p Vp-p VOH(CSD)1 VOH(CSD)2 VCC = 5 V VOL(CSD)1 VOL(CSD)2 VCC = 5 V ICHG1 ICHG2 f(RK) V(RK)1 V(RK)2 VCC = 5 V C = 0.068 µF 2.65 2.1 3.95 3.15 1.1 0.9 –13 8 4.4 3.5 1.4 1.1 –9 12 22 3.0 2.4 3.35 2.65 4.85 3.85 1.7 1.3 –6 16 V V V V µA µA Hz Vp-p Vp-p VOH(PWM)1 VOH(PWM)2 VCC = 5 V VOL(PWM)1 VOL(PWM)2 VCC = 5 V f(PWM) V(PWM)1 V(PWM)2 VCC = 5 V C = 560 pF 1.4 1.1 3.5 2.75 1.8 1.45 3.8 3.0 2.1 1.65 22 1.7 1.35 2.0 1.6 4.1 3.25 2.4 1.9 V V V V kHz Vp-p Vp-p ∆VIN(HA) VSLH VSHL IHB(HA) VICM1 VICM2 When Hall-effect sensors are used When one-side biased inputs are used (Hall-effect IC applications) Sine wave –2 0.5 0 100 25 9 –29 35 17 –18 52 29 –9 –0.1 VCC – 2.0 VCC µA V V mVp-p mV mV mV In stop mode VCC = 5 V VCC = 5 V, In stop mode Conditions Ratings min typ 21 2.3 20 2.1 0.1 0.8 VCC – 1.2 VCC – 0.9 max 29.5 3.3 28 2.9 0.3 1.2 Unit mA mA mA mA V V V VO sat1-1 At low level: IO = 400 µA VO sat1-2 At low level: IO = 10 mA VO sat2 At high level: IO = –20 mA Continued on next page. No. 7498-2/19 LB11923V Continued from preceding page. Parameter [Current Limiter Operation] Limiter [Thermal Shutdown Operation] Thermal shutdown operating temperature Hysteresis [VREG Pin] VREG pin voltage [Low-voltage Protection Circuit] Operating voltage Release voltage Hysteresis [FG Amplifier] Input offset voltage Input bias current Output high-level voltage 1 Output high-level voltage 2 Output low-level voltage 1 Output low-level voltage 2 FG input sensitivity Schmitt amplitude for the next stage Operating frequency range Open-loop gain Reference voltage [FGS Output] Output saturation voltage Output leakage current [Speed Discriminator Output] Output high-level voltage Output low-level voltage [Speed Control PLL Output] Output high-level voltage VOH(P)1 VOH(P)2 VOL(P)1 VOL(P)2 VOL(LD) IL(LD) VCC = 5 V ILD = 10 mA VO = VCC –6.25 VCC = 5 V 4.05 3.25 1.85 1.25 4.30 3.50 2.15 1.60 4.65 3.85 2.45 1.85 V V V V VOH(D) VOL(D) VCC – 1.0 VCC – 0.7 0.8 1.1 V V VO(FGS) IL(FGS) IO(FGS) = 2 mA VO = VCC 0.2 0.4 10 V µA VB(FG) f (FG) = 2 kHz 45 –5% 51 VCC/2 5% VIO(FG) IB(FG) VOH(FG)1 VOH(FG)2 VOL(FG)1 VOL(FG)2 IFGI = –0.1 mA, No load IFGI = –0.1 mA, No load, VCC = 5 V IFGI = 0.1 mA, No load IFGI = 0.1 mA, No load, VCC = 5 V Gain: 100× –10 –1 4.2 3.6 1.3 0.7 3 100 180 250 2 4.6 3.95 1.7 1.05 +10 +1 5.0 4.3 2.1 1.4 mV µA V V V V mV mV kHz dB V VSDL VSDH ∆VSD 3.55 3.85 0.18 3.75 4.03 0.28 4.00 4.25 0.38 V V V VREG I = 500 µA 6.6 7.0 7.4 V TTSD ∆TSD Design target value * Design target value * 150 180 30 °C °C VRF 0.235 0.260 0.285 V Symbol Conditions Ratings min typ max Unit Output low-level voltage [Lock Detection] Output saturation voltage Output leakage current Lock range [Integrator] Input offset voltage Input bias current Output high-level voltage 1 Output high-level voltage 2 Output low-level voltage 1 Output low-level voltage 2 Open-loop gain Gain-bandwidth product Reference voltage [FIL Output] Output source current Output sink current *Note: Not tested 0.25 0.4 10 +6.25 V µA % VIO(INT) IB(INT) VOH(INT)1 IINTI = –0.1 mA, No load VOH(INT)2 IINTI = –0.1 mA, No load, VCC = 5 V VOL(INT)1 IINTI = 0.1 mA, No load VOL(INT)2 IINTI = 0.1 mA, No load, VCC = 5 V Design target value * VB(INT) IOH(FIL) IOL(FIL) –10 –0.4 4.1 3.45 1.2 1.1 45 4.4 3.7 1.4 1.3 51 1.0 –5% VCC/2 –13 12 +10 +0.4 4.7 3.95 1.65 1.5 mV µA V V V V dB MHz 5% V –17 7 –7 17 µA µA Continued on next page. No. 7498-3/19 LB11923V Continued from preceding page. Parameter [S/S Pin] Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level current Input low-level current Pull-up resistance [F/R Pin] Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level current Input low-level current Pull-up resistance [BR Pin] Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level current Input low-level current Pull-up resistance [CLK Pin] Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level current Input low-level current Input frequency Pull-up resistance [N1 Pin] Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level current Input low-level current Pull-up resistance [N2 Pin] Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level current Input low-level current Pull-up resistance *Note: Not tested VIH(N2) VIL(N2) VIO(N2) ∆VIN(N2) IIH(N2) IIL(N2) RU(N2) VCC = 6.3 V, 5 V, design target value * VN2 = VCC VN 2 = 0 V VCC = 6.3 V, 5 V VCC = 6.3 V, 5 V 2.0 0 VCC – 0.5 0.13 –10 –170 37 0.22 0 –118 53.5 70 VCC 1.0 VCC 0.31 +10 V V V V µA µA kΩ VIH(N1) VIL(N1) VIO(N1) ∆VIN(N1) IIH(N1) IIL(N1) RU(N1) VCC = 6.3 V, 5 V, design target value * VN1 = VCC VN 1 = 0 V VCC = 6.3 V, 5 V VCC = 6.3 V, 5 V 2.0 0 VCC – 0.5 0.13 –10 –170 37 0.22 0 –118 53.5 70 VCC 1.0 VCC 0.31 +10 V V V V µA µA kΩ VIH(CLK) VIL(CLK) VIO(CLK) ∆VIN(CLK) VCC = 6.3 V, 5 V, design target value * IIH(CLK) IIL(CLK) f(CLK) RU(CLK) 37 53.5 VCLK = VCC VCLK = 0 V VCC = 6.3 V, 5 V VCC = 6.3 V, 5 V 2.0 0 VCC – 0.5 0.13 –10 –170 0.22 0 –118 3.9 70 VCC 1.0 VCC 0.31 +10 V V V V µA µA kHz kΩ VIH(BR) VIL(BR) VIO(BR) ∆VIN(BR) IIH(BR) IIL(BR) RU(BR) VCC = 6.3 V, 5 V VBR = VCC VBR = 0 V VCC = 6.3 V, 5 V VCC = 6.3 V, 5 V 2.0 0 VCC – 0.5 0.13 –10 –170 37 0.22 0 –118 53.5 70 VCC 1.0 VCC 0.31 +10 V V V V µA µA kΩ VIH(F/R) VIL(F/R) VIO(F/R) ∆VIN(F/R) IIH(F/R) IIL(F/R) RU(F/R) VCC = 6.3 V, 5 V VF/R = VCC VF/R = 0 V VCC = 6.3 V, 5 V VCC = 6.3 V, 5 V 2.0 0 VCC – 0.5 0.13 –10 –170 37 0.22 0 –118 53.5 70 VCC 1.0 VCC 0.31 +10 V V V V µA µA kΩ VIH(S/S) VIL(S/S) VIO(S/S) ∆VIN(S/S) IIH(S/S) IIL(S/S) RU(S/S) VCC = 6.3 V, 5 V VS/S = VCC VS/S = 0 V VCC = 6.3 V, 5 V VCC = 6.3 V, 5 V 2.0 0 VCC – 0.5 0.13 –10 –170 37 0.22 0 –118 53.5 70 VCC 1.0 VCC 0.31 +10 V V V V µA µA kΩ Symbol Conditions Ratings min typ max Unit No. 7498-4/19 LB11923V Pd max – Ta 2.0 Allowable power dissipation, Pdmax – W 1.79 W Mounted on the specified PCB (114.3 × 76.1 × 1.6 mm glass epoxy PCB) 1.5 1.0 1.002 W 0.62 W 0.5 Independent IC 0.347 W 0 –20 0 20 40 60 80 100 Ambient temperature, Ta – °C ILB01550 Pin Assignment RFGND FGOUT FGIN+ 23 22 CSD Top view FGIN– 24 21 C GND2 GND1 VCC1 VCC2 IN1+ IN2+ IN3+ IN1– IN2– IN3– WH WL UH 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 NC 19 FIL VH RF UL VL 25 LB11923V 1 VREG 2 S/S 3 CLK 4 F/R 5 BR 6 N1 7 N2 8 FGS 9 LD 10 DOUT 11 POUT 12 NC 13 INT.REF 14 INT.IN 15 INT.OUT 16 TOC 17 PWM 18 NC 20 R Speed Discriminator Count and VCO Divisor N1 High or open High or open Low Low N2 High or open Low High or open Low Count 1024 1024 256 512 Divisor 1024 512 256 512 fFG = (divisor ÷ count) × fCLK No. 7498-5/19 LB11923V Three-Phase Logic Truth Table (A high (H) input is the state where IN+ > IN–.) F/R=L Item 1 2 3 4 5 6 IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R=H IN2 H H L L L H IN3 L H H H L L Output PWM VH WH WH UH UH VH — UL UL VL VL WL WL S/S Pin High or open Low Stop Start BRK Pin High or open Low Brake Released Pin Functions Pin No. Pin Functions 1 Equivalent circuit VCC1 1 VREG 7-V shunt regulator output VCC1 2 S/S Start/stop control Low: 0 V to 1.0 V High: 2.0 V to VCC Goes high when left open. Low for start. High or open for stop. The hysteresis is about 0.22 V. 50 kΩ 3.5 kΩ 2 VCC1 50 kΩ 3.5 kΩ 3 3 CLK External clock signal input Low: 0 V to 1.0 V High: 2.0 V to VCC Goes high when left open. The hysteresis is about 0.22 V. f = 16 kHz, maximum Continued on next page. No. 7498-6/19 LB11923V Continued from preceding page. Pin No. Pin Functions VCC1 Equivalent circuit 4 F/R Forward/reverse control Low: 0 V to 1.0 V High: 2.0 V to VCC Goes high when left open. Low for forward. High or open for reverse. The hysteresis is about 0.22 V. 50 kΩ 3.5 kΩ 4 VCC1 50 kΩ 3.5 kΩ 5 VCC1 50 kΩ 3.5 kΩ 6 VCC1 50 kΩ 3.5 kΩ 5 BR Brake control (short braking operation) Low: 0 V to 1.0 V High: 2.0 V to VCC Goes high when left open. High or open for brake mode operation. The hysteresis is about 0.22 V. 6 N1 Switches the speed discriminator VCO divisor count. Low: 0 V to 1.0 V High: 2.0 V to VCC Goes high when left open. The hysteresis is about 0.22 V. 7 N2 The speed discriminator count switching. Low: 0 V to 1.0 V High: 2.0 V to VCC Goes high when left open. The hysteresis is about 0.22 V. 7 VCC1 8 8 FGS FG amplifier output (after the Schmitt circuit) This is an open collector output. Continued on next page. No. 7498-7/19 LB11923V Continued from preceding page. Pin No. Pin Functions VCC1 Equivalent circuit 9 9 LD Speed lock detection output This is an open collector output. Goes low when the motor speed is within the speed lock range (±6.25%). VCC1 10 DOUT Speed discriminator output Acceleration → high, deceleration → low 10 VCC1 11 POUT Speed control system PLL output Outputs the phase comparison result for CLK and FG. 11 13 INT REF Integrating amplifier non-inverting input (1/2 VCC potential) VCC1 30 kΩ 500 Ω 13 30 kΩ 14 INT IN Integrating amplifier inverting input 500 Ω 14 VCC1 15 INT OUT Integrating amplifier output (speed control) 40 kΩ 15 Continued on next page. No. 7498-8/19 LB11923V Continued from preceding page. Pin No. Pin Functions Equivalent circuit VCC1 16 TOC Torque command input Normally, this pin is connected to the INT.OUT pin. The PWM duty is increased when the TOC pin voltage falls. Do not apply a voltage that exceeds VCC – 0.5 V to this pin. (An input from a normal operational amplifier is desirable.) 16 300 Ω VCC1 17 PWM PWM oscillator frequency setting. Connect a capacitor between this pin and ground. 7.5 kΩ 300 Ω 17 VCC1 19 FIL VCO PLL filter connection 19 300 Ω VCC1 20 R Sets the value of the charge current from the VCO circuit C pin. Insert a resistor between this pin and ground. 300 Ω 20 Continued on next page. No. 7498-9/19 LB11923V Continued from preceding page. Pin No. Pin Functions VCC1 Equivalent circuit 21 C VCO oscillator connection This pin sets the VCO frequency. Insert a capacitor between this pin and ground. Set the value of the capacitor so that the oscillator frequency does not exceed 1 MHz. 300 Ω 21 VCC1 Reset circuit 22 CSD Sets the operating time of the constrained-rotor protection circuit. Reference signal oscillator used when the clock signal is cut off and to prevent malfunctions. The protection function operating time can be set by connecting a capacitor between this pin and ground. This pin also functions as the logic circuit block power-on reset pin. 300 Ω 22 VCC1 30 kΩ 500 Ω FGOUT 23 24 FGIN+ FGIN– FG amplifier input 23 500 Ω 30 kΩ 500 Ω 24 VCC1 25 FGOUT FG amplifier output This pin is connected to the FG Schmitt comparator circuit internally in the IC. 40 kΩ 25 FG Schmitt comparator VCC1 27 RF GND Output current detection Connect a resistor between this pin and ground. 27 Continued on next page. No. 7498-10/19 LB11923V Continued from preceding page. Pin No. Pin Functions Equivalent circuit VCC1 28 RF Output current detection Connect a resistor between this pin and ground. The output limitation maximum current, IOUT, is set to be 0.26/Rf by this resistor. 28 29 30 GND1 GND2 Control block ground Output block ground VCC2 50 kΩ 31 32 33 34 35 36 UL UH VL VH WL WH Outputs (that are used to drive external transistors). The PWM duty is controlled on the UH, VH, and WH side of these outputs. 31 33 35 32 34 36 37 38 VCC2 VCC1 Output block power supply Control block power supply Short VCC1 to VCC2 and, for stability, insert a capacitor between these pins and ground. VCC1 39 40 41 42 43 44 IN3– IN3+ IN2– IN2+ IN1– IN1+ Hall-effect device inputs. The input is seen as a high-level input when IN+ > IN–, and as a low-level input for the opposite state. If noise on the Hall-effect device signals is a problem, insert capacitors between the corresponding IN+ and IN– inputs. The logic high state indicates that VIN+ > VIN– 40 42 44 500 Ω 500 Ω 39 41 43 12 18 26 NC These are unconnected pins, and can be used for wiring. No. 7498-11/19 LB11923V Sample Application Circuit 1 (P-channel + n-channel, Hall-effect sensor application) 1 S/S CLK F/R BR N1 N2 FGS LD 2 3 4 5 6 7 8 9 VREG S/S CLK F/R BR N1 N2 FGS LD IN1+ 44 IN1– 43 IN2+ 42 IN2– 41 IN3+ 40 IN3– 39 + VCC1 38 VCC2 37 WH 36 WL 35 VH 34 VL 33 UH 32 UL 31 GND2 30 GND1 29 RF 28 RFGND 27 NC 26 FGOUT 25 FGIN– 24 FGIN+ 23 + 24 V 10 DOUT 11 POUT 12 NC 13 INT.REF 14 INT.IN 15 INT.OUT 16 TOC 17 PWM 18 NC 19 FIL 20 R 21 C 22 CSD LB11923V Top view No. 7498-12/19 LB11923V Sample Application Circuit 2 (PNP + NPN, Hall-effect sensor application) 1 VREG S/S CLK F/R BR N1 N2 FGS LD 2 3 4 5 6 7 8 9 S/S CLK F/R BR N1 N2 FGS LD IN1+ 44 IN1– 43 IN2+ 42 IN2– 41 IN3+ 40 IN3– 39 + VCC1 38 VCC2 37 WH 36 WL 35 10 DOUT 11 POUT 12 NC 13 INT.REF 14 INT.IN 15 INT.OUT 16 TOC 17 PWM 18 NC 19 FIL 20 R 21 C 22 CSD LB11923V VH 34 VL 33 UH 32 UL 31 GND2 30 GND1 29 RF 28 RFGND 27 NC 26 FGOUT 25 FGIN– 24 FGIIN+ 23 + 24 V Top view No. 7498-13/19 LB11923V Equivalent Circuit Block Diagram IN2+ IN1+ IN3+ IN2– CSD IN1– IN3– HALL CSD FR F/R OSC HYS AMP LOGIC PRI DRIVER VCC LOGIC BR BR TSD S/S INT OUT S/S COMP WH VH UH WL VL UL TOC RF CURR LIM RFGND – INT IN VCC INT REF POUT + RES 1.3VREF PWM LVSD OSC PWM GND LD LD SPEED SPEED PLL 1/N N2 N2 DOUT DISCRI N1 FG FILTER N1 FGS R VCO PLL VCO C FIL – FGO + CLK VCC VREG FIL – FGIN– + FGIN+ CLK VREG No. 7498-14/19 LB11923V IC Operation Description 1. Speed Control Circuit This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The speed discriminator circuit outputs (This counts a single FG period.) an error signal once every two FG periods. The PLL circuit outputs an error signal once every one FG Period. As compared to the earlier technique in which only a speed discriminator circuit was used, the combination of a speed discriminator and a PLL circuit allows variations in motor speed to be better suppressed when a motor that has large load variations is used. The FG servo frequency (fFG) is determined by the frequency relationship shown below and by the clock signal (fCLK) input to the CCLK pin. fFG = (VCO divisor ÷ speed discriminator count) × fCLK N1 High or open High or open Low Low N2 High or open Low High or open Low Count 1024 1024 256 512 Divisor 1024 512 256 512 Therefore it is possible to implement half-speed control without switching the clock frequency by using combinations of the N1 = high, N2 = low state and other setting states. 2. VCO Circuit The LB11923V includes a built-in VCO circuit to generate the speed discriminator circuit reference signal. The reference signal frequency is given by the following formula. fVCO = fCLK × divisor fVCO: Reference signal frequency fCLK: Externally input clock frequency The range over which the reference signal frequency can be varied is determined by the resistor and capacitor components connected to the R and C pins (pins 20 and 21) and by the VCO loop filter constant (the values of the external components connected to pin 19). Supply voltage When VCC is 5 V When VCC is 6.3 V R (kΩ) 7.5 11 C (pF) 200 200 To acquire the widest possible range, it is better to use 6.3 V than 5 V as the supply voltage. It is also possible to handle an even wider range than is possible with fixed counts by making the speed discriminator count and the VCO divisor switchable. The components connected to the R, C, and FIL pins must be connected with lines to their ground pins (pins 29 and 30) that are as short as possible. 3. Output Drive Circuit To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with which the output is on. The PWM switching is performed on the high side for each phase (UH, VH, and WH). The PWM switching side in the output can be selected to be either the high or low side depending on how the external transistors are connected. 4. Current Limiter Circuit The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.26 V (typical), Rf: current detection resistor). The current limitation operation consists of reducing the output duty to suppress the current. High accuracy detection can be achieved by connecting the RF and RFGND pin lines near the ends of the current detection resistor (Rf). 5. Speed Lock Range The speed lock range is ±6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to the speed error to control the motor speed to be within the lock range. No. 7498-15/19 LB11923V 6. Notes on the PWM Frequency The PWM frequency is determined by the capacitor (F) connected to the PWM pin. When VCC = 6.3 V: fPWM ≈ 1/(82000 × C) When VCC = 5.0 V: fPWM ≈ 1/(66000 × C) A PWM frequency of between 15 and 25 kHz is desirable. If the PWM frequency is too low, the motor may resonate at the PWM frequency during motor control, and if that frequency is in the audible range, that resonation may result in audible noise. If the PWM frequency is too high, the output transistor switching loss will increase. To make the circuit less susceptible to noise, the connected capacitors must be connected to the GND pin (pin 29 and pin 30) with lines that are as short as possible. 7. Hall effect sensor input signals An input amplitude of over 100 mV p-p is desirable in the Hall effect sensor inputs. The closer the input waveform is to a square wave, the lower the required input amplitude. Inversely, a higher input amplitude is required the closer the input waveform is to a triangular wave. Also note that the input DC voltage must be set to be within the commonmode input voltage range. If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those capacitors must be located as close as possible to the input pins. When the Hall inputs for all three phases are in the same state, all the outputs will be in the off state. If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of the Hall effect sensor signal inputs as 0 to VCC level signals if the other side is held fixed at a voltage within the common-mode input voltage range that applies when a Hall effect sensors are used. 8. Forward/Reverse Switching The motor rotation direction can be switched using the F/R pin. However, the following notes must be observed if the motor direction is switched while the motor is turning. • This IC is designed to avoid through currents when switching directions. However, increases in the motor supply voltage (due to instantaneous return of motor current to the power supply) during direction switching may cause problems. The values of the capacitors inserted between power and ground must be increased if this increase is excessive. • If the motor current after direction switching exceeds the current limit value, the PWM drive side outputs will be turned off, but the opposite side output will be in the short-circuit braking state, and a current determined by the motor back EMF voltage and the coil resistance will flow. Applications must be designed so that this current does not exceed the ratings of the output transistors used. (The higher the motor speed at which the direction is switched, the more severe this problem becomes.) 9. Brake Switching The LB11923V provides short-circuit braking implemented by turning the output transistors for the high side for all phases (UH, VH, and WH) on. (The opposite side transistors are turned off for all phases.) Note that the current limiter does not operate during braking. During braking, the duty is set to 100%, regardless of the motor speed. The current that flows in the output transistors during braking is determined by the motor back EMF voltage and the coil resistance. Applications must be designed so that this current does not exceed the ratings of the output transistors used. (The higher the motor speed at which braking is applied, the more severe this problem becomes.) The braking function can be applied and released with the IC in the start state. This means that motor startup and stop control can be performed using the brake pin with the S/S pin held at the low level (the start state). If the startup time becomes excessive, it can be reduced by controlling motor startup and stop with the brake pin rather than with the S/S pin. (Since the IC goes to the power saving state when stopped, enough time for the VCO circuit to stabilize will be required at the beginning of the motor start operation.) 10. Constraint Protection Circuit The LB11923V includes an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. If the LD output remains high (indicating the locked state) for a fixed period in the start state, the upper side (external) transistors are turned off. This time is set by the capacitance of the capacitor attached to the CROCK pin. A time of a few seconds can be set with a capacitance of under 0.1 µF. No. 7498-16/19 LB11923V When VCC = 6.3 V: The set time (in seconds) is 37 × C (µF) When VCC = 5.0 V: The set time (in seconds) is 30 × C (µF) To clear the rotor constrained protection state, the application must either switch to the stop state for a fixed period (about 1 ms or longer) or turn off and reapply power. If the rotor constrained protection circuit is not used, a 220 kΩ resistor and a 1500 pF capacitor must be connected in parallel between the CSD pin and ground. However, in that case, the clock disconnect protection circuit described below will no longer function. Since the CSD pin also functions as the power-on reset pin, if the CSD pin were connected directly to ground, the IC would go to the power-on reset state and motor drive operation would remain off. The power-on reset state is cleared when the CSD pin voltage rises above a level of about 0.64 V. 11. Clock Disconnect Protection Circuit If the clock input goes to the no input state when the IC is in the start state, this protection circuit will operate and turn off the PWM output. If the clock is resupplied before the motor constraint protection circuit operates, the IC will return to the drive state, but if the motor constraint protection circuit does operate, the IC must either be set temporarily (approximately 1 ms or over) to the stop or brake state, or the power must be turned off and reapplied. 12. Low-Voltage Protection Circuit The LB11923V includes a low-voltage protection circuit to protect against incorrect operation when power is first applied or if the power-supply voltage (VCC) falls. The (external) upper side output transistors are turned off if VCC falls under about 3.75 volts, and this function is cleared at about 4.0 volts. 13. Power Supply Stabilization Since this IC is used in applications that draw large output currents, the power-supply line is subject to fluctuations. Therefore, capacitors with capacitances adequate to stabilize the power-supply voltage must be connected between the VCC pin and ground. If diodes are inserted in the power-supply line to prevent IC destruction due to reverse power supply connection, since this makes the power-supply voltage even more subject to fluctuations, even larger capacitors will be required. 14. Ground Lines The signal system ground and the output system ground must be separated and a single ground point must be taken at the connector. Since the output system ground carries large currents, this ground line must be made as short as possible. Output system ground ... Ground for Rf and the output diodes Signal system ground ... Ground for the IC and the IC external components 15. VREG Pin If a motor drive system is formed from a single power supply, the VREG pin (pin 1) can be used to create the powersupply voltage (about 6.3 V) for this IC. The VREG pin is a shunt regulator and generates a voltage of about 7 volts by passing a current through an external resistor. A stable voltage can be generated by setting the current to value in the range 0.2 to 1.5 mA. The external transistors must have current capacities of at least 80 mA (to cover the ICC + Hall bias current + output current requirements) and they must have voltage handling capacities in excess of the motor power-supply voltage. Since the heat generated by these transistor may be a problem, heat sinks may be required depending on the packages used. If the IC power-supply voltage (4.4 to 7.0 V) is provided from an external circuit, apply that voltage directly to the VCC pin(pin 37 and pin 38). In that case, the VREG pin must either be left open or connected to ground. 16. FG Amplifier The FG amplifier is normally implemented as a filter amplifier such as that shown in the application circuits to reject noise. Since a clamp circuit has been added at the FG amplifier output, the output amplitude is clamped at about 3 V p-p, even if the gain is increased. Since a Schmitt comparator is inserted after the FG amplifier, applications must set the gain so that the amplifier output amplitude is at least 250 mV p-p. (It is desirable that the gain be set so that the amplitude is over 0.5 V p-p at the lowest controlled speed to be used.) The capacitor inserted between the FGIN+ pin (pin 23) and ground is required for bias voltage stabilization. To make the connected capacitor as immune from noise as possible, connect this capacitor to the GND pin (pin 29 and pin 30) with a line that is as short as possible. No. 7498-17/19 LB11923V 17. Integrating Amplifier The integrating amplifier integrates the speed error pulses and the phase error pulses and converts them to a speed command voltage. At the same time it also sets the control loop gain and frequency characteristics using external components. The integrating amplifier output (pin 15) is normally connected to the TOC pin (pin 16) using external wiring. In cases where it is necessary to switch the integration constant in an application that uses a wide speed range by isolating the integrating amplifier output and the PWM control circuit, this type of constant switching application can be implemented by adding external operational amplifier, analog switch, and other components. In either case, the basic idea is that the operational amplifier output is connected to the TOC pin. (Note that voltages in excess of VCC – 0.5 V must not be applied to the TOC pin.) 18. FIL Pin External Components The capacitor inserted between the FIL pin and ground is used to suppress ripple on the FIL pin voltage. Therefore, application designers must select a capacitance value that provides fully adequate smoothing of the FIL pin voltage even at the lowest external clock input frequency used. Also, the FIL pin voltage convergence time (the time until the reference signal stabilizes) when the input clock frequency is switched is shortened by connecting a resistor and a capacitor in series between the FIL pin and ground. Therefore, designers must select values for the resistor and capacitor that give the required convergence time. 19. R and C Pin External Components The maximum range over which the reference signal frequency fVCO can be varied when 5 V is used as the VCC supply voltage is about a factor of three. When it is desirable to make this range as wide as possible, since the values of the R pin external resistor (R) and the C pin external capacitor (C) are determined by the maximum value of the reference signal frequency (fVCO1) and the minimum value (VCCL) of the VCC power supply due to unit-to-unit variations, R and C can be determined using the following procedure as a reference. (1) Calculate R1 and C1 using the following formulas and determine values for R and C such that the conditions R ≤ R1 and C ≤ C1 will hold taking the sample-to-sample variations (including other issues such as temperature characteristics) into account. R1 = (VCCL – 2.2 V) / 280 µA C1 = (280 µA / 0.9 V) × (1/fVCO1) × 0.7 (2) The minimum value (fVCO2) for the reference signal frequency that can be set for the R and C values determined in step (1) can be calculated from the following formula if we let R2 and C2 be the smallest values for R and C due to the sample-to-sample variations (including other issues such as temperature characteristics). Therefore, the range over which the reference signal frequency can be set is fVCO1 to fVCO2. fVCO2 = 0.38 / (R2 × C2) (3) The following are the conditions that must be met and the points that require care when determining the values of the external components connected to the R and C pins. 1. The maximum value of the set reference signal frequency must not exceed 1 MHz. 2. The R pin voltage and the FIL pin voltage must be in the range 0.3 V to (VCCL – 2.2 V). (VCCL is the lowest value of the VCC supply voltage given the unit-to-unit variations. VCCL is always greater than or equal to 4.4 V.) However, the lower the R pin voltage, the more susceptible the system will be to ground line noise, and the reference signal frequency may become unstable as a result. Therefore the lower end of the R pin voltage range must not be used if there is much ground line noise in the system. 3. Set the value of the R pin external resistor to a value in the range 6.8 kΩ to 15 kΩ. Also, assure that the R pin current remains under 280 µA. 4. Set the value of the C pin external capacitor to a value in the range 150 pF to 1000 pF. 5. When it is desirable to make the range of the reference signal frequency as wide as possible, set the values of R and C to the largest possible values. (However, those values must be lower than the calculated values R1 and C1.) Use components with the smallest sample-to-sample variations possible. The VCC voltage must be made as much higher than 5 V as possible by, for example, using this IC’s VREG pin (7 V shunt regulator), to acquire the widest possible range for the reference signal frequency. No. 7498-18/19 LB11923V 20. NC pin Since the NC pins are electrically open with respect to the IC itself, they can be used as intermediate connection points for lines in the PCB pattern. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any and all SANYO products described or contained herein fall under strategic products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of Japan, such products must not be exported without obtaining export license from the Ministry of International Trade and Industry in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 2004. Specifications and information herein are subject to change without notice. PS No. 7498-19/19