LB1991V_09

Ordering number : EN5792B Monolithic Digital IC LB1991V Overview Functions For Fan Motor 3-phase Brushless Motor Driver The LB1991V is a 3-phase brushless motor driver IC that is optimal for driving the DC fan motor. • 3-phase full-wave voltage drive technique (120° voltage-linear technique) • Torque ripple correction circuit (overlap correction) • Speed control technique based on motor voltage and current control • Built-in FG comparators • Built-in thermal shutdown circuit Specifications Parameter Absolute Maximum Ratings at Ta = 25°C Symbol VCC1 max VCC2 max VS max Applied output voltage Maximum output current Allowable power dissipation Operating temperature Storage temperature VO max IO max Pd max Topr Tstg Independent IC Conditions Ratings 10 11 11 VS+2 1.0 440 -20 to +75 -55 to +150 Unit V V V V A mW °C °C Maximum supply voltage Allowable Operating Ranges at Ta = 25°C Parameter Supply voltage Symbol VCC1 VCC2 VS Hall input amplitude VHALL Between Hall effect element inputs VCC1 ≤ VCC2 Conditions Ratings 2.7 to 6.0 3.5 to 9.0 Up to VCC2 ±20 to ±80 Unit V V V mVp-p Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 10709 MS/73099TH (OT)/53098RM (OT) No.5792-1/7 LB1991V Electrical Characteristics at Ta = 25°C, VCC1 = 3V, VCC2 = 4.75V, VS = 1.5V Parameter Supply Current VCC1 current drain VCC2 current drain VCC1 quiescent current VCC2 quiescent current VS quiescent current VX1 High side residual voltage Low side residual voltage VX2 High side residual voltage Low side residual voltage Output saturation voltage Overlap High/low overlap difference Hall Amplifiers Input offset voltage Common-mode input voltage range I/O voltage gain Standby Pin High-level voltage Low-level voltage Input current Leakage current FRC Pin High-level voltage Low-level voltage Input current Leakage current VH Hall supply voltage (−) pin voltage FG Comparator Input offset voltage Input bias voltage Input bias current offset Common-mode input voltage range Output high-level voltage Output low-level voltage Voltage gain Output current (sink) Thermal shutdown Operating temperature Temperature hysteresis TSD ∆TSD Design target *1 Design target *1 180 20 °C °C VFGOFF IbFG ∆IbFG VFGCM VFGOH VFGOL VGFG IFGOS At the internal pull-up resistors At the internal pull-up resistors Design target *1 For the output pin low level 100 5 VFGIN+ = VFGIN− = 1.5V VFGIN+ = VFGIN− = 1.5V -3 +3 500 -100 1.2 2.8 0.2 +100 2.5 mV nA nA V V V dB mA VHALL VH(−) IH = 5mA, VH(+) − VH(−) IH = 5mA 0.85 0.81 0.95 0.88 1.05 0.95 V V VFRCH VFRCL IFRCIN IFRCLK VFRC = 3V VFRC = 0V 25 2.5 0.4 30 -30 V V µA µA VSTH VSTL ISTIN ISTLK VSTBY = 3V VSTBY = 0V 25 2.5 0.4 40 -30 V V µA µA VHOFF VHCM VGVH Design target *1 Rangle = 20kΩ Rangle = 20kΩ -5 0.95 25.5 28.5 +5 2.1 31.5 mV V dB VXH2 VXL2 VO(sat) O.L ∆O.L IOUT = 0.5A IOUT = 0.5A IOUT = 0.8A, Sink + Source RL = 39Ω × 3, Rangle = 20kΩ *2 (Average upper side overlap) – (Average lower side overlap) *2 72 -8 80 0.25 0.25 0.40 0.40 1.4 87 +8 V V V % % VXH1 VXL1 IOUT = 0.2A IOUT = 0.2A 0.15 0.15 0.22 0.20 0.29 0.25 V V ICC1 ICC2 ICC1Q ICC2Q ISQ IOUT = 100mA IOUT = 100mA VSTBY = 0V VSTBY = 0V VSTBY = 0V 75 3 7.0 1.5 5 10.0 3.0 100 100 mA mA mA µA µA Symbol Conditions min Ratings typ max Unit *1: Design target values in the conditions column are not tested. *2: The standard for overlap is the value as measured. No.5792-2/7 LB1991V Package Dimensions unit : mm (typ) 3175C 0.5 Pd max -- Ta Allowable power dissipation, Pd max -- W 7.8 24 13 0.44 0.4 0.3 0.264 0.2 5.6 7.6 1 0.65 (0.33) 0.22 12 0.15 0.5 0.1 (1.3) 1.5max 0 -20 0 20 40 60 75 80 100 Ambient temperature, Ta -- °C 0.1 SANYO : SSOP24(275mil) Pin Assignment FGOUT FGIN− FGIN+ STBY WIN2 WIN1 UIN2 UIN1 VIN2 VIN1 GND 13 Top view 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 LB1991V WOUT UOUT VOUT VCC1 VCC2 VH+ VH− RF VS RF FRC Truth Table Source phase → Sink phase U 1 V→W W→V U→W W→U U→V V→U W→V V→W W→U U→W V→U U→V H Hall input V H W L H L H L L H L H L H H L L L H H L L H H H L L H L H L FRC 2 3 4 5 6 Note: The “H” entries in the FRC column indicate a voltage of 2.50V or higher, and the “L” entries indicate a voltage of 0.4V or lower. (When VCC1 is 3V.) At the Hall inputs, for each phase a high-level input is the state where the (+) input is 0.02V or higher than the (−) input. Similarly, a low-level input is the state where the (+) input is 0.02V or lower than the (−) input. ANGLE NC No.5792-3/7 VCC2 2 FRC 14 R5 R5 Block Diagram Forward/ reverse switching 3I Current 0 distribution 3I Power to the hatch blocks is supplied from VCC2. 3 VS UIN1 16 U UIN2 17 B R5 R5 U-V V-W W-U 5 UOUT VIN1 18 V VIN2 19 R5 R5 B 7 VOUT WIN1 20 W WIN2 21 Hall amplifiers ANGLE 12 VS/2 I=O.L×VO1/(1.5×R5) Synthesized signal level shifters Drive signal current generation block Hall input synthesis (matrix) B 9 WOUT 6 RF TSD 8 RF 1 VCC1 1.2V reference voltage and bias startup circuit 15 STBY SBD Bias supply LB1991V 2×R1 VCC2 Upper/lower amplitude limiters SBD R1 R2 VO1 R4 1.5×R5 VS/4 R2 O.L×VO1 VO2 Vx+Vf VO3 VS−Vx−Vf+2α Hall power-supply voltage output circuit R6 VCC1 10 VH+ 11 VH− R1 Vx R3 Vx+α FG amplifier 24 FGOUT SBD +Vf (VS/2)+α Vx+Vf R6 GND 13 VO1= 1 VS+( 1 VS-Vx)= 1 VS-Vx 4 2 4 R3 O.L= R3+R4 VO3= 1 VS+α−(Vx+Vf)+ 1 VS+α=VS−Vx−Vf+2α 2 2 23 22 FGIN+ FGIN− No.5792-4/7 LB1991V Pin Function Pin No. 1 Pin name VCC1 VCC2 VS UOUT VOUT WOUT RF VH+ Pin function Supply voltage for all circuits other than the IC internal output block and the amplitude control block. 2 Supply voltage for the IC internal output control block and the amplitude control block. 3 Motor drive power supply. The voltage applied to this pin must not exceed VCC2. 5 U phase output. 10kΩ 1/2×VS 5kΩ 1/4×VS 5kΩ Equivalent circuit 2 VCC2 3 VS 7 V phase output. Each 5 OUT (7,9) 6 RF (8) 9 W phase output. (These outputs include built-in spark killer diodes.) 6,8 Ground for the output power transistors. 10 Hall element bias voltage supply. A voltage that is typically 0.95V is generated between the VH+ and VH− pins (When IH is 5mA). About 0.9V 1 VCC1 11 VH− 11 VH− About 1.9V 20kΩ 13 GND Ground for circuits other than the output transistor. The RF pin potential is the lowest output transistor potential. 14 FRC Forward/reverse selection. Applications can select motor forward or reverse direction rotation using this pin. (This pin has hysteresis characteristics.) VCC1 VCC1 15 STBY Selects the bias supply for all circuits other than the FG comparators. The bias supply is cut when this pin is set to the low level. FRC 14 50kΩ 100kΩ STBY 15 20kΩ 10 VH+ 100kΩ 100kΩ 16 17 UIN1 UIN2 VIN1 VIN2 WIN1 WIN2 ANGLE FGIN+ U phase Hall element input. The logic high level is the state where the IN+ voltage is greater than the IN− voltage. V phase Hall element input. The logic high level is the state where the IN+ voltage is greater than the IN− voltage. 1.2V typ 200Ω 1 VCC1 0.3V 18 19 4kΩ VCC1 4kΩ 200Ω (18,20) Each 16 input of 1 17 Each input of 2 20 21 W phase Hall element input. The logic high level is the state where the IN+ voltage is greater than the IN− voltage. Hall input/output gain control. The gain is controlled by the resistor connected between this pin and ground. 400Ω 400Ω 200Ω (19,21) ANGLE 17 12 22 FG comparator non-inverting inputs. There is no internally applied bias. 15kΩ 20kΩ VCC1 1 23 FGIN− FG comparator inverting inputs. There is no internally applied bias. FGIN− 23 200Ω 200Ω FGIN+ 22 50kΩ FGOUTN 24 24 FGOUT FG comparator outputs. There is an internal 20kΩ resistor load. No.5792-5/7 LB1991V Overlap Generation and Calculation Method VS VS−VXH Vα Absolute voltage Upper side residual voltage VXH Upper side clamp potential VS Electrical A angle B VS−VXH VS O.L × ( 2 −VXH) VS − 2 VXH 180° Calculated center point VN C D Vβ VXL 0 Lower side clamp potential Lower side residual voltage VXL VXL Time Overlap Generation Since the voltage generated in the amplitude control block is, taking the center point as the reference, 2 × × (1/2 VS − VX) on one side, the intersection point of the waveform will be × (1/2 VS − VX) from the center point. To clamp that waveform at (1/2 VS − VX) referenced to the center point the overlap must be: A/B × 100 = × 100 (%). Overlap Calculation • Upper side overlap (VS − VXH − VXL) (VS − VXH + VXL) + VXL = 2 2 Since A = Vα − VN, B = VS − VXH − VN, the upper side overlap will be: Vα − ((VS − VXH + VXL)/2) A = B = ×100 VS − VXH − ((VS − VXH + VXL)/2) Calculated center point: VN = 2Vα − (VS − VXH) − VXL ×100(%) (VS − VXH) − VXL Which can be calculated as: = • Lower side overlap Since C = VN − Vβ, and D = VN − VXL, the lower side overlap will be: ((VS − VXH + VXL)/2) − Vβ C = D = ×100 ((VS − VXH + VXL)/2) − VXL Which can be calculated as: = (VS − VXH) + VXL − 2Vβ ×100(%) (VS − VXH) − VXL No.5792-6/7 LB1991V Test Circuit ±15V 1kΩ 1µF 100kΩ 3 SV 2 1 3 2 1 SO SP SN 3 2 1 3 21 SM SL SK SJ 1 100kΩ 3 2 1 3 2 1 VH3 VH1 VH2 LA6358 VIN f=1kHz −50dBm A Im6 SW 2 1kΩ 100kΩ 1kΩ 1 2 SR 0.1µF SQ A Im7 A Im5 A Im4 VFRC VSTBY SU 3 213 1 2 VFG1 1 2 ST Vm4 V SS IOUT3 5mA VFG2 1 LB1991V 2 SA VCC1 3V VCC2 4.75V Im3 VS 1.5V Im1 A SB SH SC 1 2 V A A SD 39Ω × 3 IOUT2 4mA 2 Vm3 S1 1 20kΩ Im2 The following hold unless otherwise specified: Vm1 V 123 SE 123 SF VCC1=3V VCC2=4.75V VS =1.5V VH1=1.4V VH2=4.75V VH3=1.5V VFRC=3V VSTBY=3V VFG1=VFG2=1.5V Switch status: 0 : CLOSED X : OPEN IOUT1 100mA 200mA 500mA 800mA SG V V Vm5 Vm2 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2009. Specifications and information herein are subject to change without notice. PS No.5792-7/7