Ordering number : ENA1928A
CMOS LSI
LC01707PLF
Overview
FM multiple tuner IC
LC01707PLF is a vehicle-mounted FM multiple tuner IC with FM-FE, IF, IF-Filter, PLL, FM-DEMO and LPF incorporated. An FM multiple tuner can be developed with this one chip. It makes up a small-sized FM multiple tuners which can be mounted on PND.
Functions
• It is the FM tuner IC exclusively for the FM multiple. • LNA is incorporated • Image reduction complex BPF is incorporated • Wide / Narrow Band RF AGC is incorporated • Narrow Band IF AGC is incorporated • Image rejection is adopted • DLL detection method is adopted for the FM detection circuit, and it is not necessary to adjust. • LPF for the carrier removal is incorporated. • IC requires fewer external components. • It is a BUS control tuner IC which can be controlled by controlled by I2C BUS.
Specifications
Parameter Supply voltage Maximum input voltage
Maximum Ratings at Ta = 25°C
Symbol VDD max VDD H VDD L Pd max Topr Tstg Tj max Ta = 85°C *1 Conditions Ratings 4.3 4.3 4.3 700 -40 to 85 -55 to 150 150 Unit V V V mW °C °C °C
Maximum output voltage Power dissipation Operating ambient Storage temperature Maximum junction temperature
*1: Board size: 80mm × 70mm × 1.6mm Glass epoxy double-sided board
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment.
O1911 SY/81011 SY 20110210-S00002 No.A1928-1/18
LC01707PLF
Recommended Operating Conditions at Ta = 25°C
Parameter Supply voltage range Recommended supply temperature Symbol VDD VDD Conditions Ratings 3.0 to 3.6 3.3 Unit V V
Electrical Characteristics at Ta = 25°C, VDD = 3.3V, fc = 83MHz, VIN=60dBμVEMF, fm=1kHz, Audio filter: HPF=100Hz, LPF=15kHz Resister setting: IF AGC (02h) =6(110), RF AGC (00h) =0(0000) DLL demodulator loop gain setting (09h) =1(01), Mono multi center setting (09h) =7(0111)
Ratings Parameter Practical sensitivity 1 (S/N30dB) Practical sensitivity 2 (S/N10dB) S/N1 S/N2 Total harmonic distortion rate 1 Total harmonic distortion rate 2 AM suppression ratio Image rejection ratio Audio output level 1 Audio output level 2 Consumption current Symbol SN30 SN10 SN1 SN2 THD_1 THD_2 AMR IMR AD01 AD02 IDD Conditions min 22.5kHz dev, fm=1kHz, S/N=30dB input level 7.5kHz dev, fm=76kHz, S/N=10dB input level *1 22.5kHz dev, fm=1kHz 7.5kHz dev, fm=76kHz *1 22.5kHz dev, fm=1kHz 75.0kHz dev, fm=1kHz AM 30% mod 22.5k\Hz dev, fm=1kHz 7.5kHz dev, fm=1kHz *1 7.5kHz dev, fm=76kHz *1 No signal input 26 15 34 34 44 21 0.5 0.5 44 32 39 23 106 70 41 170 dB dB % % dB dB mVrms mVrms mA typ 12 27 max 20 dBμEMF dBμEMF Unit
*1: Audio filter: HPF=100Hz, LPF=OFF
Package Dimensions
unit : mm (typ) 3408
TOP VIEW 6.0 SIDE VIEW BOTTOM VIEW
(4.0)
6.0 (4.0) 0.5
12 0.16 SIDE VIEW
(0.8) 0.85 MAX
21 0.4 (1.0)
0.0 NOM
SANYO : VQFN44K(6.0X6.0)
44
No.A1928-2/18
LC01707PLF
Example of applied circuit (constant is tentative)
0.022 F 0.68 F
Decoder
DEMCO 56pF 220pF LPFI
DEMCO 0.22 F
NC
NC
39
37
38
36
35
43
41
44
42
40
34
SMETER
GND
LPFO
VDD
NC
NC
NAGC 0.22 F WAGC 10nF VSS
1 2 3 W_AGC
Freq.Count
33
+
VDD 0.022 F
LIM
DEMO
LPF 32 I/F 31 30
SDA
SCL
N_AGC
INT
NC VDD
4 5 6 7 8 9 DIV 10 11
13 15 12 14 16
NC 22 F 0.68 F VDD 0.022 F LNA_P
MIX I
IF AGC IF AGC
Complex BPF f0:1.2MHz
MIX I
f0:600kHz
29 28
NC
COM
17
19
18
20
21
CP
VSS
VSS
NC
NC
VDD
VDD
2.7nH
10pF
* Culprits oscillation circuit is used in this IC as a crystal oscillation circuit. Caution is required for layout of the board because oscillation between pin25 and power source and GND line. * The margin of crystal oscillation changes due to the combination of the IC, a crystal oscillator and a board layout. This independent IC does not quarantine the oscillation operation. * This IC uses the signal of FM band frequency (VCO divided into 1/4) which leaks into ANT pin. If the VCO leakage affects the performance of the system, make sure to connect an isolator on ANT pin path.
Component L1/L2 L3 X1
Parameter Local OSC coil Differential input coil Crystal
100pF
0.022 F
0.022 F
Value 2.7nH 120nH 7.2MHz
Type C2012H-2N7D-RD C2012H-R12G-RC SMD-49 AT-49 EXS00A-A01145 EXS00A-A01146
2.7nH
NC
Supplier SAGAMI SAGAMI KDS KDS NDK NDK
NC
22
+
BPF
NC
MIX Q
Complex BPF
MIX Q
1.8MHz
DIV LNA injection LOCK DET PD CP REF COUNT PROG COUNT
Freq.Count
27 26 X_TAL 25 24 23
NC
100pF 120nH
27pF VSS 47pF LNA_N
SD 18pF 7.2MHz VSS DEVAR
XTAL
NC
NC
C BANK
No.A1928-3/18
LC01707PLF
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin name NAGC WAGC VSS NC NC VDD LNA_A VSS LNA_N NC NC VSS CP VDD VDD LO_1 VSS LO_2 NC NC NC NC DEVER VSS XTAL SD NC NC NC INT SCL SDA VDD SMETER VDD LPFO DEMOO LPFI DEMOC NC NC NC NC GND I/O O O P P I P I P O P P O P O I P I O O I I P O P O O I O P GND pin Test pin Serial data clock input serial data input-output Supply pin for PLL and logic S-meter output Supply pin for IF Demodulation output (after band limitation) Demodulation output Demodulation signal input pin Capacitance connecting pin for demodulation detection Device address setting pin GND pin for PLL and logic Crystal resonator connecting pin (Clock input pin) Station detector pin GND pin for 1st Mixer PLL charge pump capacitance connecting pin Supply pin 1st Mixer Supply pin for local oscillation Inductor connecting pin for local oscillation GND pin for local oscillation Inductor connecting pin for local oscillation Supply pin for LNA LNA +input pin GND pin for LNA LNA –input pin Function Narrow band AGC detection capacitance connecting pin Wide band AGC detection capacitance connecting pin GND pin for IF
No.A1928-4/18
LC01707PLF
Pin Function
Pin No. Pin name 1 NAGC Function Narrow band AGC detection capacitor connection pin. Equivalent circuit
VDD VDD
1
2
WAGC
Wide band AGC detection capacitor connection pin.
VDD VDD
2
3 4 5 6 7 8 9
VSS NC NC VDD LNA_P VSS LNA_N
GND pin for IF. No connection. No connection. Supply pin for LNA. Pin 7 is + input pin for LNA. Pin 8 is GND pin for LNA. Pin 9 is - input pin for LNA.
VDD VDD
VDD
7 9
10 11 12 13
NC NC VSS CP
No connection. No connection. GND pin 1st mixer for the 1st mixer. PLL charge pump capacitor connection pin.
VDD
VDD
VDD
13
14 15
VDD VDD
Supply pin for the 1st mixer. Supply pin for local oscillator.
Continued on next page.
No.A1928-5/18
LC01707PLF
Continued from preceding page.
Pin No. Pin name 16 17 18 LO_1 VSS LO_2 Function Pin 16 is inductor connection pin for local oscillator. Pin 17 is GND pin for local oscillator. Pin 18 is inductor connection pin for local
Cap Bank
Equivalent circuit
16 VDD
17
18 VDD
oscillator.
Cap Bank
To Pin13
19 20 21 22 23
NC NC NC NC DEVAR
No connection. No connection. No connection. No connection. Device address setting pin.
VDD
VDD
23
24 25
VSS XTAL
PLL_logic GND pin. Crystal oscillator connection pin (clock input pin).
VDD VDD
25 20pF 10pF
5pF
26 30
SD INT
Station detector pin. Test monitor pin.
VDD
VDD
30 26
27 28 29
NC NC NC
No connection. No connection. No connection.
Continued on next page.
No.A1928-6/18
LC01707PLF
Continued from preceding page.
Pin No. Pin name 31 SCL Function Serial data clock input. Equivalent circuit
VDD
31
VDD
32
SDA
Serial data input/ output.
VDD 32
33 34
VDD SMETER
PLL_logic supply voltage pin. S-meter output.
VDD VDD
34
35 36
VDD LPFO
IF supply voltage pin Demodulator output (After band limit).
VDD VDD 4pF 36
37
DEMOO
Demodulator output.
VDD VDD
20.4pF
37 1pF
38
LPFI
Demodulator signal input pin.
VDD + -
38
1pF
Continued on next page.
No.A1928-7/18
LC01707PLF
Continued from preceding page.
Pin No. Pin name 39 DEMOC Function Capacitor connection pin for demodulator detection. Equivalent circuit
39
VDD VDD
40 41 42 43 44
NC NC NC NC GND
No connection. No connection. No connection. No connection. GND pin.
VSS VSS VSS VSS VSS
(Pin_3)
(Pin_8)
44
(Pin_12)
(Pin_17)
(Pin_24)
No.A1928-8/18
LC01707PLF
Communication specification
Communication specifications are indicated as below: Serial Interface (I2C-bus); Sending and receiving data through I2C-bus that consists of two bus lines of a serial data line (SDA) and a serial clock line (SCL). This bus enables 8-bit bi-directional serial data to transmit at the maximum speed of 400kbits (fast mode). This is not compatible with Hs mode. Terms used in I2C The following terms are used in I2C
Terms Transmitter Receiver Master Slave Device to send data to the bus Device to receive from the bus Device to start data transmission, generate signal, and terminate data transmission Device of which address is designated master Description
[Start] and [Stop] conditions [Start] condition is required at the start of data communication and [Stop] condition at the end of data communication. The condition in which the SDA line changes from [H] to [L] with SCL at [H] is called the [Start] condition. The condition in which the SDA line changes from [L] to [H] with SCL at [H] is called the [Start] condition.
SDA
SDA
SCL
S
P
SCL
START condition
STOP condition
Data transmission The length of each byte which is output to SDA line is always 8 bits. An acknowledge bit is needed after each byte. Data is transmitted sequentially from the most significant bit (MSB). During the data transfer, the slave address is transmitted after the [Start] condition (S). Data transfer is always ended by the [Stop] condition (P) generated by the master.
ACK:acknowledgement
ACK signal from slave
ACK signal from receiver P
SDA
D7 MSB
D6
D1
D0 Sr Byte complate, interrupt within slave Clock line held low while interrrupts are serviced
SCL
S or Sr
1
2
7
8
9
1
2
3-8
9
Sr or P
Clock pulse for ACK START or repeated START condition
Clock pulse for ACK STOP or repeated START condition
No.A1928-9/18
LC01707PLF
Acknowledge (Receive acknowledge) When the master generates the acknowledge clock pulse, the transmitter opens the SDA line. (SDA line enters the [H] state.) When the acknowledge clock pulse is in the [H] state, the receiver sets the SDA line to [L] each time it receives one byte (eight bits) data. When the master works as a receiver, the master informs the slave of the end of data by omitting acknowledge at the end of data sent from the slave.
Release the SDA line(HIGH) Data output by transmitter
NACK(master is receiver) Data output by receiver ACK(master is transmitter)
SCL from master S START condition
1
2 ACK:acknowledgement NACK:not acknowledgement
8
9
Clock pulse for ACK
Software reset If the communication is interrupted (microcomputer reset, etc.), it is possible to communicate normally by entering the below signals and resetting the CPU in software. *These signal timings restore the communication after its interruption. The register setting is never reset. *Software reset command is incompatible with I2C-bus format.
SDA
SCL S START condition
1
2
7
8
9
Sr
P STOP cindition
Repeated START condition
No.A1928-10/18
LC01707PLF
Electrical specification and timing for I/O stages
t1
t2
SD
t4
t2
t7
t1
t9
SC
t10 t5 t6 t3 t8
START condition
STOP condition
Bus line characteristics
Characteristic Symbol min SCL clock frequency Fall time of SDA and SCL Rise time of SDA and SCL SCL “H” time SCL “L” time [Start] condition holding time Data holding time for I2C bus device Data setup time [Stop] condition setup time Bus free time between [Stop] and [Start] [Start] condition setup time Bus line capacitive load fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Cb 20+0.1Cb 20+0.1Cb 0.6 1.3 0.6 0.3 0.1 0.6 1.3 0.6 400 FAST-MODE max 400 300 300 kHz ns ns μs μs μs μs μs μs μs μs pF 3 10 20 3 7 10 unit Example at SCL = 100kHz 100
Serial interface voltage level
Characteristic High level input voltage Low level input voltage High level output voltage (open drain) Low level output voltage (open drain)
VDD: Communication bus voltage
min 0.7VDD 0.0 VDD *2 0.0 0.2VDD max VDD 0.3VDD unit V V V V
*2: Output impedance of open drain becomes high at the high level output voltage. Output voltage equals to VDD (voltage =VDD) since drain is pulled up to VDD.
No.A1928-11/18
LC01707PLF
Definition of each bit 1) Slave address The slave address consists of seven-bit fixed address "1110000" or "1110001", which is unique to a chip, and the eighth-bit data direction bit(R/W). Sending (writing) is processed when the data direction bit is"0", and receiving (reading) is processed when it is "1". The fixed address is set to "1110001" at DEVAR=1 and it is set to "1110000" at DEVAR=0.
MSB 1 1 1 0 0 0 1/0
LSB R/W
R/W BIT 1 0 READ WRITE
Fixed address
2) Register address Since the total number of internal register is 34, 2-bit data set on the MSB side becomes invalid. 64 addresses are accepted 6 bits are used, but only 34 registers are used.
MSB 0 0 A5 A4 A3 A2 A1
LSB A0
Invakid address
Valid address
3) Register data Each register data consists of eight bits.
D7 MSB
D6
D5
D4
D3
D2
D1
D0 LSB
No.A1928-12/18
LC01707PLF
Command Format 1) Individual registers data writing
Write Invalid address
SDA
S
1
1
1
0
0
0
1/0
0
0
0
0
1/0
1/0
1/0
1/0
1/0
1/0
0
START condition
Slave address
ACK
Register address
ACK
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
0
P
Register data From master to slave
ACK STOP condition From slave to master
2) Individual registers data reading
Write
Invalid address
SDA
S
1
1
1
0
0
0
1/0
0
0
0
0
1/0
1/0
1/0
1/0
1/0
1/0
0
START condition
Slave address
ACK
Register address
ACK
Read
Sr
1
1
1
0
0
0
1/0
1
0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1
P
Repeated START condition
Slave address From master to slave
ACK From slave to master
Register data
NACK STOP condition
No.A1928-13/18
LC01707PLF
Register Map 1
* HEX value is set by default.
Register address 00h BIT 7 6 5 4 3 2 1 0 01h 7 6 5 4 3 2 1 0 02h 7 6 5 4 3 2 1 0 03h 7 6 5 4 3 2 1 0 04h 7 6 5 4 3 2 1 0 05h 7 6 5 4 3 2 1 0 06h 7 6 5 4 3 2 1 0 07h 7 6 5 4 3 2 1 0 DNBAGC DWBAGC DF0OSC[7] DF0OSC[6] DF0OSC[5] DF0OSC[4] DF0OSC[3] DF0OSC[2] DF0OSC[1] DF0OSC[0] DBPFO[7] DBPFO[6] DBPFO[5] DBPFO[4] DBPFO[3] DBPFO[2] DBPFO[1] DBPFO[0] Capacitor bank value Complex BPF F0 adjustment IF AGC detection selector (Narrow band AGC) RF AGC detection selector (Wide band AGC) Capacitor band value Oscillation frequency adjustment for master time constant setting 1:ON 0:OFF 1:ON 0:OFF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W IMSD_SL[1] IMSD_SL[0] CLKIN DLOCKSEL DFSEL[1] DFSEL[0] ENPE DNGA[2] DNGA[1] DNGA[0] ENCPLEVEL DENPRO DENPD DENCP DENREF DENXTAL DEBDEMO ENFST DENLEVELDET ENRFMIX ENIFLPF ENDET ENLNA DENSMETER DLOEN DENPLL Charge pump level comparison selection Program counter enable Phase comparison enable Charge pump enable S-meter enable XTAL enable Demodulator enable Complex BPF block, IF AGC block enable Capacitor bank control circuit enable RFMIX enable IF LPF enable Wide band AGC, Narrow band AGC block enable LNA block enable Reference counter enable Local oscillation enable PLL block enable Entire circuit enable Narrow band AGC level setting 1:ON 0:OFF (Entire circuit OFF) 0:35mVp-p 1:111mVp-p 2:187mVp-p 3:263mVp-p 4:339mVp-p 5:415mVp-p 6:491mVp-p 7:567mVp-p (When the setting value is ether 0 or 1 and MSK=4%, error is detected in BER.) 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF XTAL current setting LOCKDET output waveform selection Phase comparison frequency selection 1:Normal 0:Twice 1:Number of comparing 6 0:Munber of comparing 3 0:100kHz 1:50kHz 2:50kHz 3:25kHz R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Unused SD_SL[2] SD_SL[1] SD_SL[0] DWAG[3] DWAG[2] DWAG[1] DWAG[0] Wide band AGC level setting 0:15.6mVp-p 1:31.3mVp-p 2:46.9mVp-p 3:62.5mVp-p 4:78.1mVp-p 5:93.8mVp-p 6:109.4mVp-p 7:125.0mVp-p 8:140.6mVp-p 9:156.3mVp-p 10:171.9mVp-p 11:187.5mVp-p 12:203.1mVp-p 13:218.8mVp-p 14:234.4mVp-p 15:250mVp-p SD level detection setting 0:DRS0 1:DRS1 2:DRS2 3:DRS3 4:DRS4 5:DRS5 6:DRS6 7:DRS7 R/W R/W R/W R/W R/W R/W R/W Bit name Function Bit operation
: Unused BIT
Read/ Write Binary value 0 0 0 0 h’00 0 0 0 0 0 0 0 0 h’00 0 0 0 0 1 0 0 1 h’99 1 0 0 1 1 1 1 1 h’FF 1 1 1 1 0 1 1 1 h’7F 1 1 1 1 0 0 0 0 h’03 0 0 1 1 1 0 0 0 h’80 0 0 0 0 1 0 0 0 h’80 0 0 0 0 Hex value
No.A1928-14/18
LC01707PLF
Register Map 2
* HEX value is set by default.
Register address 08h BIT 7 6 5 4 3 2 1 0 09h 7 6 5 4 3 2 1 0 0Ah 7 6 5 4 3 2 1 0 0Bh 7 6 5 4 3 2 1 0 0Ch 7 6 5 4 3 2 1 0 0Dh 7 6 5 4 3 2 1 0 0Eh 7 6 5 4 3 2 1 0 0Fh 7 6 5 4 3 2 1 0 DCP1REF[3] DCP1REF[2] DCP1REF[1] DCP1REF[0] DPCNT_L[7] DPCNT_L[6] DPCNT_L[5] DPCNT_L[4] DPCNT_L[3] DPCNT_L[2] DPCNT_L[1] DPCNT_L[0] DPCNT_H[7] DPCNT_H[6] DPCNT_H[5] DPCNT_H[4] DPCNT_H[3] DPCNT_H[2] DPCNT_H[1] DPCNT_H[0] DCBANK_L[7] DCBANK_L[6] DCBANK_L[5] DCBANK_L[4] DCBANK_L[3] DCBANK_L[2] DCBANK_L[1] DCBANK_L[0] Local oscillator capacitor bank setting (low 8 bits) N value of frequency divider (high 8 bits) N value of frequency divider (low 8 bits) N value of frequency divider = st ((4 × received frequency)±(4 × 1 IF frequency)) / (4 channel × step frequency) st * 1 IF frequency is 1.2MHz Charge pump output current value setting 0:0.1mA 1:0.2mA 2:0.3mA 3:0.4mA 4:0.5mA 5:0.6mA 6:0.7mA 7:0.8mA 8:0.9mA A:1mA E: unused F: unused B:1.1mA C:1.2mA D: unused R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DBL[6] DBL[5] DBL[4] DBL[3] DBL[2] DBL[1] DBL[0] IQ balance adjustment R/W R/W R/W R/W R/W R/W R/W ENIMRSSI DIQC XTAL OSC FET size setting Complex BPF injection changeover 1:Normal 0:Twice 1:lower 0:upper R/W R/W DDEMOG[1] DDEMOG[0] DMONOC[3] DMONOC[2] DMONOC[1] DMONOC[0] Mono multi center setting DLL demodulator loop gain setting R/W R/W R/W R/W R/W R/W Bit name D2BPF[7] D2BPF[6] D2BPF[5] D2BPF[4] D2BPF[3] D2BPF[2] D2BPF[1] D2BPF[0] Function Capacitor bank value nd 2 IF BPF f0 adjustment Bit operation
: Unused BIT
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W Binary value 1 0 0 0 h’80 0 0 0 0 0 0 0 1 h’17 0 1 1 1 0 0 0 0 h’02 0 0 1 0 0 1 0 0 h’40 0 0 0 0 0 0 0 0 h’0A 1 0 1 0 * * * * h’** * * * * * * * * h’** * * * * 0 0 0 0 h’00 0 0 0 0 Hex value
No.A1928-15/18
LC01707PLF
Register Map 3
* HEX value is set by default.
Register address 10h BIT 7 6 5 4 3 2 1 0 11h 7 6 5 4 3 2 1 0 12h 7 6 5 4 3 2 1 0 13h 7 6 5 4 3 2 1 0 14h 7 6 5 4 3 2 1 0 15h 7 6 5 4 3 2 1 0 16h 7 6 5 4 3 2 1 0 17h 7 6 5 4 3 2 1 0 IMRSSI[3] IMRSSI[2] IMRSSI[1] IMRSSI[0] Reset detection circuit 0:reset 1:reset cancellation R R R R COUNTSEL LOCKDETSEL LOCKDET_DIG LOCKDET PHLEVEL[1] PHLEVEL[0] LOCK detection Charge pump voltage level detection 1:LOCK 0:UNLOCK 0:less than 0.5V 1:0.5V to 2.8V 2:Unused 3:more than 2.8V R/W R/W R/W CTE GT[1] GT[0] LOFQ_L[7] LOFQ_L[6] LOFQ_L[5] LOFQ_L[4] LOFQ_L[3] LOFQ_L[2] LOFQ_L[1] LOFQ_L[0] LOFQ_H[7] LOFQ_H[6] LOFQ_H[5] LOFQ_H[4] LOFQ_H[3] LOFQ_H[2] LOFQ_H[1] LOFQ_H[0] LO_COUNT value (upper 8 bits) LO_COUNT value (low 8 bits) Measurement frequency = counter value / GT[ms] Counter start trigger Frequency counter gate time selection 1:ON (frequency counter start) Charge to 0 automatically 0:4ms 1:8ms 2:32ms 3:64ms R/W R/W R/W R R R R R R R R R R R R R R R R DSCTCOUNT[2] DSCTCOUNT[1] DSCTCOUNT[0] Count frequency selection 0:unused 1:IF frequency 2:prescaler frequency 3:freacaler frequency 4:f0 detection oscillation frequency 5:f0 detection oscillation frequency 6:unused 7:IF frequency R/W R/W R/W DENIFCOUNT DENF0OSC DENIFFREQ Frequency counter (analog block) enable f0 detection oscillation circuit enable Logic part reference clock enable 1:ON 0:OFF 1:ON 0:OFF 1:ON 0:OFF R/W R/W R/W DCBEN DLOALC[3] DLOALC[2] DLOALC[1] DLOALC[0] Unused Local oscillation level setting R/W R/W R/W R/W DCBANK_H[8] Local oscillator capacitor bank setting (high 1 bit) R/W Bit name Function Bit operation
: Unused BIT
Read/ Write Binary value 0 0 0 0 h’01 0 0 0 1 0 0 0 0 h’0F 1 1 1 1 0 0 0 0 h’00 0 0 0 0 0 0 0 0 h’01 0 0 0 1 * * * * h’00 * * * * * * * * h’00 * * * * 0 0 0 1 h’10 0 0 0 0 * * * * h’0* * * * * Hex value
No.A1928-16/18
LC01707PLF
Register Map 4
* HEX value is set by default.
Register address 18h BIT 7 6 5 4 3 2 1 0 19h 7 6 5 4 3 2 1 0 1Ah 7 6 5 4 3 2 1 0 1Bh 7 6 5 4 3 2 1 0 1Ch 7 6 5 4 3 2 1 0 1Dh 7 6 5 4 3 2 1 0 1Eh 7 6 5 4 3 2 1 0 1Fh 7 6 5 4 3 2 1 0 DOUTSEL DCNTEST DOUTTEST Register for TEST Register for TEST Register for TEST R/W R/W R/W DRS[6] DRS[5] DRS[4] DRS[3] DRS[2] DRS[1] DRS[0] IFCOUNT_L[7] IFCOUNT_L[6] IFCOUNT_L[5] IFCOUNT_L[4] IFCOUNT_L[3] IFCOUNT_L[2] IFCOUNT_L[1] IFCOUNT_L[0] IFCOUNT_H[7] IFCOUNT_H[6] IFCOUNT_H[5] IFCOUNT_H[4] IFCOUNT_H[3] IFCOUNT_H[2] IFCOUNT_H[1] IFCOUNT_H[0] IMCOUNT_L[7] IMCOUNT_L[6] IMCOUNT_L[5] IMCOUNT_L[4] IMCOUNT_L[3] IMCOUNT_L[2] IMCOUNT_L[1] IMCOUNT_L[0] IMCOUNT_H[7] IMCOUNT_H[6] IMCOUNT_H[5] IMCOUNT_H[4] IMCOUNT_H[3] IMCOUNT_H[2] IMCOUNT_H[1] IMCOUNT_H[0] F0_L[7] F0_L[6] F0_L[5] F0_L[4] F0_L[3] F0_L[2] F0_L[1] F0_L[0] F0_H[7] F0_H[6] F0_H[5] F0_H[4] F0_H[3] F0_H[2] F0_H[1] F0_H[0] f0 detection oscillation frequency count value (high 8 bits) f0 detection oscillation frequency count value (low 8 bits) Frequency measurement result for master time constant setting Unused Unused IF count value (high 8 bits) IF count value (low 8 bits) 2
nd
: Unused BIT
Read/ Binary value 0 Hex value Function Bit operation Write
Bit name
S-meter detection level
Detection range can be changed by setting to DNGA (02h)
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
* * * h’** * * * * * * * * h’** * * * * * * * * h’** * * * * * * * * h’** * * * * * * * * h’** * * * * * * * * h’** * * * * * * * * h’** * * * * 0 0 0 0 h’02 0 0 1 0
IF frequency measurement results
Continued on next page.
No.A1928-17/18
LC01707PLF
Continued from preceding page.
Register address 20h BIT 7 6 5 4 3 2 1 0 21h 7 6 5 4 3 2 1 0 22h 7 6 5 4 3 2 1 0 DENINT MASKSEL LOSEL INTPH INTIM INTLO TESTSEL[2] TESTSEL[1] TESTSEL[0] DSW TIMESEL2[1] TIMESEL2[0] TIMESEL[1] TIMESEL[0] Local oscillator capacitor bank control sequential comparison control operation clock setting 0:10μs 1: 20μs 2:40μs 3:80μs Register for TEST Register for TEST Register for TEST Register for TEST Register for TEST Register for TEST Register for TEST Register for TEST Register for TEST PLL loop filter ON/OFF Local oscillator capacitor bank control correcting circuit operation clock setting 1:ON 0:OFF 0:200μs 1: 400μs 2:800μs 3:1600μs R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ERR2 ERR1 DCOSEL2 DCOSEL1 DCOSEL0 DWAITSEL[1] DWAITSEL[0] Local oscillator capacitor bank control error flag 2 Local oscillator capacitor bank control error flag 1 Local oscillator capacitor bank value changeover Local oscillator capacitor bank control process changeover Local oscillator capacitor bank control process changeover (micro alignment) PLL operation check wait time after local oscillator capacitor bank adjustment 1:cap bank control value 0:I C input value 1:correcting process after sequential comparison 0:No correcting process after sequential comparison 1:micro adjustment process 0:No micro adjustment process 0:200μs 1: 400μs 2:800μs 3:1600μs
2
Read/ Bit name Function Bit operation Write
Binary value 0
Hex value
R/W R/W R/W R/W R/W R/W R/W
0 0 0 1 0 1 0 0 0 0 0 h’0A 1 0 1 0 0 0 0 1 h’15 0 1 0 1 h’0A
SD pin specification SD voltage level VDD: supply voltage
item High level output voltage Low level output voltage min VDD-0.8 0 max VDD 0.4 unit V V
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This catalog provides information as of October, 2011. Specifications and information herein are subject to change without notice. PS No.A1928-18/18