LC0710LG

Ordering number : ENA1345 CMOS IC LC0710LG Overview Monaural CODEC + Audio I/F + Video Driver The LC07410LG is an IC that integrates a video driver with audio CODEC developed for digital still cameras and other portable equipment. Incorporating 16-bit A/D and D/A converters as well as a microphone amplifier and speaker driver that are necessary for audio recording and playback, the one-chip IC is ideal for use to create audio interfaces. Functions ■ Audio Block • Audio interfaces • ∆Σ method 16-bit monaural A/D and D/A converters I2S, Left-justified mode, Right-justified mode • Generates bias voltage (2.3V) for microphone • Supports microphone amplifier • PLL differential inputs (0/+20/+26dB) Input: 12MHz, 13.5MHz, 24MHz, 27MHz • Amplifier with automatic level control (ALC) Sampling frequency: 7.86kHz to 48kHz (-14dB to +34dB) for recording system PLL master mode/slave (EXT) mode • Wind cut HPF • Loopback: ADOUT to DAIN switch incorporated • Two programmable digital filter HSF/Notch filter/LPF/EQ ■ Video Block • Digital volume with • DC direct coupling input/output automatic level control (ALC) for playback system • Built-in 6th order low-pass filter (fc = 7.5MHz) Supports zerocross detection and soft switching • Amplifier gain selectable (6dB or 12dB) • Line output • Drive capacity 75Ω, 1 system On-chip MUTE and POP-noise suppression circuits • Speaker driver Supports VDDS = 5V (piezoelectric speaker supported) BTL drive, rated output of 350mW at 8Ω, VDDS = 3V 1W at 8Ω, VDDS = 5V Idling current adjustable Supports BEEP input, volume level switchable Continued on next page. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. D0308 MS 20081010-S00002 No.A1345-1/36 LA07410LG Continued from preceding page. ■ REG Block • 3.0V output linear regulator for Audio Block • Overcurrent protective function (typ: 200mA) • Quick discharge activity • 3-line serial register control • Digital I/O 1.8V supported • Supply voltage VDDIO = 1.8V/3.3V (1.71 to 3.6V) VDDA = VDDP =3 .0V (2.7 to 3.6V) VDDR = 3.3V (3.2 to 3.6V) VDDV = DVDD = 3.3V (2.7 to 3.6V) VDDS = 3.3/5V (2.7 to 5.5V) • Operating ambient temperature: -20 to +80°C Function comparison table of LC07410 and LC074146 Function Logic I/O 1.8V accepted 3V Regulator BEEP sound generator PLL frequencies EXT-BEEP GAIN ALC attack speed ALC recovery speed ALC noise gate function Digital filters Wind cut HPF +2 programmable filters Wind cut HPF + EQ (HSF) + Notch flexible 0dB, -15/-18/-21dB 2step variable 3step variable Pre-fix -12/-15/-18/-21dB monotonic monotonic LC07410 LC074146 Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage (5V system) Maximum supply voltage (3V system) Input voltage Output voltage Input/output voltage Allowable operating voltage range VIN max VOUT max VIO max VDDSRANGE VDDRRANGE VDDARANGE VDDIORANGE Allowable power dissipation Operating ambient temperature Storage ambient temperature Pd max Topr Tstg VDDS VDDR VDDA, VDDP, VDDV, DVDD VDDIO Ta = 80°C * -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 2.7 to 5.5 3.2 to 3.6 2.7 to 3.6 1.71 to 3.6 500 -20 to +80 -55 to +125 V V V V V V V mW °C °C VDD3 max Other than VDDS -0.3 to 4.0 V Symbol VDD5 max VDDS Conditions Ratings -0.3 to 7.0 unit V * Mounted on a specified board: 40mm×50mm×0.8mm, glass epoxy board 2S2P (4-layer board) No.A1345-2/36 LA07410LG Recommended Operating Range at Ta = 25°C, VSSV = DVSS = VSSR = VSSA = 0V Parameter Supply voltage Symbol VDDIO DVDD VDDana VDDV VDDR VDDS Supply voltage gap VDDDV VDDDR VDDID VDDPR VDDPA VDDAS VDDVS Inpupt high level voltage Input low level voltage Input clock frequency Input clock duty VIH VIL fMCLK DutyMCLK VDDIO pin DVDD pin VDDP, VDDA pin VDDV pin VDDR VDDS pin DVDD-VDDV DVDD-VDDR VDDIO-DVDD VDDP-VDDR VDDP-VDDA VDDA-VDDS VDDV-VDDS (*1) (*1) MCLKIN pin MCLKIN pin 0.8×VDDIO DVSS 2.012 0.45 0.50 Conditions min 1.71 2.7 2.7 2.7 3.2 2.7 Ratings typ 3.3 3.3 3.0 3.3 3.3 3.3/5.0 max 3.6 3.6 3.6 3.6 3.6 5.5 0.3 0.3 0.3 0.3 0.3 0.3 0.3 VDDIO 0.2×VDDIO 27 0.55 V V V V V V V V V V V V V V V MHz % unit (*1) Applicable pins: PDNB, CSB, SCK, SDA, TESTIN, DAIN, MCLKIN, BCLK, LRLK (in input mode) Electrical Characteristics at Ta = 25±2°C, VDDIO = 1.71 to 3.6V, VDDA = VDDP = VDDV = DVDD = 2.7 to 3.6V, VDDR = 3.2 to 3.6V, VSSS = 2.7 to 5.5V, VSSV = DVSS = VSSR = VSSA = 0V Parameter Input high level current Inputp low level current Output high level voltage Output low level voltage Symbol IIH IIL VOH1 VOL1 VI = VDDIO (*1) VI = DVSS (*1) IOH = -1mA (*2) IOL = 1mA (*2) -1 0.8×VDDIO 0.2×VDDIO Conditions min Ratings typ max +1 µA µA V V unit (*1) Applicable pins: PDNB, CSB, SCK, SDA, TESTIN, DAIN, MCLKIN, BCLK, LRCK (in input mode) (*2) Applicable pins: ADOUT, BCLK, LRCK (in output mode) Analog Characteristics at Ta = 25°C, VDDA = VDDP = 3.0V, VDDIO = DVDD = VDDS = VDDV = VDDR = 3.3V, fs=48kHz Parameter Current drain REC time PB (LINE) time PB (SPK) time Video block 1 Video block 2 Power down time current MIC MIC amplifier gain VGmic VIN = -30dBV, 1kHz, MGAIN[1:0] = 01 VIN = -30dBV, 1kHz, MGAIN[1:0] = 10 VIN = -30dBV, 1kHz, MGAIN[1:0] = 11 MIC amplifier output THD+N MIC amplifier output noise voltage MIC bias output voltage Vmicpwr RL = 5kΩ 2.2 2.3 2.4 V VNOmic MIC IN no signal, A-weighted, MGAIN[1:0] = 11 -88 -82 dBV THDNmic VIN = -30dBV, 1kHz, MGAIN[1:0] = 11 -1 19 25 0 20 26 -80 1 21 27 -70 dB dB dB IDDRA1 IDDPA2 IDDPA3 IDDV1 IDDV2 IDDPD REG/PLL/MIC/PGA/ADC on, no input signal REG/PLL/DAC/LINE on, no input signal REG/PLL/DAC/SPK on, no input signal VDDV, no input signal VDDV, Video in = white 50% VDDA+VDDP+VDDR+VDDS+VDDV+DVDD+VDDIO, clock stopped 9.0 8.0 11.0 4.0 8.0 13.8 12.2 15.2 6.1 12.8 1.0 18.0 16.0 21.0 8.0 16.0 10 mA mA mA mA mA µA Symbol Conditions min Ratings typ max unit Continued on next page. No.A1345-3/36 LA07410LG Continued from preceding page. Parameter ALC Gain change Gain control range DGalc VGalc -14 0.6×VDDA -80 80 80 86 86 -74 1 +34 dB dB Symbol Conditions min Ratings typ max unit ADC: ALCIN input, ALCOFF, PGA Gain = 0dB Analog input voltage THD+N Dynamic range S/N ratio DAC Digital volume change DGvol1 DGvol2 DGvol3 LINE: DAC→LINE Gain = 0dB, DVOL = 0dB Analog output voltage THD+N Dynamic range S/N ratio SPK SPK amplifier gain SPK output distortion SPK output noise voltage SPK maximum rated output BEEP gain VGbp BTL, RL=8Ω BPVOL[1:0] = 00 BTL, RL = 8Ω BPVOL[1:0] = 01 BTL, RL = 8Ω BPVOL[1:0] = 10 BTL, RL = 8Ω BPVOL[1:0] = 11 Regulator Regulator output voltage Video driver Video amplifier gain VGvideo VGAIN[1:0] = 00, VDIN = 1Vp-p 100% white VGAIN[1:0] = 10, VDIN = 0.5Vp-p 100% white Frequency characteristics Fva f = 8MHz/100kHz f = 20MHz/100kHz Input impedance Rvin 100 5 11 6 12 -4.5 -40 120 7 13 0 -35 dB dB dB dB kΩ VOreg IOUT = 20mA 2.9 3.0 3.1 V -2 -16 -19 -22 0 -15 -18 -21 2 -14 -17 -20 dB dB dB dB VGsp HDsp VNOsp VOMsp SPKIN = -9dBV, 1kHz , BTL, RL = 8Ω SPKIN = -9dBV, 1kHz SPKIN no signal, RL = 8Ω RL = 8Ω, THD = 3% 300 11 12 0.2 -86 350 13 1 -80 dB % dBV mW Voutda THDNda DRda SNda 0dBFS, 1kHz 0dBFS, 1kHz -60dBFS, A-weighted A-weighted 80 80 0.6×VDDA -83 88 88 -74 Vp-p dB dB dB +12dB to -10dB -11dB to -42dB -44dB to -64dB 0.5 1 2 dB dB dB Vinad THDNad DRad SNad 0dBFS, 1kHz -1dBFS, 1kHz -60dBFS, A-weighted ALCIN no signal, A-weighted Vp-p dB dB dB ADC Filter Characteristics Parameter Resolution Passband Stopband Passband ripple Stopband attenuation Output data delay HPF cutoff frequency -3dB 0 to 20kHz -69 58 0.0000385fs ±0.045dB 0 0.5465fs ±0.045 dB dB 1/fs Hz 1.85Hz@fs = 48kHz Conditions min Ratings typ 16 0.4535fs max Bit 21.8kHz@fs = 48kHz 26.2kHz@fs = 48kHz unit Remarks No.A1345-4/36 LA07410LG DAC Filter Characteristics Parameter Resolution Passband Stopband Passband ripple Stopband attenuation Output data delay HPF cutoff frequency -3dB -63 48 0.0000385fs ±0.015dB 0 0.5465fs ±0.015 dB dB 1/fs Hz 1.85Hz@fs = 48kHz Conditions min Ratings typ 16 0.4535fs max Bit 21.8kHz@fs = 48kHz 26.2kHz@fs = 48kHz unit Remarks Switching Characteristics Parameter PLL CKIN frequency fCKI PLL used EXT input present BCLK frequency fBCK FBCLK = 0 FBCLK = 1 BCLK duty cycle LRCK frequency LRCK duty cycle CLK transition time ↑ CLK transition time ↓ dtBK fLR dtLR trCK tfCK Rise time, MCLKIN/BCLK/LRCK inputs present Fall time, MCLKIN/BCLK/LRCK inputs present 45 7.86 45 50 12 2.012 64fs 32fs 50 55 48 55 10 10 % kHz % ns ns 27 24.576 MHz MHz Symbol Conditions min Ratings typ max unit Package Dimensions unit : mm (typ) 3370 TOP VIEW 3.6 BOTTOM VIEW 0.55 6 78 4.4 0.45 1 2 34 5 0.5 FE 0.3 0.0 NOM D CB A 0.5 SIDE VIEW 0.85 MAX SANYO : FLGA40(4.4X3.6) No.A1345-5/36 LA07410LG Pin Assignment NC ADOUT VDDIO DVSS SCK NC 8 MCLKIN LRCK DVDD TESTIN SDA CSB 7 MCLKO VDDR BCLK DAIN PDNB VDREF 6 VSSR REGOUT VSSV VDOUT 5 VCOFIL VDDP Top view VDDV VDIN 4 ALCIN MICPWR VDDA BEEP VSSS SPOUTP 3 MICOUT MICINN VSSA LOUT2 VDDS SPOUTN 2 NC MICINP VREF LOUT1 SPKIN NC 1 A B C D E F Block Diagram 3.0V 3.3V MICOUT VCOFIL VREG VDDP VSSR ALCIN MICPWR MIC Power MIC AMP LDO PLL -14 to +34dB MCLKIN MCLKO MICINP MICINN ADC Digital filter 0/+20/+26dB VDDA VSSA VREF ADOUT DAIN VREF 0/4/6/8dB ALC CTL MUTE 0/6dB I/F VDDIO VDDR BCLK LRCK 1.8V or µP/ 3.3V DSP 3.3V LINE OUT LOUT1 DAC VOL DVDD DVSS TESTIN LOUT2 BEEP GEN SPKIN BEEP +6/+12dB SDA SPK AMP SPOUTN SPOUTP VSSS VDIN LPF VDOUT VDDV REF VDREF VSSV MODE CTL PDNB SCK CSB VDDS 1.8V or 3.3V 3.3V or Li+ batt. 3.3V Video out VIDEO DAC No.A1345-6/36 LA07410LG Pin Function Pin No. B3 Pin name MICPWR I/O O (Note) I/O: I => input, Is => Schmitt input, O => output, IO s=> Schmitt input/output Function Microphone power supply output (2.3V) Equivalent circuit B1 MICINP I Microphone amplifier input (+ side) 70kΩ B2 MICINN I Microphone amplifier input (- side) 70kΩ C3 C1 VDDA VREF − O Analog block power supply (3V) 3V analog power supply reference voltage output C2 D1 VSSA LOUT1 − O Analog block ground (0V) Line output 1 D2 LOUT2 O Line output 2 D3 BEEP I BEEP signal input, mixed to speaker amplifier 5kΩ 5kΩ 107kΩ D3 E1 SPKIN I Speaker amplifier input E1 5kΩ 10kΩ Continued on next page. No.A1345-7/36 LA07410LG Continued from preceding page. Pin No. E2 F2 Pin name VDDS SPOUTN I/O − O Function Speaker analog power supply Speaker output (-) Equivalent circuit F3 SPOUTP O Speaker output (+) E3 E4 F4 VSSS VDDV VDIN − − I Speaker analog ground Video driver analog power supply Video signal input 120kΩ 120kΩ F5 VDOUT O Video signal output F6 VDREF O Video VREF 500Ω 500Ω 50kΩ E5 E6 F7 E8 E7 D8 C7 C8 D7 VSSV PDNB CSB SCK SDA DVSS DVDD VDDIO TESTIN − Is Is Is Is − − − I Video driver ground Reset (negative polarity) Chip select (negative polarity) Microcontroller IF Serial clock Serial data input Digital ground (0V) Digital power supply (3.3V) Digital I/O power supply (3.3V/1.8V) Test input (VSS fixed in normal operation) Microcontroller IF Microcontroller IF schmitt D6 DAIN I DAC serial data input B8 ADOUT O ADC serial data output Continued on next page. No.A1345-8/36 LA07410LG Continued from preceding page. Pin No. B7 Pin name LRCK I/O IOs LR clock input Function Equivalent circuit schmitt C6 BCLK IOs Bit clock input A6 MCLKO O Master clock output (Default: Set to Low, serial setting enables output/Addr: 16h) A7 MCLKIN I Master clock input B6 B5 VDDR REGOUT − O Regulator power supply input (3.3V) Regulator output pin 144kΩ 100kΩ 100Ω A5 A4 VSSR VCOFIL − O Regulator block ground VCO filter pin 100Ω B4 A3 VDDP ALCIN − I PLL block supply (3.0V) ALC amplifier input 20kΩ A2 MICOUT O Microphone amplifier output No.A1345-9/36 LA07410LG Interface Timing Characteristics Parameter Microcontroller serial interface timing SCLK cycle time SCLK high period SCLK low period Data setup time Data hold time CSX rise to SCLK wait time SCLK to CSX rise wait time Rise time Fall time Audio data timing Clock phase (Note 2) Clock phase (Note 3) Data delay time Data setup time Data hold time tPH tPH tDD tSUA tHDA 0 1T 1T 75 1/(128fs) 75 ns ns ns ns ns tCYC tSH tSL tSU tHD tWSCLK tWCSX tSR tSF 4T 2T 2T 2T 2T 0T 4T 8T 4T 4T 4T 4T 2T 6T 50 50 ns ns ns ns ns ns ns ns ns Symbol Ratings min typ max unit Note 1: T = 1/fMCLK, fMCLK: Frequency of MCLKIN pin; example: when fMCLK = 10MHz, T = 100ns, 2T = 200ns Note 2: LRCK and BCLK are inputs in Slave mode. The MCLK timing needs only to be synchronized with LRCK and BCLK and its phase is irrelevant. Note 3: In master mode, LRCK and BCLK are output in master mode and fs is the sampling frequency. Note 4: The load of output pin: 30pF. Microcontroller Serial Interface Timing Diagram CSB tCYC tWSCLK tSH tSL tWCSX SCK tSU tHD SDA A[7] tSF tSR Dn[0] Audio Data Timing Diagram LRCK tPH BCLK tDD ADOUT tSU DAIN tHD tPH No.A1345-10/36 LA07410LG Audio Data Formats • I2S mode LRCK BCLK ADOUT 15 14 1 Lch Data 0 15 14 1 Rch Data 0 • Left-justified mode LRCK BCLK ADOUT 15 14 1 0 15 14 1 0 15 Lch Data Rch Data • Right-justified mode LRCK BCLK ADOUT 0 15 14 Lch Data 1 0 15 14 Rch Data 1 0 PLL/BCLK/LRCK Master/Slave Pin No. A7 A6 Pin Name MCLKIN MCLKO Slave Mode (PLL: OFF) Input Output (through) Master Mode (PLL: ON) Input Output (PLL = 256fs) Pin No. B7 C6 Pin Name LRCK BCLK Slave Mode (ADF_MASTER = 0) Input Input Master Mode (ADF_MASTER = 1) Output Output No.A1345-11/36 LA07410LG Microcontroller Serial Interface The internal registers values are written by the serial interface consisting of the three CSB, SCK, and SDA lines. When the CSB pin is set low, the LC07410LG is switched into the mode that enables operation. The data is received on a byte basis with MSB first. Continuous access (burst access) is also possible, and the addresses incremented by 1 are accessed in sequence with each byte following access to the register specified by the address byte. If the size of data exceeding the highest address (39h) is accessed in this process, the data concerned is treated as invalid. In other word, the address never wraps around to 00h. Transferring data to one address A[7:0] D[7:0] X CSB SCK SDA X X A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] ADDRESS BYTE WRITE DATA (address A) : Designated address : Register data : Invalid X X Transferring data to contiguous addresses CSB SCK SDA X X A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] ADDRESS BYTE WRITE DATA (address A) WRITE DATA (address A+1) Dn[0] X X No.A1345-12/36 LA07410LG Specification Details • Power down/system reset When the PDNB pin is set to 0, all the circuits are set to power down mode regardless of the power down settings for each block. A 0 on the PDNB pin also triggers a system reset. After the power is first applied, the system must be reset without fail. [See the section on “Checkpoint_2) Resetting”] After resetting, the contents of the serial port register are initialized. The VREF buffer is activated by releasing power down mode by setting the PDNB pin from 0 to 1, and then by setting VREF_BIAS[1:0] to 01. When VREF_BIAS [1:0] is set to 10, VREF starts. Along with the start of VREF, the LINE output pin is biased to 1/2VDDA. Once the VREF voltage has stabilized, VREF_BIAS [1:0] must be set to 11 (normal state). Reference voltage generator circuit VREF_BIAS: Voltage Reference Bias ADRS 01h Bit [5:4] Name VREF_BIAS Init 00b Sets the reference voltage circuit (VREF pin). 11: Normal operation (standard resistor value) 10: Quick rise to reference voltage 01: Activates IREF bias, VREF OFF 00: Power down The target voltage is reached quickly by connecting a low-resistance element in the “reference voltage generation circuit.” During normal operation, a standard resistance is recommended in order to save power. * Bold letters indicate initial settings. Description Power Control ADRS 00h Bit [7] Name MIC_PDX Init 0b MIC amplifier circuit, power control 1: power on [6] MIC_PWR_PDX 0b 0: power down Description MIC power circuit (MIC_PWR pin), power control 1: power on 0: power down [5] PGA_PDX 0b PGA circuit, power control 1: power on 0: power down [4] ADC_PDX 0b ADC circuit, power control 1: power on 0: power down [3] DAC_PDX 0b DAC circuit, power control 1: power on 0: power down [2] SEL_PDX 0b Selector (LOUT2) circuit, power control 1: power on 0: power down Line out circuit (LOUT1) circuit, power control 1: power on 0: power down Speaker amplifier circuit, power control 1: power on 0: power down [1] LO_PDX 0b [0] SP_PDX 0b 01h [2] PLL_PDX 0b PLL circuit, power control 1: power on 0: power down (PLL-EXT mode) [1] REG_PDX 0b Regulator circuit, power control 1: power on 0: power down [0] VD_PDX 0b Video driver circuit, power control 1: power on 0: power down Sampling Frequency Setting Set sampling frequency used by FS [4:0] register. This is necessary to make it for correctly setting digital frequency characteristic and ALC damping time constant. The setting is adjusted to a value that is the closest to fs used. ADRS 15h Bit [3:0] Name FS Init 1000b Sampling Frequency Setting 1000: 48kHz/0111: 44.1kHz/0110: 32kHz/0101: 24kHz 0100: 22.05kHz/0011: 16kHz/0010: 12kHz/0001: 11.025kHz 0000: 8kHz Note: This setting doesn’t synchronize with PLL setting. It is necessary to set it individually respectively. Refer to the page of PLL function explanation for PLL setting. Description No.A1345-13/36 LA07410LG • 3V Regulator Built-in 3V Regulator for VDDA,VDDP. The regulator starts by setting as REG_PDX = 1. Output current is 100mA (typ). It provides with max 200mA (typ) output current limiter for over-current protective function. • Microphone (MIC) amplifier The microphone amplifier has a differential input and a gain of +26dB (typ). Its gain can also be set to +20dB or 0dB by register MGAIN [1:0]. Its input resistance is 70kΩ (typ). The MICPWR is a power output pin for the microphone, and its output voltage is 2.3V (typ 0.767×VDDA). The maximum output current is 20mA. The microphone amplifier is placed in the power down mode by setting MIC_PDX to 0. When MIC_PWR_PDX is set to 0, the microphone power supply circuit is placed in the power down mode. ADRS 02h Bit [5:4] Name MIC_GAIN Init 01b MIC amplifier circuit, gain setting 11: 26dB 10: 20dB 01: 0dB 00: 0dB Description • Recording system automatic level control (ALC) The amplifier gain of the PGA (Programmable Gain Amplifier) must be automatically adjusted so that the A/D converter output audio level is setup to the predetermined value. The gain can be varied within a range (maximum) of -14dB to +34dB. When using ALC in the recording system, set REC_ALC to 1 and PB_ALC to 0 (recording system ALC mode). When REC_ALC is set to 0 and PB_ALC is set to 0 (ALC off mode), the PGA is placed in the manual mode, and the amplifier gain is fixed to the value of the ALC_GAIN register setting. When PGA_PDX is set to 0, the PGA is placed in the power down mode. During normal use, the state of PGA_PDX must be switched at the same time as ADC_PDX. For further details on operation, refer to “Description of ALC/limiter (Automatic Level Control) operation.” Any of eight recording ALC levels (in 1dB steps from -3dBFS to -10dBFS) can be set using the ALC_VAL register. ADRS 03h Bit [6:4] Name ALC_VAL Init 001b Set the ALC limiter level 000: -3dBFS 001: -4dBFS 010: -5dBFS 011: -6dBFS 100: -7dBFS 101: -8dBFS 110: -9dBFS 111: -10dBFS [2:0] 04h [6:4] [2:0] 05h [6:4] [2:0] 06h [6:4] [2:0] 07h 08h [2:0] [7] ALC_FA1 ALC_THA ALC_FA2 ALC_THR1 ALC_FR1 ALC_THR2 ALC_FR2 ALC_FR3 ALC_FULLEN 010b 010b 100b 011b 100b 011b 100b 100b 0b Attack coefficient 1 setting Set the attack speed switch over thresh Attack coefficient 2 setting Set the recovery speed switch over thresh1 Recovery coefficient 1 setting Set the recovery speed switch over thresh2 Recovery coefficient 2 setting Recovery coefficient 3 setting Sets the full scale detection mode 1: Performs attack operation regardless of the ALCZCD setting when a full scale is detected. 0: Normal operation [6] ALC_ZCD 1b Controls the gain change operation at zerocross timing. 1: Changes the gain at zerocross timing. 0: Changes the gain without waiting for a zerocross timing. [5:4] ALC_ZCDTM 01b Set the zerocross detection timeout time. Valid when [ALC_ZCD] = 1. 11: 2048/fs 10: 1024/fs 01: 512/fs 00: 256/fs * It becomes the above-mentioned 1/4 times at fs 8k to12kHz, It becomes the above-mentioned 1/2 times at fs 16k to 24kHz. [3:2] ALC_TLIM 01b Set the inter-zerocross attack limit. 11: 4dB 10: 2dB 01: 1dB 00: 0.5dB Valid when [ALC_ZCD] = 1 [1:0] ALC_RWT 10b Set the recovery alert time 11: 1024/fs 10: 512/fs 01: 256/fs 00: 128/fs * It becomes the above-mentioned 1/4 times at fs 8k to 12kHz, It becomes the above-mentioned 1/2 times at fs 16k to 24kHz. Description Continued on next page. No.A1345-14/36 LA07410LG Continued from preceding page. ADRS 09h Bit [7] Name ALC_NGEN Init 0b Set the noise gate function 1: Valid 0: Invalid [6:4] [3:2] [1:0] 0Bh [5:0] ALC_NGTH ALC_NGDT ALC_NGRT ALC_VMAX 100b 10b 01b 0Eh Set the noise gate silent detection thresh level Set the noise gate silent detection time/See the gain attenuation time Set the noise gate reset time Set the maximum PGA gain value (Init value = 0Eh: 0dB) Refer to “ALC Circuit Gain Setting Table.” 0Ch [5:0] ALC_GAIN 0Eh Set the manual mode PGA gain value (Init value = 0Eh: 0dB) Refer to “ALC Circuit Gain Setting Table.” 0Dh [1:0] REC_ALC PB_ALC 10b ALC mode setting 10: REC ALC, PB manual gain setting 01: PB ALC, REC manual gain setting 00/11: ALC OFF, REC/PB manual gain setting See the section on "Description of ALC Operation." Description • Attack coefficient 1 FA1[2:0] 000 001 010 011 100 101 110 111 1dB Attenuation time* 1/fs 2/fs 4/fs 8/fs 16/fs 32/fs 64/fs 128/fs fs = 48kHz 24kHz 12kHz 20.83µs 41.67µs 83.33µs 166.7µs 333.3µs 666.6µs 1.333ms 2.666ms • Attack coefficient 2 FA2[2:0] 000 001 010 011 100 101 110 111 1dB Attenuation time* 1/fs 2/fs 4/fs 8/fs 2 /fs 210/fs 211/fs 2 /fs 12 9 fs = 48kHz 24kHz 12kHz 20.83µs 41.67µs 83.33µs 166.7µs 10.66ms 21.33ms 42.67ms 85.33ms * At fs = 32k to 48kHz setting. 1/4 times at 8k to 12kHz, 1/2 times at 16k to 24kHz (48kHz, 24kHz, 12kHz become the same speed). • Attack speed switch over thresh level THA[2:0] 000 001 010 011 100 101 110 111 Level to ALC_VAL +1dB +2dB +3dB +4dB +5dB +6dB +7dB +8dB • Recovery coefficient 1 FR1[2:0] 000 001 010 011 100 101 110 111 FS/s* 13.2 6.6 3.3 1.65 0.828 0.424 0.212 0.106 • Recovery coefficient 2 FR2[2:0] 000 001 010 011 100 101 110 111 FS/s* 3.3 1.65 0.828 0.424 0.212 0.106 0.053 0.026 • Recovery coefficient 3 FR3[2:0] 000 001 010 011 100 101 110 111 FS/s* 0.828 0.424 0.212 0.106 0.053 0.026 0.013 0.006 * Value at fs = 48kHz, 24kHz, 12kHz No.A1345-15/36 LA07410LG • Recovery speed switch over thresh level 1 THR1[2:0] 000 001 010 011 100 101 110 111 Level to ALC_VAL -26dB -24dB -22dB -20dB -18dB -16dB -14dB Prohibition • Recovery speed switch over thresh level 2 THR2[2:0] 000 001 010 011 100 101 110 111 Level to ALC_VAL -20dB -18dB -16dB -14dB -12dB -10dB -8dB Prohibition • Zerocross timeout period ZCDTM[1:0] 00 01 10 11 Timeout period* 1024/fs 2048/fs 4096/fs 8192/fs fs = 48k/24k/12kHz 21.33ms 42.67ms 85.33ms 170.7ms • Recovery alert time RWT[1:0] 00 01 10 11 Standby time 128/fs 256/fs 512/fs 1024/fs fs = 48k/24k/12kHz 2.67ms 5.33ms 10.67ms 21.33ms * At fs = 32k to 48kHz setting. 1/4 times at 8k to 12kHz, 1/2 times at 16k to 24kHz (48kHz, 24kHz, 12kHz become the same speed). ALC Circuit Gain Setting Table ALC_VMAX[5:0]/ALC_GAIN[5:0] [5:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h GAIN -14dB -13dB -12dB -11dB -10dB -9dB -8dB -7dB -6dB -5dB [5:0] 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h GAIN -4dB -3dB -2dB -1dB 0dB 1dB 2dB 3dB 4dB 5dB [5:0] 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh GAIN 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 15dB [5:0] 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h GAIN 16dB 17dB 18dB 19dB 20dB 21dB 22dB 23dB 24dB 25dB [5:0] 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h GAIN 26dB 27dB 28dB 29dB 30dB 31dB 32dB 33dB 34dB • Noise gate silent detection thresh NGTH[2:0] 000 001 010 011 100 101 110 111 Thresh -35dBFS -41dBFS -47dBFS -53dBFS -59dBFS -65dBFS -71dBFS -77dBFS • Noise gate silent detection time/Gain attenuation speed (0dB → -35dB) fs = 48kHz NGDT[1:0] 00 01 10 11 Detection time* 213/fs 2 /fs 215/fs 216/fs 14 fs = 48kHz Gain attenuation time* 30×210/fs 30×2 /fs 11 24kHz 12kHz 0.17s 0.34s 0.68s 1.36s 24kHz 12kHz 0.64s 1.28s 2.56s 5.12s 30×212/fs 30×213/fs * At fs = 32k to 48kHz setting. 1/4 times at 8k to 12kHz, 1/2 times at 16k to 24kHz • Noise gate reset time (-35dB → 0dB) fs = 48kHz NGRT[1:0] 00 01 10 11 Gain reset time* 30×28/fs 30×2 /fs 9 24kHz 12kHz 0.16s 0.32s 0.64s 1.28s 30×210/fs 30×211/fs * At fs = 32k to 48kHz setting. 1/4 times at 8k to 12kHz, 1/2 times at 16k to 24kHz (48kHz, 24kHz, 12kHz become the same speed). No.A1345-16/36 LA07410LG Relation Between Output level and Recovery Speed (FR,THR) FR1 FR2 FR3 ALC VAL THR2 THR1 Signal after ADC FR value is shown by inclination (FS/s) of the shape of recovery waves. (FS = Full Scale = 0dBFS) Description of ALC/Limiter (automatic level control) operation Note: Whatever is contained inside the parentheses “ ” is applicable in the PB-ALC mode. The amplifier gain “digital volume value” of the PGA (programmable gain amplifier) is automatically adjusted so that the A/D converter output audio level “digital volume output” is set to the ALC value “ALC_VAL [2:0]”. The PGA “digital volume” gain can be varied in the -14dB to +34dB range. The maximum value “ALC_VMAX [5:0]” can be set in this variable range. • ALC settings · Power-saving function When [PGA_PDX] is 0, the ALC circuit and PGA circuit are set to power down mode. · Manual function (ALC OFF) At REC_ALC = PB_ALC = 0, it become manual mode. PGA gain is fixed by value of ALC_GAIN [5:0] Digital volume value is fixed by EVR_GAIN [6:0] · System operation ALC is performed by feeding back the A/D converter “digital volume” data. Accordingly, configure the settings as shown in the table below in order for the ALC functions to be activated. Resister REC-ALC PGA_PDX ADC_PDX DAC_PDX REC_ALC PB_ALC 1 1 x 1 0 Mode PB-ALC 0 x 1 0 1 (1) Attack operations When the ADC “digital volume” output exceeds the ALC limiter level, ALC_VAL[2:0], the PGA gain “digital volume value” is lowered. When the rate of gain attenuation is ALC_THA[2:0] or more, ALC_FA1[1:0] results, but when the value is less than ALC_THA[2:0], ALC_FA2[1:0] results. When zero-cross detection ALC_ZCD is set to 1, the gain attenuation from zero-cross to zero-cross is limited by the limit value ALC_TLIM[1:0]. No.A1345-17/36 LA07410LG (2) Recovery operations When the ADC “digital volume” output is less than 2dB of the ALC limiter level, ALC_VAL[1:0], and this status continues for the recovery wait time, ALC_RWT[1:0], the PGA gain “digital volume value” is increased. The rate of gain increase is performed using the recovery coefficients given below according to the amplitude. Recovery coefficients by level Output level FR 300ms (LOUT1 charge time) t3 > 1ms (Waiting time of MUTE ON/OFF) t4 > 0s t5 > 300ms (Pull down period) • It makes it to LO_VREFSW = 1 usually. • LO_VREFSW function at power down (LO_PDX = 0) LO_VREFSW = 1: LOUT1 pin becomes VREF level output LO_VREFSW = 0: LOUT1 pin becomes Hi-Z Speaker Amplifier Start/Stop Sequence Speaker amplifier input signal SP_PDX t4 SP_OUT_EN t1 t2 t3 t2 t3 0.5×VDDS SPOUTP/N pin (Speaker output) • Recommendation value t1 > 5ms (Speaker bias start-up time) t2 ≠ 10ms (Processing period when POP sound is decreased. Input signal recommends MUTE.) t3 > 15ms t4 > 1ms • External capacitance connected to SPKIN pin is 0.1µF • SP_OUT_EN must be set to 0 when power down (SP_PDX = 0) mode. No.A1345-32/36 LA07410LG Digital Filter ADC/DAC digital filters ADC Digtal Filter Frequency Response 0 0.15 – 20 0.1 0.2 ADC Digtal Filter Frequency Response (passband) Amplitude – dB – 40 – 60 – 80 – 100 – 120 – 140 0 1 2 3 4 Amplitude – dB 0.05 0 – 0.05 – 0.1 – 0.15 – 0.2 0 0.1 0.2 0.3 0.4 0.5 Frequency – Xfs 0 Frequency – Xfs 0.05 0.04 DAC FIR Filter Frequency Response DAC FIR Filter Ripple – 20 0.03 – 40 0.02 Gain – dB Gain – dB 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 – 60 0.01 0 – 0.01 – 0.02 – 0.03 – 80 – 100 – 120 – 0.04 – 140 – 0.05 0 0.1 0.2 0.3 0.4 0.5 Frequency – fs Frequency – fs No.A1345-33/36 LA07410LG Programmable digital filter setting example Notch Filter 1kHz 2kHz fb = 4kHz 1kHz 2kHz fb = 4kHz @fs = 48kHz High Shelf Filter Q = 0.7 f0 = 20kHz gain (-6dB) 5 0 –5 – 10 5 0 Response – dB – 15 – 20 – 25 – 30 – 35 – 40 – 45 0 5 10 15 20 25 Response – dB –5 – 10 f0 = 15kHz – 15 (-12dB) f0 = 16kHz f0 = 8kHz – 20 (-20dB) 0 5 10 15 20 25 – 25 f – kHz 15 f – kHz 15 Equalizer f0 = 14kHz Equalizer f0 = 8kHz 10 10 fb = 8kHz gain +12dB gain +6dB fb = 4kHz gain +12dB gain +6dB Response – dB fb = 2kHz 0 Response – dB 5 5 fb = 1kHz 0 –5 – 10 fb = 1kHz gain -6dB fb = 4kHz gain -12dB f0 = 5kHz gain -6dB –5 fb = 3kHz fb = 12kHz gain -12dB – 10 f0 = 16kHz – 15 10 15 20 25 0 5 10 15 20 25 – 15 0 5 f – kHz 0 f – kHz Q = 0.7 5 0 LPF f0 = 16 Hz HPF 8k – 20 –5 – 10 Response – dB Response – dB – 40 – 60 – 80 – 100 – 120 – 140 0.1 2 3 57 1 2 3 – 15 – 20 – 25 – 30 – 35 – 40 – 45 z 0H z = 0H f0 20 z 0H 40 z H 1k 10 4k f – kHz Hz 2k kHz 5 7 10 Hz 2 3 5 7 100 0.01 2 3 5 7 0.1 2 3 57 1 2 3 5 7 10 f – kHz No.A1345-34/36 LA07410LG Checkpoints The user is responsible for ascertaining whether this IC can be adopted for the set to be mass production by the user, including the various condition for mounting in the set. 1) Power supply • The 3.0V type and 3.0V/5.0V type are available as the power supply pins. 1.8V type: Digital power supply I/O (VDDIO) 3.0V type: Digital power supply (VDD), analog power supplies (VDDR, VDDA, VDDV, VDDP) 3.0V/5.0V type: Analog power supply (VDDS) • The power-on sequence is such that the power is first applied in sequence starting with the circuits that operate using a high voltage and the power is turned off in sequence starting with the circuits that operate using a low voltage. 2) Resetting • At power-on, the PDNB pin must be set to low without fail. (A) or (B) is executed as shown in the figure below. 95% power startup level Power pin tD PDNB (A) tD PDNB tD > 1µs Normal operation start 0.8V 0.8V (B) Notes: (A) is reset at the same time as the power is first applied. (B) is reset immediately after the power is first applied. The MCLKIN pin clock input must be provided without fail during either the (A) or (B) period. 3) 3-line serial setting • Whenever 3-line serial setting is to be performed, it must be done where the MCLKIN input has stabilized without fail. • If garbled data is found, restart the IC (switching the state of the PDNB pin from low to high) and perform 3-line serial setting again. No.A1345-35/36 LA07410LG Application Circuit Example 3.0V VDDR 1µF 10µF 3900pF ALCIN MICOUT VCOFIL VDDP 3.3kΩ VREG 10µF 0.068µF 1 µF MCLKIN MCLKO VSSR VDDR 0.1µF MICPWR 2.2k to 4.7kΩ 0.47µF MICINP 0.47µF MICINN VDDA 10µF VSSA BCLK LRCK ADOUT DAIN VDDIO VDDIO DVDD DVSS 10µF 10µF DVDD VREF 4.7µF µP/ DSP LINE OUT LOUT1 0.1µF LOUT2 0.1µF SPKIN 0.01µF TESTIN SDA SCK SPOUTN BEEP CSB SPOUTP VDOUT VDREF VDDV VSSV VDDS 10µF 75Ω 10µF VDDS VDDV Video out 1µF PDNB VSSS VDIN VIDEO DAC SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2008. Specifications and information herein are subject to change without notice. PS No.A1345-36/36