LC36256AML-85

Ordering number : EN4163A Asynchronous Silicon Gate CMOS LSI LC36256AL, AML-70/85/10/12 256 K (32768 words × 8 bits) SRAM Overview The LC36256AL, AML are fully asynchronous silicon gate CMOS static RAMs with an 32768 words × 8 bits configuration. This series have CE chip enable pin for device select/nonselect control and an OE output enable pin for output control, and features high speed as well as low power dissipation. For these reasons, the series is especially suited for use in systems requiring high speed, low power, and battery backup, and it is easy to expand memory capacity. Package Dimensions unit: mm 3012A - DIP28 [LC36256AL] Features • Access time 70 ns (max.) : LC36256AL-70, LC36256AML-70 85 ns (max.) : LC36256AL-85, LC36256AML-85 100 ns (max.) : LC36256AL-10, LC36256AML-10 120 ns (max.) : LC36256AL-12, LC36256AML-12 • Low current dissipation During standby 2 µA (max.) / Ta = 25°C 5 µA (max.) / Ta = 0 to +40°C 25 µA (max.) / Ta = 0 to +70°C During data retention 1 µA (max.) / Ta = 25°C 2 µA (max.) / Ta = 0 to +40°C 10 µA (max.) / Ta = 0 to +70°C During operation (DC) 10 mA (max.) • • • • • • Single 5 V power supply: 5 V ±10% Data retention power supply voltage: 2.0 to 5.5 V No clock required (Fully static memory) All input/output levels are TTL compatible Common input/output pins, with three output states Packages DIP 28 -pin (600 mil) plastic package : LC36256AL SOP 28-pin (450 mil) plastic package : LC36256AML SANYO: DIP28 unit : mm 3187 - SOP28D [LC36256AML] SANYO: SOP28D SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 22896HA (OT)/21593JN (OT) No. 4163-1/7 LC36256AL, AML-70/85/10/12 Pin Assignment Block Diagram Pin Functions A0 to A14 WE OE CE I/O1 to I/O8 VCC, GND Address input Read/write control input Output enable input Chip enable input Data input/output Power supply pins Functions Mode Read cycle Write cycle Output disable Nonselect X : H or L CE L L L H OE L X H X WE H L H X I/O Data output Data input High impedance High impedance Supply current ICCA ICCA ICCA ICCS No. 4163-2/7 LC36256AL, AML-70/85/10/12 Specifications Absolute Maximum Ratings at Ta=25°C Parameter Maximum supply voltage Input pin voltage I/O pin voltage Allowable power dissipation Operating temperature range Storage temperature range Symbol VCC max VIN VI/O Pd max Topr Tstg LC36256AL LC36256AML Conditions Ratings 7.0 –0.5* to VCC+0.5 –0.5* to VCC+0.5 1.0 0.7 0 to +70 –55 to +150 Unit V V V W W °C °C * –3.0 V when pulse width is less than 50 ns DC Recommended Operating Ranges at Ta = 0 to +70°C Parameter Power supply voltage Input high level voltage Input low level voltage Symbol VCC VIH VIL min 4.5* 2.2* –0.3* typ 5.0 max 5.5 VCC+0.3 +0.8 Unit V V V * –3.0 V when pulse width is less than 50 ns DC Electrical Characteristics at Ta = 0 to +70°C, VCC = 5 V ±10% Parameter Input leakage current I/O leakage current Output high level voltage Output low level voltage Symbol ILI ILO VOH VOL ICCA1 ICCA2 Conditions VIN = 0 to VCC VCE = VIH or VOE = VIH, VI/O = 0 to VCC IOH = –1.0mA IOL = 2.1mA VCE ≤ 0.2V, VIN ≤ 0.2V or VIN ≥ VCC–0.2V VCE = VIL, II/O=0mA min cycle 70ns Access time 85ns 100ns 120ns 0 to +70°C min –0.5 –0.5 2.4 typ* max +0.5 +0.5 Unit µA µA V 0.4 1 3 30 25 23 20 5 10 50 50 50 50 25 5 0.5 0.4 2 2 V mA mA Operating supply current (DC) Average operating supply current ICCA3 Duty = 100% I I/O = 0mA mA Standby supply current ICCS1 VCE ≥VCC-0.2V VCE = VIH 0 to +40°C 25°C µA ICCS2 mA * Reference values at VCC = 5 V, Ta = 25°C No. 4163-3/7 LC36256AL, AML-70/85/10/12 Input/Output Capacitance at Ta = 25°C, f = 1 MHz Parameter Input/output capacitance Input capacitance Symbol CI/O CIN Conditions VI/O = 0V VIN = 0V min typ max 8 6 Unit pF pF Note: These parameters were obtained through sampling, and not full-lot measurement. AC Electrical Characteristics at Ta = 0 to +70°C, VCC = 5 V ±10% AC testing conditions Input pulse voltage level : 0.8 V, 2.2 V Input rise and fall time : 5 ns Input - output timing level : 1.5 V Output load : 1 TTL gate + CL = 100 pF (85 ns/100 ns/120 ns) 1 TTL gate + CL = 30 pF (70 ns) (including scope and jig capacitance) Read Cycle LC36256AL, AML -85 max min 100 85 85 45 20 10 5 30 0 30 0 Parameter Read cycle time Address access time CE access time OE access time Output hold time CE output enable time OE output enable time OE output disable time OE output disable time Symbol tRC tAA tCA tOA tOH tCOE tOOE tCOD tOOD min 70 -70 max 70 70 35 20 10 5 0 0 20 10 5 0 0 min 85 -10 max 100 100 50 20 10 5 0 0 min 120 -12 max 120 120 60 Unit ns ns ns ns ns ns ns ns ns 30 30 30 30 30 30 Write Cycle LC36256AL, AML -85 max min 100 80 0 60 80 0 0 35 0 10 25 0 Parameter Write cycle time Address valid to end of write Address setup time Write pulse width CE setup time Write recovery time (WE) Write recovery time (CE) Data setup time Data hold time WE output enable time WE output disable time tWC tAW tAS tWP tCW tWR tWR1 tDS tDH tWOE tWOD min 70 65 0 50 65 0 0 30 0 10 0 -70 max min 85 75 0 50 75 0 0 30 0 10 0 -10 max min 120 100 0 70 100 0 0 40 0 10 0 -12 max Unit ns ns ns ns ns ns ns ns ns ns ns 25 25 25 No. 4163-4/7 LC36256AL, AML-70/85/10/12 Timing Chart • Read Cycle (1): CE = OE = VIL, WE = VIH • Read Cycle (2): WE = VIH • Write Cycle (1): WE Control Note (6) No. 4163-5/7 LC36256AL, AML-70/85/10/12 • Write Cycle (2): CE Control Note (6) Notes (1) tCOD, tOOD, and tWOD are defined as the time at which the outputs becomes the high impedance state and are not referred to output voltage levels. (2) An external antiphase signal must not be applied when DOUT is in the output state. (3) tWP is the time interval that CE and WE are low-level and is defined as the interval from the falling of WE to the rising of CE or WE whichever is earlier. (4) tCW is the time interval that CE and WE are low-level and is defined as the time from the falling of CE to the rising of CE or WE whichever is earlier. (5) DOUT goes to the high-impedance state when either OE is high-level, CE is high-level, or WE is low-level. (6) When OE is high-level during the write cycle, DOUT goes to the high-impedance state. Data Retention Characteristics at Ta = 0 to +70°C Parameter Data retention supply voltage Symbol VDR ICCDR1 Data retention supply current ICCDR2 CE setup time CE hold time tCDR tR ** tRC = Read Cycle time Conditions VCE ≥ VCC–0.2V VCC = 3.0V, VCE ≥ 2.8V VCC = 2.0 to 5.5V, VCE ≥ VCC–0.2V 0 tRC** 0.5 25 µA ns ns 0 to +70°C 0 to +40°C 25°C 0.25 min 2.0 typ* max 5.5 10 2 1 µA Unit V * Reference values at VCC = 5V, Ta = 25°C Data Retention Waveform No. 4163-6/7 LC36256AL, AML-70/85/10/12 s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1996. Specifications and information herein are subject to change without notice. PS No. 4163-7/7