LC5822

Ordering number : EN5944 CMOS IC LC5824, LC5823, LC5822 4-Bit Single-Chip Microcontrollers Featuring 4 KB to 8 KB of ROM, 1 Kbit of RAM, and an LCD Driver for Medium Speed Small-Scale Control Applications Overview The LC5822, LC5823, and LC5824 are CMOS microcontrollers that feature the low-voltage operation required for battery-power applications and that provide 4 KB, 6 KB, or 8 KB of ROM, 1 kilobit of RAM, and an LCD driver. These microcontrollers support an instruction set based on that of the earlier LC5800, LC5812, and LC5814 for excellent efficiency in software development. Features • These microcontrollers are high-end versions of the LC5800 and provide the following features. Low Current Drain * In halt mode (typical) • Ceramic oscillator 400 kHz (3.0 V) 200 µA • Crystal oscillator 32 kHz (1.5 V, Ag specifications) 3.0 µA (LCD biases other than 1/3) 4.5 µA (LCD drive: 1/3 bias) • Crystal oscillator 32 kHz (3.0 V, Li specifications) 2.0 µA (LCD biases other than 1/3) 6.0 µA (LCD drive: 1/3 bias) Timer and Counter Functions • One 8-bit programmable timer (May be used as an event counter) • One 8-bit programmable reload timer • Time base timer (for clocks) • Watchdog timer • 8-bit serial I/O (3-pin synchronous system) Standby Functions • Clock standby function (halt mode) Only the oscillator circuits, the divider circuit, and the LCD driver operate. All other internal operations are stopped. This provides a power-saving function in which current drain is minimized, and allows a clock function to be implemented easily with low power dissipation. Furthermore, low-speed and high-speed modes can be implemented by setting the operating modes of the two oscillator circuits. • Full standby function (hold mode) • Halt mode can be cleared by any of two external and two internal interrupts. Applications • LCD display in multi-function watches, timers, and other products • Control and LCD display in timers • Control and LCD display in miniature test equipment, health maintenance equipment, and other products • These microcontrollers are optimal for products that include an LCD display, especially battery powered products. Wide Allowable Operating Ranges Power options supply EXT-V EXT-V EXT-V EXT-V Li Ag Cycle times Supply voltage range VDD = 2.3 to 3.6 V VDD = 2.3 to 3.6 V VDD = 2.3 to 3.6 V VDD = 2.0 to 3.6 V VDD = 2.6 to 3.6 V* VDD = 1.3 to 1.65 V Notes When an 800-kHz ceramic oscillator is used When an 400-kHz ceramic oscillator is used When an 65-kHz crystal oscillator is used When an 32-kHz crystal oscillator is used When an 32-kHz crystal oscillator is used When an 32-kHz crystal oscillator is used 10 µs 20 µs 61 µs 122 µs 122 µs 122 µs Note*: When the backup flag is set, the BAK pin is connected to VDD. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 82198RM (OT) No. 5944-1/24 LC5824, LC5823, LC5822 Improved I/O Functions • External interrupt pins • Input pins that can clear halt mode: 10 pins (maximum) • Input ports with input resistors that can be controlled from software: 8 pins (maximum) • Pins with a function that prevents the input port floating state: 8 pins (maximum) • LCD drive pins: 4 pins (common), 42 pins (segment outputs) • General-purpose I/O ports: 16 pins (when all 4 P port pins are used) • General-purpose inputs: 8 pins • General-purpose outputs (1): 1 pin (the ALM pin) • General-purpose outputs (2): 42 pins (when all 42 of the LCD segment outputs are switched over to function as general-purpose outputs) • 8-bit serial output port: 1 set (3 pins: output, input, and clock) Functional Overview • Program ROM: 4096 × 16 bits LC5824 3072 × 16 bits LC5823 2048 × 16 bits LC5822 • Internal RAM: 256 × 4 bits • All instructions execute in a single cycle. • Extensive set of interrupt functions for clearing halt and hold mode — 8 halt mode clearing functions — 5 hold mode clearing functions — 6 interrupt functions — Subroutines can be nested up to 8 levels (Specialpurpose registers that are shared with the interrupt function are built in.) • Powerful hardware to increase system processing capacity — Segment port related hardware Built-in segment PLA circuit Built-in segment decoder Support for six different LCD drive specifications Outputs can be switched to CMOS levels — Built-in 8-bit synchronous serial I/O circuit — 8-bit read/write timer (plus a separate 8-bit prescaler; can be used as and event counter) — 8-bit reload timer (plus built-in 8-bit prescaler) — Built-in 8-bit prescaler (for use with timer 1, timer 2, and the serial counter) — All of RAM can be used a working area (RAM bank system) — Dedicated data pointer register for RAM access — 15-stage divider circuit for clocks (also used as the LCD voltage alternation frequency generator) — 8-bit table reference function (reads 8-bit ROM data) — Chattering prevention circuit (on two ports) — Alarm signal generation circuit • LCD panel drive output pins with high flexibility (42 pins) Drive system bias · duty bias · duty bias · duty bias · duty bias · duty Static drive Number of driven segments Required number of common pins 168 segments 4 pins 126 segments 3 pins 168 segments 4 pins 126 segments 3 pins 84 segments 2 pins 42 segments 1 pin — The LCD output pins can be switched to function as general-purpose outputs. CMOS/p-channel/n-channel type combinations: Up to 42 pins — An alternation frequency appropriate for the LCD panel used can be selected. • An oscillator appropriate for your system’s specifications can be selected. — A 32- or 65-kHz crystal oscillator can be selected (Used when a clock function is required or for low current drain operation.) — A ceramic oscillator with a frequency from 400 kHz to 2 MHz can be selected (when high-speed operation is required.) Available delivery formats: QIP-80 and chip Package Dimensions unit: mm 3174-QFP80E [LC5824, 5823, 5822] SANYO: QIP80E No. 5944-2/24 LC5824, LC5823, LC5822 Pin Assignment Top view No. 5944-3/24 LC5824, LC5823, LC5822 Pad Arrangement Chip size: 4.92 mm × 5.15 mm Pad size: 120 µm × 120 µm Chip thickness 480 µm (chip specifications) Pad Coordinates PAD No. 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 1 2 3 4 Note: • • • • • Seg 22 Seg 23 Seg 24 Seg 25 Seg 26 Seg 27 Seg 28 Seg 29 Seg 30 Seg 31 Seg 32 Seg 33 Seg 34 Seg 35 Seg 36 Seg 37 Seg 38 Seg 39 Seg 40 Seg 41 Seg 42 XC XTOUT XTIN VDD VSS CFIN/P1 CFOUT/P2 Pin Coordinates X µm Y µm –2030 –2178 –1850 –1670 –1490 –1310 –1130 –950 –770 –590 –410 –230 –50 122 302 482 662 842 1022 1202 1382 1562 1774 1954 2134 2257 2257 2257 2257 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –2178 –1959 –1779 –1599 –1402 PAD No. 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD3 VDD2/BAK VDD1 ALM SO1 SO2 I/O port SO3 I/O port SO4 I/O port M1 M2 I/O port M3 I/O port M4 I/O port RES I/O port Test Test TST CUP1 CUP2 Seg 1 Seg 2 Seg 3 Seg 4 Seg 5 Seg 6 Seg 7 Seg 8 Seg 9 Seg 10 Pin Coordinates X µm Y µm 2257 –1212 2257 2257 2257 2257 2257 2257 2257 2257 2257 2257 2257 2257 2330 2330 2150 1970 1790 1606 1426 1246 1066 886 706 526 346 166 –14 –1032 –852 –601 –419 –236 56 132 364 544 724 904 1636 1998 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 PAD No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Seg 11 Seg 12 Seg 13 Seg 14 Seg 15 Seg 16 Seg 17 Seg 18 Seg 19 Seg 20 Seg 21 COM1 COM2 S1 S2 Input port S3 Input port S4 Input port K1 K2 Input port K3 Input port K4 Input port A1 A2 I/O ports A3 I/O ports A4 I/O ports COM3/P3 COM4/P4 Pin Coordinates X µm Y µm –194 2178 –374 –546 –726 –906 –1086 –1266 –1446 –1626 –1806 –1986 –2270 –2270 –2270 –2270 –2270 –2270 –2270 –2270 –2270 –2270 –2270 –2270 –2270 –2270 –2270 –2270 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 1871 1628 1367 1140 960 734 328 88 –140 –380 –593 –773 –953 –1133 –1602 –1846 The pin numbers are the QIP-80E mass-production package pin numbers. The test pin (TST) must be connected to VSS. Pads number 42 and 43 in the chip version must be left open. Do not use solder dip techniques to mount the QIP-80E package version. In the chip version, the substrate must be either connected to VSS or left open. No. 5944-4/24 LC5824, LC5823, LC5822 System Block Diagram Data I/O - D bus Address B register (4 bits) OPG (2 bits) Program counter (13 bits) Table reference Interrupt control Accumulator (AC) (4 bits) Alarm tone generator Buffer Watchdog timer Reset circuit Crystal oscillator circuit (32 kHz/65 kHz) Timer 1 Serial I/O Clock timer (15 bits) Timer 2 Carrier control circuit Segment decoder strobe decoder Chronograph circuit Chronograph control circuit Switching circuit CF/RC oscillator circuit (400 kHz to 4 MHz) Voltage step- LCD driver System clock generator RAM: Data memory ROM: Program memory DP: Data pointer register BNK: Bank register APG: RAM page flag AC: Accumulator ALU: Arithmetic and logic unit B: B register OPG: ROM page flag PC: Program counter IR: Instruction register STS1: Status register 1 STS2: Status register 2 STS3: Status register 3 STS4: Status register 4 PLA: Programmed logic array used for segment data and strobe functions WAIT.C: Wait time counter No. 5944-5/24 LC5824, LC5823, LC5822 Pin Functions Pin No. 24 25 Pin VDD VSS I/O — — Power supply LCD drive power supply 30 29 28 VDD1 VDD2/BAK VDD3 — — — Power supply specifications Function Options Status at reset Pin • Ag specifications • Li specifications • EXT-V specifications 42 43 CUP1 CUP2 — — Connections of the LCD power supply step-up (step-down) capacitors • CF specifications • RC specifications • Unused 26 27 CFIN CFOUT System clock oscillator connections • Ceramic element connections (CF specifications) Input • RC component connections (RC specifications) Output *: This oscillator circuit is stopped when a STOP or SLOW instruction is executed. Used for reference counting (clock specifications, LCD alternation frequency) and as the system clock. Input • 32-kHz crystal oscillator Output • 65-kHz crystal oscillator *: This oscillator circuit is stopped when a STOP instruction is executed. — Used for the phase compensation capacitor connected between this pin and XTOUT and XTIN. This pin is only used in the chip product. Input-only port • Input pins used to acquire input data to RAM • 1.95-ms and 7.8-ms chattering exclusion circuits included. • Pull-down resistors are built in. Note: the 1.95 ms and 7.8 ms values are for a ø0 of 32.768 kHz. Input-only port • Input pins used to acquire input data to RAM • 1.95-ms and 7.8-ms chattering exclusion circuits included. • Pull-down resistors are built in. Note: the 1.95 ms and 7.8 ms values are for a ø0 of 32.768 kHz. 23 22 XTIN XTOUT • 32-kHz specifications • 65-kHz specifications • 38-kHz specifications • Unused — XC 67 68 69 70 S1 S2 S3 S4 Input • Pull-down resistors • Presence or absence of enabled low-level hold Note: After a reset is transistors cleared, these pins go to the floating state. 71 72 73 74 K1 K2 K3 K4 Input • Pull-down resistors • Presence or absence of enabled low-level hold Note: After a reset is transistors cleared, these pins go to the floating state. • Pull-down resistors enabled Note: After a reset is cleared, these pins go to the floating state. • Input mode • The output latch data is set to 1. The same as those for M1 to M4. However, only for valid ports. 36 37 38 39 M1 M2 M3 M4 I/O I/O port • Input pins used to acquire input data to RAM. • Presence or absence of • Output pins used to output RAM data. low-level hold • M4 is also used as the TM1 external clock input in TM1 mode 3. transistors • M3 is also used for HEF8 halt mode clear control. • Output type: CMOS or *: The minimum period for clock signal inputs is twice the cycle p-channel time • Pull-down resistors are built in. I/O port • Input pins used to acquire input data to RAM. • Output pins used to output RAM data. • Pull-down resistors are built in. I/O port • Input pins used to acquire input data to RAM. • Output pins used to output RAM data. • Pull-down resistors are built in. • A1 is also used as the external interrupt request control input signal (INT). The same as those for M1 to M4. However, only for valid ports. 26 27 79 80 P1 P2 P3 P4 I/O 76 77 78 79 A1 A2 A3 A4 I/O The same as those for M1 to M4. The same as those for M1 to M4. Continued on next page. No. 5944-6/24 LC5824, LC5823, LC5822 Continued from preceding page. Pin No. Pin I/O Function I/O port • Input pins used to acquire input data to RAM. • Output pins used to output RAM data. • Pull-down resistors are built in. SO1 to SO3 are also used as the serial interface pins. • The serial interface function can be selected under program control. • Pin functions: SO1: Serial input SO2: Serial output SO3: Serial clock The serial clock can be taken from either internal or external sources, and can be set up to detect either rising or falling edges under program control. Options Status at reset 32 33 34 35 SO1 SO2 SO3 SO4 I/O Identical to M1 through M4 Identical to M1 through M4 31 ALM Output-only pin Output • A signal modulated by ø0, ø3, or ø4 can be output under program control. IC internal reset input • The program counter is set to point to location 00H. • The reset input level can be set to be either high or low. • Either a pull-up or a pull-down resistor is built in. Note: Applications must apply the reset signal level for at least 500 µs to effect a reset. LCD panel drive outputs/general-purpose outputs • LCD panel drive (1) Static (2) 1/2 bias 1/2 duty (3) 1/2 bias 1/3 duty (4) 1/2 bias 1/4 duty (5) 1/3 bias 1/3 duty (6) 1/3 bias 1/4 duty One of items (1) through (5) is selected as a mask option. • Selection of a pull-up or pull-down resistor • Selection of active-low or active-high reset logic Low-level output 40 RES Input 44 64 1 21 Seg 22 Seg 21 Seg 22 Seg 42 • When used for LCD drive: • Switching between LCD —All lit drive output and —All off general-purpose output * Determined by the • Switching between the master options LCD drive type options • When used as general—Static purpose outputs: —1/2 bias 1/2 duty —High level —1/2 bias 1/3 duty —Low level • General-purpose output ports —1/2 bias 1/4 duty * Determined by the Output (1) CMOS output —1/3 bias 1/3 duty master options (2) p-channel open-drain output —1/3 bias 1/4 duty Note: When a (3) n-channel open-drain output • General-purpose output combination of LCD drive One of items (1) through (3) is selected as a mask option. type switching and general-purpose —CMOS outputs is selected, these • The adoption of the segment PLA in these microcontrollers —p-channel open-drain pins will be either: means that there is no need for programs to control the —n-channel open-drain All lit/high-level output, or LCD/general-purpose output states of these pins. • Standby mode output All off/low-level output. • Output latch control is supported in the oscillator stopped latch control • During the reset period, standby states and during a reset. the LCD drive functions • Any combination of LCD and general-purpose output functions as static drive. may be used. Common drive outputs for the LCD panel The table below lists which pins are used in each of the drive types. However, note that the listed alternation frequencies are the typical specifications when ø0 is 32.768 kHz. 65 66 79 80 COM1 COM2 COM3 COM4 Static COM1 Output COM2 COM3 COM4 Alternation frequency q ! ! ! 32 Hz 1/2 duty q q ! ! 32 Hz 1/3 duty q q q ! 42.7 Hz 1/4/duty q q q q 64 Hz * In products with the CF specifications, the alternation frequency signal stops briefly. Note: Note that the “!” symbol indicates that the corresponding common pin cannot be used in that drive type. Test input • In the QIP-80 version, this pin must be connected to VSS. • In the chip version, this pin must be left open or connected to VSS. Test pins. (These are not used in the device user interface.) 41 TST Input — — TEST TEST — — No. 5944-7/24 LC5824, LC5823, LC5822 Sample Application Circuit LCD : 1/2 bias — 1/4 duty No. 5944-8/24 LC5824, LC5823, LC5822 Oscillator Circuit Options Option Circuit type Notes Timing generator • The cycle time is 4 times the f1 period. • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive waveform generation clock, and for S/K port chattering prevention. • OSC1 is stopped by the execution of a SLOW instruction. Divider RC & Xtal Timing generator • The cycle time is 4 times n times the f1 period. (n:1) • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive waveform generation clock, and for S/K port chattering prevention. CF & Xtal • 400 kHz (CF) • 4 MHz (CF) Divider • OSC1 is stopped by the execution of a SLOW instruction. Timing generator • The cycle time is 4 times the f1 period. RC • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive waveform generation clock, and for S/K port chattering prevention. Divider Continued on next page. No. 5944-9/24 LC5824, LC5823, LC5822 Continued from preceding page. Option Circuit type Notes Timing generator CF • 400 kHz • 4 MHz Divider • The cycle time is 4 times n times the f1 period. (n:1) • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive frequency generation clock, and for S/K port chattering prevention. Timing generator • The cycle time is 4 times the f2 period. • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive waveform generation clock, and for S/K port chattering prevention. Xtal • 32 kHz • 55 kHz Divider Note that the CFIN and CFOUT pins are switched over to function as the P1 and P2 pins. No. 5944-10/24 LC5824, LC5823, LC5822 Crystal Oscillator Circuit Options Option Circuit type Notes Used at 32 kHz The resistor RD is built into the IC when this circuit is used at 32 kHz. • The cycle time is 4 times n times the f1 period. (n:2) Used at 38 kHz Used at 65 kHz • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive frequency generation clock, and for S/K port chattering prevention. • OSC1 is stopped by the execution of a SLOW instruction. Input Port Options Option Circuit type Notes When use of the hold transistor is selected, it is used to minimize the current drain that flows in the pull-down resistor when a pushbutton switch is used with S1 or a slide switch is used with S2. • When the input open specifications are selected, before reading the input, the pulldown transistor is turned on. Then the input state is read and the pull-down transistor is turned off. If the input was in the floating state, the low level hold transistor operates to hold the level. SF2/RF2, D2 to D7 Pull-down resistor Output mode If use of the hold transistor is not selected: • The circuit is used with the pull-down transistor turned on. • Select unused if the external control signal line connected to this input will never be in the floating state. Bus Low level hold transistor Low level hold transistor selection RES Pin Option Circuit type Notes Pull-up resistor Pull-up resistor, pull-down resistor, resistors left open, and level selections Pull-down resistor Internal resistor and polarity selections • Reset on low, pull-up resistor included • Reset on high, pull-down resistor included • Reset on low, no resistors connected • Reset on high, no resistors connected No. 5944-11/24 LC5824, LC5823, LC5822 Mask Option List Voltage specifications • Ag specifications • Li specifications • EXT-V specifications LCD driver • Static • 1/2 bias — 1/2 duty • 1/2 bias — 1/3 duty • 1/2 bias — 1/4 duty • 1/3 bias — 1/3 duty • 1/3 bias — 1/4 duty • Unused Segment port states during a reset LCD driver pins • All lit • All off CMOS p/n-channel pins • High level • Low level Oscillator specifications • CF only (ceramic oscillator element) • RC only (using a resistor and a capacitor) • Crystal only • CF + crystal • RC + crystal CF • 400 kHz • 800 kHz • 1 MHz • 2 MHz • 4 MHz RC • 400 kHz • 800 kHz • 1 MHz Crystal • 32 kHz • 65 kHz • 38 kHz LCD alternation frequency • SLOW • TYP • FAST External reset circuit • RES pin • RES pin + S1 to S4 pressed at the same time Internal reset circuit (power on reset) • Selected • Disabled RES pin • Reset on low, pull-up resistor included • Reset on high, pull-down resistor included • Reset on low, no resistors connected • Reset on high, no resistors connected Alarm output initial level • Low level • High level Chronometer and strobe selection • 00H • 10H • 00H & 10H • Unused Port S low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port K low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port M low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port P low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port SO low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port A low level hold transistors • Low level hold transistors present • Low level hold transistors disabled M1 to M4 outputs • CMOS • p-channel • n-channel P1 to P4 outputs • CMOS • p-channel • n-channel A1 to A4 outputs • CMOS • p-channel • n-channel No. 5944-12/24 LC5824, LC5823, LC5822 These electrical characteristics are provisional and the values are subject to change. Ag Specifications Absolute Maximum Ratings at Ta = 25°C ±2°C, VSS = 0 V Parameter Symbol VDD VDD1 Maximum supply voltage VDD2 VDD3 VDD3 Maximum input voltage VIN1 VOUT1 VOUT2 Operating temperature Storage temperature Topg Tstg For 1/3-bias LCD drive techniques For LCD drive techniques other than 1/3 bias S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, RES,TST M1 to M4, A1 to A4, SO1 to SO4, ALM, CUP2 (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) SEGOUT, COM1 to COM4, CUP1 Conditions and applicable pins Ratings min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –20 –30 typ max +4.0 +4.0 +5.5 +4.0 +4.0 VDD + 0.3 +0.3 VDD3 + 0.3 +65 +125 Unit V V V V V V V V °C °C Maximum output voltage Allowable Operating Ranges at Ta = 25°C ±2°C, VSS = 0 V Parameter Symbol VDD VDD1 Supply voltage VDD2 VDD3 VDD3 High-level input voltage VIH For 1/3-bias LCD drive techniques For LCD drive techniques other than 1/3 bias S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES Ta = –20 to +65°C Conditions and applicable pins VBAK = VDD1 Ratings min 1.3 2.4 3.7 2.4 VDD – 0.2 typ max 1.65 3.3 4.95 3.3 VDD V Unit V V V Low-level input voltage Operating frequency VIL fopg 0 32 0.2 33 V kHz Electrical Characteristics at Ta = 25°C ±2°C, VSS = 0 V, VDD = VDD1 Parameter Symbol RIN1A RIN1B Input resistance RIN2A RIN2B RIN3 High-level output voltage Low-level output voltage High-level output voltage VOH1 VOL1 VOH2 Conditions and applicable pins VDD = 1.5 V, Low level hold transistor VIN = 0.35 VDD *1 Figure 1 VDD = 1.5 V, Programmable pull-down resistor VIN = 0.7 VDD *1 Figure 1 VDD = 1.5 V, Low level hold transistor VIN = 0.35 VDD, Input mode *2, Figure 1 VDD = 1.5 V, Programmable pull-down resistor VIN = 0.7 VDD, Input mode *2, Figure 1 VDD = 1.5 V, The RES pin pull-up/pull-down resistor VIN = 0.7 VDD/0.3 VDD VDD = 1.3 V, IOH = –250 µA, ALM VDD = 1.3 V, IOL = 250 µA, ALM VDD = 1.5 V, M1 to 4, A1 to 4, SO1 to 4 IOH = –20 µA, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) VDD = 1.5 V, M1 to 4, A1 to 4, SO1 to 4 IOL = 20 µA, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) VDD – 0.2 Ratings min 50 50 50 50 10 VDD – 0.65 0.65 typ max 500 1000 500 1000 300 Unit kΩ kΩ kΩ kΩ kΩ V V V Low-level output voltage VOL2 0.2 V Continued on next page. No. 5944-13/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter Segment driver output impedance [When Set Up as CMOS Output Ports] High-level output voltage Low-level output voltage VOH3 VOL3 VOH3 IOFF VOH3 VOL3 VOH4 VOL4 VOH3 VOL3 VOH4 VOM VOL4 VOH3 VOL3 VOH4 VDD = 1.5 V, IOH = –3 µA, Segment 1 to 42 VDD = 1.5 V, IOL = 3 µA, Segment 1 to 42 VDD = 1.5 V, IOH = –3 µA, Segment 1 to 42 VDD = 1.5 V, VOL = VSS, Segment 1 to 42 VDD = 1.5 V, IOH = –0.4 µA, SEGOUT VDD = 1.5 V, IOL = 0.4 µA, SEGOUT VDD = 1.5 V, IOH = –4 µA, COM1 VDD = 1.5 V, IOL = 4 µA, COM1 VDD = 1.5 V, IOH = –0.4 µA, SEGOUT VDD = 1.5 V, IOL = 0.4 µA, SEGOUT VDD = 1.5 V, IOH = –4 µA, COM1 to COM2 VDD = 1.5 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM2 VDD = 1.5 V, IOL = 4 µA, COM1 to COM2 VDD = 1.5 V, IOH = –0.4 µA, SEGOUT VDD = 1.5 V, IOL = 0.4 µA, SEGOUT VDD = 1.5 V, IOH = –4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD = 1.5 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) VDD = 1.5 V, IOL = 4 µA, COM1 to 2 COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) VDD2 – 0.2 VDD1 – 0.2 VDD1 + 0.2 0.2 VDD2 – 0.2 0.2 VDD2 – 0.2 VDD1 – 0.2 VDD1 + 0.2 0.2 VDD2 – 0.2 0.2 VDD2 – 0.2 0.2 VDD2 – 0.2 0.2 0.3 VDD – 1.0 1.0 V V Symbol Conditions and applicable pins Ratings min typ max Unit [When Set Up as P-Channel Open-Drain Output Ports] High-level output voltage Output off leakage current [Static Drive] High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage [Duplex Drive (1/2 bias - 1/2 duty)] High-level output voltage Low-level output voltage High-level output voltage Middle-level output voltage Low-level output voltage V V V V V V V V V 1.0 1.0 V µA [1/2 Bias - 1/3 Duty and 1/2 Bias - 1/4 Duty Drive] High-level output voltage Low-level output voltage High-level output voltage Middle-level output voltage Low-level output voltage V V V V V VOM VOL4 [1/3 Bias - 1/3 Duty and 1/3 Bias - 1/4 Duty Drive] High-level output voltage M1-level output voltage M2-level output voltage Low-level output voltage High-level output voltage M1-level output voltage M2-level output voltage Low-level output voltage VOH3 VOM1–3 VOM2–3 VOL3 VOH4 VOM1–4 VOM2–4 VOL4 VDD = 1.5 V, IOH = –0.4 µA, SEGOUT VDD = 1.5 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD = 1.5 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD = 1.5 V, IOL = 0.4 µA, SEGOUT VDD = 1.5 V, IOH = –4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD = 1.5 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) VDD = 1.5 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) VDD = 1.5 V, IOL = 4 µA, COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) VDD3 – 0.2 VDD2 – 0.2 VDD1 – 0.2 VDD2 + 0.2 VDD1 + 0.2 0.2 VDD3 – 0.2 VDD2 – 0.2 VDD1 – 0.2 VDD2 + 0.2 VDD1 + 0.2 0.2 V V V V V V V V Continued on next page. No. 5944-14/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter [Output Voltage] LCD drive method: 1/3 bias (doubler) (tripler) LCD drive method: 1/2 bias (doubler) VDD2 VDD = 1.35 V, fopg = 32.768 kHz, C1 to C2 = 0.1 µF Figure 3 VDD = 1.5 V, In halt mode, C1 to C3 = 0.1 µF, CI = 25 kΩ, Figure 2, Co = Cg = 20 pF, 32.768 kHz Xtal VDD = 1.5 V, In halt mode, C1 = C2 = 0.1 µF, CI = 25 kΩ, Figure 3, Co = Cg = 20 pF, 32.768 kHz Xtal Co = Cg = 20 pF, CI = 25 kΩ, Figure 3, 32.768 kHz Xtal VBAK = VDD1, CI = 25 kΩ, Figures 2 and 3 Co = Cg = 20 pF, 32.768 kHz Xtal VDD = 1.35 V, CI = 25 kΩ, Figure 4, Co = Cg = 20 pF, 32.768 kHz Xtal XC XTOUT 8 16 10 20 1.3 2.5 V VDD2 VDD3 VDD = 1.35 V, fopg = 32.768 kHz, C1 to C3 = 0.1 µF Figure 2 VDD = 1.35 V, fopg = 32.768 kHz, C1 to C3 = 0.1 µF Figure 2 2.5 3.75 V V Symbol Conditions and applicable pins Ratings min typ max Unit [Current Drain (with the backup flag cleared)] LCD drive method: 1/3 bias LCD drive methods other than 1/3 bias Oscillator start voltage Oscillator hold voltage Oscillator start time Oscillator correction capacitance | IDD | | IDD | | Vstt | | VHOLD | Tstt 10P 20P 3.5 2.0 1.35 1.65 10 12 24 µA µA V V sec pF pF No. 5944-15/24 LC5824, LC5823, LC5822 Li Specifications Absolute Maximum Ratings at Ta = 25°C ±2°C, VSS = 0 V Parameter Symbol VDD VDD1 Maximum supply voltage VDD2 VDD3 VDD3 Maximum input voltage VIN1 (LCD drive method: 1/3 bias) (LCD drive methods other than 1/3 bias) S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES, TST M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) ALM, CUP2 SEGOUT, COM1 to COM4, CUP1 M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) ALM, SEGOUT, COM1 to COM4, CUP1, CUP2 VBAK = VDD1 or VDD2 Conditions and applicable pins Ratings min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 typ max +4.0 +4.0 +4.0 +5.5 +4.0 VDD + 0.3 Unit V V V V V V Maximum output voltage (LCD drive method: 1/3 bias) (LCD drive methods other than 1/3 bias) Operating temperature Storage temperature VOUT1 VOUT2 VOUT2 Topg Tstg –0.3 –0.3 –0.3 –20 –30 VDD + 0.3 VDD3 + 0.3 VDD + 0.3 +65 +125 V V V °C °C Allowable Operating Ranges at Ta = 25°C ±2°C, VSS = 0 V Parameter Symbol VDD VDD2 Supply voltage VDD VDD2 VDD3 VDD3 High-level input voltage VIH Conditions and applicable pins VBAK = VDD /2 (With the backup flag cleared) VBAK = VDD (With the backup flag uncleared) (LCD drive method: 1/3-bias) (LCD drive methods other than 1/3 bias) S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) VDD – 0.4 RES S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES Ta = –20 to +65°C 0 32 1.3 3.9 VDD3 = VDD2 VDD 3.6 5.0 V V V V Ratings min 2.0 typ max 3.6 Unit V Low-level input voltage Operating frequency VIL fopg 0.4 33 V kHz Electrical Characteristics at Ta = 25°C ±2°C, VSS = 0 V, VDD = VDD2 Parameter Symbol RIN1A RIN1B Input resistance RIN2A RIN2B RIN3 Conditions and applicable pins VDD = 3.0 V, VIN = 0.35 VDD Low level hold transistor *1, Figure 5 VDD = 3.0 V, VIN = 0.7VDD Programmable pull-down resistor *1, Figure 5 VDD = 3.0 V, input mode, Low level hold transistor *1, VIN = 0.35 VDD, Figure 5 VDD = 3.0 V, Programmable pull-down resistor, *2, VIN = 0.7 VDD, input mode, Figure 5 VDD = 3.0 V, RES pin pull-up/pull-down resistor VIN = 0.7 VDD/0.3 VDD Ratings min 50 50 50 50 typ max 500 1000 500 1000 Unit kΩ kΩ kΩ kΩ kΩ 10 300 No. 5944-16/24 LC5824, LC5823, LC5822 Electrical Characteristics at Ta = 25°C ±2°C, VSS = 0 V, VDD = VDD2 Parameter High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Segment driver output impedance [When Set Up as CMOS Output Ports] High-level output voltage Low-level output voltage VOH3 VOL3 VOH3 IOFF VOH3 VOL3 VOH4 VOL4 VOH3 VOL3 VOH4 VOM VOL4 VOH3 VOL3 VOH4 VOM VDD = 3.0 V, IOH = –5 µA, Segment 1 to 42 VDD = 3.0 V, IOL = 5 µA, Segment 1 to 42 VDD = 2.5 V, IOH = –10 µA, Segment 1 to 42 VDD = 3.0 V, VOL = VSS VDD = 3.0 V, IOH = –0.4 µA, SEGOUT VDD = 3.0 V, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –4 µA, COM1 VDD = 3.0 V, IOL = 4 µA, COM1 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT VDD = 3.0 V, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –4 µA, COM1 to COM2 VDD = 3.0 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM2 VDD = 3.0 V, IOL = 4 µA, COM1 to COM2 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT VDD = 3.0 V, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD = 3.0 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD = 3.0 V, IOL = 4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD – 0.2 VDD1 – 0.2 VDD1 + 0.2 VDD – 0.2 0.2 VDD – 0.2 VDD1 – 0.2 VDD1 + 0.2 0.2 VDD – 0.2 0.2 VDD – 0.2 0.2 VDD – 0.2 0.2 0.3 VDD – 1 1 V V Symbol VOH1 VOL1 VOH2 VOL2 Conditions and applicable pins VDD = 2.5 V, IOH = –250 µA, ALM VDD = 2.5 V, IOL = 250 µA, ALM VDD = 3.0 V, IOH = –40 µA, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) VDD = 3.0 V, IOL = 40 µA, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) VDD – 0.4 0.4 Ratings min VDD – 0.65 0.65 typ max Unit V V V V [When Set Up as P-Channel Open-Drain Output Ports] High-level output voltage Output off leakage current [Static Drive] High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage [Duplex Drive (1/2 bias - 1/2 duty)] High-level output voltage Low-level output voltage High-level output voltage Middle-level output voltage Low-level output voltage V V V V V V V V V 1 1 V µA [1/2 Bias - 1/3 Duty and 1/2 Bias - 1/4 Duty Drive] High-level output voltage Low-level output voltage High-level output voltage V V V Middle-level output voltage V Low-level output voltage VOL4 0.2 V Continued on next page. No. 5944-17/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter Symbol Conditions and applicable pins Ratings min typ max Unit [1/3 Bias - 1/3 Duty and 1/3 Bias - 1/4 Duty Drive] High-level output voltage M1-level output voltage M2-level output voltage Low-level output voltage High-level output voltage VOH3 VOM1–3 VOM2–3 VOL3 VOH4 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD = 3.0 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD = 3.0 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD = 3.0 V, IOL = 4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD3 – 0.2 VDD3 – 0.2 VDD2 – 0.2 VDD1 – 0.2 VDD2 + 0.2 VDD1 + 0.2 0.2 V V V V V M1-level output voltage VOH1–4 VDD2 – 0.2 VDD2 + 0.2 V M2-level output voltage VOM2–4 VDD1 – 0.2 VDD1 + 0.2 V Low-level output voltage [Output Voltage] LCD drive method: 1/3 bias (halver) (tripler) LCD drive method: 1/2 bias (halver) VOL4 0.2 V VDD1 VDD3 VDD = 3.0 V, fopg = 32.768 kHz, C1 to C4 = 0.1 µF, Figure 6 VDD = 3.0 V, fopg = 32.768 kHz, C1 to C4 = 0.1 µF, Figure 6 1.35 4.1 V V VDD1 VDD = 3.0 V, fopg = 32.768 kHz, C1 = C2 = 0.1 µF, Figure 7 1.35 V [Current Drain (With the backup flag cleared)] LCD drive method: 1/3 bias | IDD | VDD = 3.0 V, Halt mode C1 to C4 = 0.1 µF, C1 = 25 kΩ, Figure 6 Co = Cg = 20 pF, 32.768 kHz Xtal VDD = 3.0 V, Halt mode C1 = C2 = 0.1 µF, CI = 25 kΩ, Figure 7 Co = Cg = 20 pF, 32.768 kHz Xtal VDD1 = VDD, CI = 25 kΩ, Figure 4 Co = Cg = 20 pF, 32.768 kHz Xtal VBAK = VDD1 = VDD/2, CI = 25 kΩ, Figures 6 and 7 Co = Cg = 20 pF, 32.768 kHz Xtal VDD1 = VDD = 1.35 V, CI = 25 kΩ, Figure 4 Co = Cg = 20 pF, 32.768 kHz Xtal XC XTOUT 8 16 10 20 2.6 10 12 24 2.0 µA LCD drive methods other than 1/3 bias Oscillator start capacitor Oscillator hold voltage (with the backup flag cleared) Oscillator start time Oscillator correction capacitance | IDD | 1.0 µA | Vstt | VHOLD Tstt 10P 20P 1.35 V V sec pF pF No. 5944-18/24 LC5824, LC5823, LC5822 EXT-V Specifications Absolute Maximum Ratings at Ta = 25°C ±2°C, VSS = 0 V Parameter Symbol VDD VDD1 Maximum supply voltage VDD2 VDD3 VDD3 Maximum input voltage VIN2 (LCD drive method: 1/3 bias) (LCD drive methods other than 1/3 bias) S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES, TST M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) ALM, CUP2 SEGOUT, COM1 to COM4, CUP1 M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) ALM, SEGOUT, COM1 to COM4, CUP1 Conditions and applicable pins Ratings min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 typ max +4.0 +4.0 +4.0 +5.5 +4.0 VDD + 0.3 Unit V V V V V V Maximum output voltage (LCD drive method: 1/3 bias) VOUT2 VOUT3 –0.3 –0.3 –0.3 –20 –30 VDD + 0.3 VDD3 + 0.3 VDD + 0.3 +65 +125 V V V °C °C (LCD drive methods other than 1/3 bias) Operating temperature Storage temperature VOUT2 Topg Tstg Allowable Operating Ranges at Ta = 25°C ±2°C, VSS = 0 V Parameter Symbol VDD1 Supply voltage VDD VDD2 VDD3 VDD3 High-level input voltage VIH (LCD drive method: 1/3-bias) (LCD drive methods other than 1/3 bias) S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES Ta = –20 + 65°C Conditions and applicable pins Ratings min 1.3 2.0 3.9 VDD3 = VDD2 VDD – 0.4 VDD typ max 3.6 3.6 5.0 Unit V V V V V Low-level input voltage Operating frequency VIL fopg 0 32 0.4 33 V kHz Electrical Characteristics at Ta = 25°C ±2°C, VSS = 0 V, VDD = VDD2 Parameter Symbol RIN1A RIN1B Input resistance RIN2A RIN2B RIN3 Conditions and applicable pins VDD = 3.0 V, VIN = 0.35 VDD, Low level hold transistor *1, Figure 5 VDD = 3.0 V, VIN = 0.7 VDD, Programmable pull-down resistor *1, Figure 5 VDD = 3.0 V, VIN = 0.35 VDD, Input mode, Low level hold transistor *1, Figure 5 VDD = 3.0 V, VIN = 0.7 VDD, input mode, Programmable pull-down resistor *2, Figure 5 VDD = 3.0 V, VIN = 0.7 VDD/0.3 VDD RES pin pull-up/pull-down resistor Ratings min 50 50 50 50 10 typ max 500 1000 500 1000 300 Unit kΩ kΩ kΩ kΩ kΩ Continued on next page. No. 5944-19/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Segment driver output impedance [When Set Up as CMOS Output Ports] High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage VOH3 VOL3 VOH4 VOL4 VOH3 IOFF VOH5 VOL5 VOH6 VOL6 VOH5 VOL5 VOH6 VOM VOL6 VOH5 VOL5 VOH6 VDD = 2.4 V, IOH = –10 µA, Segment 1 to 42 VDD = 2.4 V, IOL = 40 µA VDD = 2.4 V, IOH = –5 µA, Segment 1 to 42 VDD = 2.4 V, IOL = 20 µA VDD = 2.4 V, IOH = –10 µA, Segment 1 to 42 VDD = 2.6 V, VOL = VSS VDD = 3.0 V, IOH = –0.4 µA, SEGOUT VDD = 3.0 V, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –4 µA, COM1 VDD = 3.0 V, IOL = 4 µA, COM1 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT VDD = 3.0 V, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –4 µA, COM1 to COM2 VDD = 3.0 V IOH = –4 µA, IOL = 4 µA, COM1 to COM2 VDD = 3.0 V, IOL = 4 µA, COM1 to COM2 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT VDD = 3.0 V, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD = 3.0 V IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD = 3.0 V, IOL = 4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD2 – 0.2 VDD – 0.2 0.2 VDD1 – 0.2 VDD1 + 0.2 0.2 VDD2 – 0.2 0.2 VDD – 0.2 0.2 VDD – 0.2 0.2 VDD – 0.2 0.3 VDD – 1 1 VDD – 1 1 V V V V Symbol VOH1 VOL1 VOH2 VOL2 Conditions and applicable pins VDD = 2.5 V, IOH = –250 µA, ALM VDD = 2.5 V, IOL = 250 µA, ALM VDD = 3.0 V, IOH = –40 µA, M1 to M4, A1 to A4, SO1 to SO4 (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) VDD = 3.0 V, IOL = 40 µA, M1 to M4, A1 to A4, SO1 to SO4 (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) VDD – 0.4 0.4 Ratings min VDD – 0.65 0.65 typ max Unit V V V V [When Set Up as P-Channel Open-Drain Output Ports] High-level output voltage Output off leakage current [Static Drive] High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage [Duplex Drive (1/2 bias - 1/2 duty)] High-level output voltage Low-level output voltage High-level output voltage Middle-level output voltage Low-level output voltage V V V V V V V V V 1 1 V µA [1/2 Bias - 1/3 Duty and 1/2 Bias - 1/4 Duty Drive] High-level output voltage Low-level output voltage High-level output voltage V V V Middle-level output voltage VOM VDD1 – 0.2 VDD1 + 0.2 V Low-level output voltage VOL6 0.2 V Continued on next page. No. 5944-20/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter Symbol Conditions and applicable pins Ratings min typ max Unit [1/3 Bias - 1/3 Duty and 1/3 Bias - 1/4 Duty Drive] High-level output voltage Middle-level output voltage Low-level output voltage High-level output voltage VOH5 VOM1–5 VOM2–5 VOL5 VOH6 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOL = 0.4 µA, SEGOUT VDD = 3.0 V, IOH = –0.4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD = 3.0 V, IOL = 0.4 µA VDD3 + 0.2 VDD3 + 0.2 VDD2 – 0.2 VDD1 – 0.2 VDD2 + 0.2 VDD1 + 0.2 0.2 V V V V V VOM1–6 Middle-level output voltage VOM2–6 Low-level output voltage [Output Voltage] LCD drive method: 1/3 bias (halver) (tripler) LCD drive method: 1/2 bias (halver) VDD1 VDD1 VDD3 VOL6 VDD2 – 0.2 VDD2 + 0.2 V VDD1 – 0.2 VDD1 + 0.2 0.2 V V VDD = 3.0 V, fopg = 32.768 kHz, C1 to C4 = 0.1 µF, Figure 6 VDD = 3.0 V, fopg = 32.768 kHz, C1 to C4 = 0.1 µF, Figure 6 1.35 4.1 V V VDD = 3.0 V, fopg 32.768 kHz, C1 = C2 = 0.1 µF, Figure 7 VDD = 3.0 V, Halt mode, C1 to C4 = 0.1 µF, CI = 25 kΩ Co = Cg = 20 pF, 32.768 kHz Xtal, Figure 6 VDD = 3.0 V, Halt mode, C1 to C2 = 0.1 µF, CI = 25 kΩ, Figure 7, Co = Cg = 20 pF, 32.768 kHz, Xtal VDD = VDD2, CI = 25 kΩ, Figure 4, Co = Cg = 20 pF, 32.768 kHz Xtal VDD = VDD2, CI = 25 kΩ, , Figures 5, 6, 7, and 8, Co = Cg = 20 pF, 32.768 kHz Xtal VDD = VDD2 = 2.2 V, CI = 25 kΩ, Figure 4 Co = Cg = 20 pF, 32.768 kHz Xtal XC XTOUT 1.35 V [Current Drain (With the backup flag cleared)] LCD drive method: 1/3 bias LCD drive methods other than 1/3 bias Oscillator start voltage Oscillator hold voltage (with the backup flag cleared) Oscillator start time Oscillator correction capacitance Note : 1. S1 to 4, K1 to 4 2. M1 to 4, A1 to 4, SO1 to 4 | IDD | | IDD | Vstt VHOLD Tstt 10P 20P 5.0 5.0 2.2 2.0 µA µA V V 10 8 16 10 20 12 24 sec pF pF No. 5944-21/24 LC5824, LC5823, LC5822 Can be applied by application software Figure 1 S1 to S4, K1 to K4, M1 to M4, A1 to A4, and SO1 to SO4 Figure 2 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit Figure 3 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit No. 5944-22/24 LC5824, LC5823, LC5822 Figure 4 Oscillator Start Voltage, Oscillator Start Time, and Frequency Stability Test Circuit Can be applied by application software Figure 5 S1 to S4, K1 to K4, M1 to M4, A1 to A4, and SO1 to SO4 Figure 6 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit No. 5944-23/24 LC5824, LC5823, LC5822 Figure 7 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit Figure 8 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any and all SANYO products described or contained herein fall under strategic products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of Japan, such products must not be exported without obtaining export license from the Ministry of International Trade and Industry in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. T his catalog provides information as of August, 1998. Specifications and information herein are subject to change without notice. PS No. 5944-24/24