LC6528L

Ordering number : EN5894 CMOS IC LC65P29 One-Time Programmable 4-Bit Single-Chip Microcontroller Overview The LC65P29 is a one-time programmable (on-chip PROM) version of Sanyo's LC6529N/F/L 4-bit single-chip CMOS microcontroller. It provides identical functionality to, and pin compatibility with, the mask ROM versions of the LC6529N/F/L, and provides a 1-KB internal PROM. The LC65P29 is provided in DIP24S and MFP30S plastic packages and the program can be written by the customer, thus makes this IC appropriate for the limited-run products and the startup of initial production of new products. Furthermore, it can provide reduced changeover periods when end product specifications change. Additionally, the LC65P29 can function as a one-time programmable PROM version of the Sanyo LC6527N/F/L and LC6528N/F/L by using the 29T27 adapter socket. Package Dimensions unit: mm 3067-DIP24S(300mil) [LC65P29] Features • Mask option settings can be switched by setting PROM data. All options, except for the port output circuit type can be set with PROM data. • 1-KB PROM • PROM data security function • Pin compatible with the mask ROM version • Instruction cycle time: 0.92 µs to 20 µs • Packages: DIP24S and MFP30S unit: mm 3216-MFP30S(375mil) [LC65P29] SANYO: DIP24S(300mil) SANYO: MFP30S(375mil) Note: The package dimension figures are provide for reference purposes without dimensional tolerances. Contact your Sanyo representative for the official package dimension figures. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 61298RM (OT) No. 5894-1/14 LC65P29 Notes on Sanyo ROM Writing Services Sanyo provides a for-fee ROM writing service that consists of writing the one-time programmable ROM , printing, screening, and readout verification. Contact your Sanyo representative for details. Pin Assignments DIP24S MFP30S Top view Top view Product Series Structure Type number. LC6527N/F/L, LC6528N/F/L LC6529N/F/L LC65E29 LC65P29 LC6543N/F/L, LC6546N/F/L LC65E43 LC65P43 LC651104N/F/L, LC651102N/F/L LC651204N/F/L, LC651202N/F/L LC65E1104 LC65P1104 Number of pins 18 24/30 24/30 24/30 30 30 30 30 30 30 30 ROM capacity 1K, 0.5K 1K 1K 1K 2K, 1K 2K 2K 4K, 2K 4K, 2K 4K 4K RAM capacity 64W, 32W 64W 64W 64W 128W, 64W 128W, 64W 128W, 64W 256W 256W 256W 256W Package DIP18, MFP18 DIP24S, SSOP24, MFP30S DIC24S, MFC30S DIP24S, MFP30S DIP30S, MFP30S DIC30S, MFC30S DIP30S, MFP30S DIP30S, MFP30S DIP30S, MFP30S DIC30S, MFC30S DIP30S, MFP30S No. 5894-2/14 LC65P29 Usage Notes The LC65P29 is designed for program development and evaluation for systems that use the LC6529N/F/L. The following points require attention when using this product. • Mounting notes Due to the nature of the device, one-time programmable microcontrollers cannot be fully tested prior to shipment. This means that users must perform the screening process described on page 14. • ROM ordering procedure when using the Sanyo for-fee ROM writing service The customer must abide by the following when using the Sanyo for-fee ROM writing service: — When ordering both one-time programmable and mask versions at the same time The customer must provide an EPROM for the mask version, the mask version order forms, and the one-time programmable version order forms. — When order only the one-time programmable version The customer must provide an EPROM for the one-time programmable version and the one-time programmable version order forms. The end area in the EPROM (locations 400 to 404H) is the option specification area and the customer must program the option specification data in that area. The customer must use the cross assembler specified by Sanyo. • Differences between the LC65P29 and the LC6529N/F/L Parameter Ports C and D output option during reset Port output type during reset Oscillator circuit option Option Divider circuit option Comparator input and port E input option Comparator function option LC65P29 High or low can be specified (option code) Open-drain output only (ports A, C, and D) CF/RC or EXT can be specified (option code) 1/1, 1/3, or 1/4 can be specified (option code) Comparator or port E can be specified (option code) Feedback resistor present or absent can be specified (option code) 0.92 µs (VDD ≥ 3.0 V) –30 to +70°C 3.0 to 6.0 V 5.0 mA typ. –50 µA typ. 3.0 to 6.0 V 2.0 mA typ. LC6529N LC6529F High or low can be specified (mask option) Open-drain or pull-up register can be specified (mask option) CF/RC or EXT can be specified (mask option) 1/1,1/3 or 1/4 can be specified (mask option) CF or EXT can be specified (mask option) Only 1/1 is possible (mask option) CF/RC or EXT can be specified (mask option) 1/1,1/3 or 1/4 can be specified (mask option) LC6529L Comparator or port E can be specified (mask option) Feedback resistor present or absent can be specified (mask option) 2.77 µs (VDD ≥ 3.0 V) 0.92 µs (VDD ≥ 3.0 V) –40 to +85°C 3.0 to 6.0 V 2.5 mA typ. –10 µA typ. 2.2 to 6.0 V 2.0 mA typ. 3.84 µs (VDD ≥ 2.2 V) Minimum cycle time Characteristic Other items Operating temperature Supply voltage Current drain Reset port input low-level current Package DIP24S, MFP30S DIP24S, SSOP24, MFP30S No. 5894-3/14 LC65P29 System Block Diagram A0 to A9 to D0 to D7 to to to RAM: Data memory ALU: Arithmetic and logic unit DP: Data pointer E: E register AC: Accumulator OSC: Oscillator circuit TM: Timer STS: Status register EPROM: Program memory PC: Program counter I.R: Instruction register I.DEC: Instruction decoder CF: Carry flag ZF: Zero flag TMF: Timer overflow flag No. 5894-4/14 LC65P29 Pin Descriptions Pin name VDD VSS Number of pins 1 1 I/O — — Function Power supply. Must be connected to +5 V during normal operation. Power supply. Must be connected to 0 V during normal operation. 1.Two-pin RC oscillator (Single-pin external clock input) 2.Two-pin ceramic oscillator 3.Divisor option: 1/1, 1/3, or 1/4 Option State during reset Function in PROM mode — — OSC1/CE OSC2/TA 1 I O System clock oscillator connections. Leave OSC2 open and input the external clock to OSC1 if an external clock is used. EPROM contorol signal inputs CE TA PA0/A6 PA1/A7 PA2/A8 PA3/A9 4 I/O • I/O ports A0 to A3 Input in 4-bit units (IP instruction) Output in 4-bit units (OP instruction) Data testing in 1-bit units (BP and BNP instructions) Data set and clear operations in 1-bit units Open-drain output (SPB and RPB instructions) • PA3 is used for standby mode control. • Applications must assure that chattering (key bounce) noise is not input during a HALT instruction execution cycle. • I/O ports C0 to C3 1. Open-drain output The pin functions are identical to those of 2. High-level output pins A0 to A3. during reset However, there is no standby mode 3. Low-level output control function. during reset • The output during a reset can be specified • Selection of items 2 or to be either high or low as an option. 3 is in 4-bit units. • I/O ports D0 to D3 The pin functions are identical to those of pins PC0 to PC3. • When comparator input is selected: CMP0 and CMP1 use VREF0 as the reference voltage, CMP2 and CMP3 use VREF1 as the reference voltage, • Comparator inputs CMP0 to CMP3 Data input in 4-bit units (IP instruction) • Data testing in 1-bit units (BP and BNP instructions) • When input is selected for port E • Input ports E0 to E3 Input in 4-bit units (IP instruction) • Data testing in 1-bit units (BP and BNP instructions) • Comparator reference voltage inputs VREF0 and VREF1 VREF0 is the reference voltage input for CMP0 and CMP1. VREF1 is the reference voltage input for CMP2 and CMP3. • When PE0/CMP0 to PE3/CMP3 are selected to function as port E inputs, these pins are connected to VSS. • System reset input • Connect an external capacitor to effect the power-on reset. • Input a low level for at least 4 clock cycles to effect a reset restart. • IC test pin This pin must be connected to VSS during normal operation. • High-level output (The n-channel output transistor turned off.) • Address inputs A6 to A9 PC0/D0 PC1/D1 PC2/D2 PC3/D3 4 I/O • High-level output • Low-level output (Depending on an option selection.) • Data I/O D0 to D3 PD0/D4 PD1/D5 PD2/D6 PD3/D7 4 I/O The same as for pins PC0 to PC3 The same as pins PC0 to • Data I/O PC3 D4 to D7 4 PE0/CMP0/A0 PE1/CMP1/A1 PE2/CMP2/A2 PE3/CMP3/A3 I 1. 2. 3. 4. 4 I Comparator input Port E input No feedback resistor Feedback resistor present • Selection of items 1 or 2 is in 4-bit units. • Items 3 and 4 are only specified when item 1 is selected. • Address inputs A0 to A3 VREF0/A4 VREF1/A5/ DASEC 2 I • Address inputs A4 and A5 • EPROM control signal input DASEC RES/VPP/OE 1 I • EPROM control signal input VPP/ OE TEST/EPMOD 1 I • EPROM control signal input EPMOD No. 5894-5/14 LC65P29 User Options • Ports C and D output level during reset option One of the following two options for the output level during a reset can be selected for each of the ports C and D in 4-bit units. Option High-level output at reset Low-level output at reset Conditions and notes Ports C and D in 4-bit units Ports C and D in 4-bit units • Port output circuit type option The I/O ports A, C, and D are always set up as open-drain outputs. Option Circuit Open-drain output (OD) • Oscillator circuit options Option Circuit Conditions and notes External clock The OSC2 pin must be left open. Two-pin RC oscillator Two-pin ceramic oscillator • Divisor option Option Circuit Conditions and notes No divisor (1/1) Can be used with any of the 3 oscillator options. (N, F, and L versions) Divide-by-3 circuit (1/3) Can only be used with the external clock and ceramic oscillator options. (N and L versions) Divide-by-4 circuit (1/4) Can only be used with the external clock and ceramic oscillator options. (N and L versions) No. 5894-6/14 LC65P29 • Comparator input/port E input option Whether the 4 port pins PE0/CMP0, PE1/CMP1, PE2/CMP2, and PE3/CMP3 function as comparator inputs or as port E inputs can be selected. Option Comparator inputs Port E inputs Conditions and notes All 4 bits specified together All 4 bits specified together • Comparator function option One of two options relating to the comparator function can be selected. Option Circuit Conditions and notes No feedback resistor The comparator can be used without hysteresis. Feedback resistor present When used with an added external resistor, the comparator can be used with hysteresis. Usage Procedures • Option specification procedures User options can be selected interactively by running the LC6529 option entry software (SU60K). This creates an option file (file.opt). Assembling the user program with the macro assembler (M60K) creates an object file. An evaluation file (file.eva) can be created by linking the object file and the option file with the linker (L60K). Then, a HEX format object file, which includes both the user program and the mask options, can be created by converting the evaluation file with the file conversion software (E2H60K). This creates the option codes in the option specification area (locations 400 to 404H). It is also possible to store data directly to the option specification area. Refer to the option code creation table on page 9 to do this. Refer to the “LC65/66K Software Manual” for details. • EPROM programming procedure A general-purpose EPROM programmer can be used to write the created data to the LC65P29 by using a specialpurpose write conversion board (either the W65EP29D or the W65EP29M). — The EPROM programmers listed below can be used. Manufacturer ADVANTEST ANDO AVAL MINATO Electronics Models that can be used R4945, R4944A, R4943 or equivalent — — — — The “27512 (VPP: 12.5 V) Intel fast write” method must be used for writing. Specify locations 0 to 404 as the address settings, and make sure that the DASEC jumper is in the off position. • Using the data security function The data security function is a function that prevents data written previously to the microcontroller EPROM from being read out. Use the following procedure to apply the data security to the LC65P29. 1. Set the DASEC jumper on the write conversion board to the on position. 2. Write the data once again. At this point, the EPROM writer will indicate an error since this function has operated, but actually, no error has occurred in either the programmer or the IC. Notes: • The data security function will not be applied if the data value FF is written to all address in step 2. • The data security function will not be applied if the sequence BLANK → PROGRAM → VERIFY is performed at step 2. • Always return the jumper to the off position after performing this procedure. No. 5894-7/14 LC65P29 LC65P29 (DIP24S) LC65P29 (MFP30S) Pin 1 Pin 1 Insert the LC65P29 into the socket correctly SW DASEC W65EP29D SW DASEC W65EP29M Pin 1 Pin 1 DASEC setting • For normal writing • For writing with the security function applied No. 5894-8/14 LC65P29 • Option data area and definition Bits specified to be 0 must be set to 0. Oscillator type specification 00 ... Illegal value 01 ... Illegal value 10 ... Two-pin RC oscillator, 1-pin external drive (2PORT RC OSC, 1PORT EXT) 11 ... Two-pin ceramic oscillator (2PORT CF OSC) Oscillator divider specification 00 1/1 (direct) 01 1/3 10 1/4 11 ... Illegal value Port C output level at initial reset 0 Low-level output 1 High-level output Port D output level at initial reset 0 Low-level output 1 High-level output Comparator function specification 0 No feedback resistor 1 Feedback resistor present Port input function specification 0 Comparator input 1 Port E input Port A output type specification Port C output type specification 0 Open-drain output 1 Pull-up resistor output 0 Open-drain output 1 Pull-up resistor output These bits must be set to 0. Port D output type specification 0 Open-drain output 1 Pull-up resistor output Port C output type specification 0 Open-drain output 1 Pull-up resistor output These bits must be set to 0. These bits must be set to 0. Note: Although all ports are set up to be open-drain outputs regardless of the port option data in the LC65P29, be sure to specify the port option data if you are using the LC6529N/F/L (mask ROM version). No. 5894-9/14 LC65P29 Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Output voltage Symbol VDD max VO VI1 Input voltage VI2 VI3 I/O voltage Peak output current VIO IOP IOA Average output current Σ IOA1 Σ IOA2 Allowable power dissipation Operating temperature Storage temperature Pdmax1 Pdmax2 Topr Tstg Applicable pins/notes VDD OSC2 OSC1*1 TEST, RES Ports with PE specifications PA, PC, PD PA, PC, PD PA, PC, PD PA PC, PD The 100 ms average per pin The total current for pins PA0 to PA3*2 The total current for pins PC0 to PC3 and PD0 to PD3*3 Ta = –30 to +70°C(DIP24S) Ta = –30 to +70°C(MFP30S) –30 –55 Conditions Ratings min –0.3 typ max +7.0 Unit V V V V V mA mA mA mA mA mW mW °C °C Values up to the generated voltage are allowed. –0.3 –0.3 –0.3 –0.3 –2 –2 –6 –14 VDD + 0.3 VDD + 0.3 VDD + 0.3 +15 +20 +20 +40 +90 360 150 +70 +125 Notes: 1. Values up to the generated oscillator amplitude are allowed when driven internally using the guaranteed circuit constant values with the oscillator circuit shown in figure 2. 2. The average over a 100 ms period. Allowable Operating Conditions at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 6.0 V Parameter Operating supply voltage Standby supply voltage Symbol VDD VST VIH1 VIH2 High-level input voltage VIH3 VIH4 VIL1 VIL2 Low-level input voltage VIL3 VIL4 VIL5 Operating frequency (cycle time) Guaranteed oscillator External clock conditions circuit constants Frequency Pulse width Rise and fall times fop(tCYC) fext(text) OSC1 See Figure 1 See Figure 1 See Figure 1 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 4 to 6 4 to 6 220 ±5% 220 ±5% 6.8 ±1% 15.0 ±1% See Table 1 RES OSC1 PA, PC, PD PE OSC1 TEST RES When the RC oscillator and external clock option is selected Output n-channel transistor off When the port E input option is selected When the RC oscillator and external clock option is selected Applicable pins/notes VDD VDD PA, PC, PD PE RAM and register retention * Output n-channel transistor off When the port E input option is selected 1.8 to6.0 Conditions Ratings VDD [V] min 3.0 1.8 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS 200 (20) 200 (20) 69 50 typ max 6.0 6.0 13.5 VDD VDD VDD 0.3 VDD 0.3 VDD 0.25 VDD 0.3 VDD 0.25 VDD Unit V V V V V V V V V V V 4330 (0.92) kHz (µs) 4330 (0.92) kHz (µs) ns ns pF pF kΩ kΩ textH, textL OSC1 textR, textF OSC1 Cext OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 Two-pin RC oscillator Cext Rext Rext Ceramic oscillator Note *: Applications must maintain the operating supply voltage (VDD) until the IC has entered the standby state when a HALT instruction is executed. Also, applications must assure that chattering (key bounce) noise is not input to the PA3 pin during a HALT instruction execution cycle. No. 5894-10/14 LC65P29 Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 6.0 V Parameter Symbol Applicable pins/notes Conditions Output n-channel transistor off (Includes the n-channel transistor off leakage current) VIN = 13.5 V When the port E input option is selected VIN = VDD When the RC oscillator and external clock option is selected VIN = VDD Output n-channel transistor off (Includes the n-channel transistor off leakage current) VIN = VSS When the port E input option is selected VIN = VSS VIN = VSS When the RC oscillator and external clock option is selected VIN = VSS IOL = 10 mA IOL = 1.8 mA (When all port I/O levels are Under 1 mA) 0.1 VDD When the RC oscillator and external clock option is selected Figure 2. 850 kHz (TYP) Figure 2. 400 kHz (TYP) Figure 3. 4 MHz, 1/1, 1/3, and 1/4 divisor ratios Figure 3. 2 MHz, 1/1, 1/3, and 1/4 divisor ratios Figure 3. 800 kHz, 1/1 divisor ratio Figure 3. 400 kHz, 1/1 divisor ratio 200 to 4330 kHz, 1/1, 1/3, and 1/4 divisor ratios Output n-channel transistor off Port = VDD Output n-channel transistor off Port = VDD Figure 2. Cext = 220 pF ±5% Rext = 15.0 kΩ ±1% Figure 2. Cext = 220 pF ±5% Rext = 6.8 kΩ ±1% Figure 3. fo = 4 MHz Figure 3. fo = 2 MHz Figure 3. fo = 800 kHz Figure 3. fo = 400 kHz Figure 4. fo = 4 MHz Oscillator stabilization time tCFS Figure 4. fo = 2 MHz fo = 800 kHz fo = 400 kHz VIN = VSS 5 70 100 See Figure 6. f = 1 MHz VIN = VSS for all input pins other than the measured pin 4 to 6 6 3 275 579 3840 1920 768 384 0.1 VDD 5 4.5 5 4.5 5 4.5 5 8 7 8 7 8 7 8 Ratings VDD [V] min typ max Unit IIH1 High-level input current PA, PC, PD 5.0 µA IIH2 IIH3 PE 5.0 µA OSC1 1.0 µA IIL1 Low-level input current PA, PC, PD –1.0 µA IIL2 IIL3 IIL4 VOL1 PE RES OSC1 PA, PC, PD PA, PC, PD RES OSC1*1 VDD VDD VDD VDD VDD VDD VDD VDD VDD OSC1, OSC2 –1.0 –80 –1.0 1.5 0.4 –50 µA µA µA V V V V mA mA mA mA mA mA mA Low-level output voltage VOL2 VHIS1 Hysteresis voltage VIHS2 IDDOP1 IDDOP2 IDDOP3 IDDOP4 RC oscillator Current drain Ceramic oscillator*2 IDDOP5 IDDOP6 External clock*2 IDDOP7 IDDst1 0.05 0.025 400 850 4000 2000 800 400 10 5 711 1179 4160 2080 832 416 10 10 150 µA µA kHz kHz kHz kHz kHz kHz ms ms kΩ ms Standby mode IDDst2 RC oscillator Oscillator frequency fMOSC OSC1, OSC2 OSC1, OSC2 Oscillator characteristics Ceramic oscillator OSC1, OSC2 Oscillator frequency fFOSC*3 OSC1, OSC2 OSC1, OSC2 Pull-up resistor reset port External reset characteristics: reset time Pin capacitance Ru tRST Cp 10 pF Notes: 1. The OSC1 pin has Schmitt characteristics when the RC oscillator and external clock input oscillator option is selected. 2. The current drain during normal operation with the output n-channel transistors off and the port at VDD. 3. fCFOSC indicates frequencies at which oscillator operation is possible. No. 5894-11/14 LC65P29 Comparator characteristics (When the comparator input option is selected) at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 6.0 V Parameter Reference input voltage range Common-mode input voltage range Offset voltage Response speed Symbol VRFIN VCMIN VOFF TRS1 TRS2 IIH1 High-level input current IIH2 IIL1 Low-level input current IIL2 RCMFB VREF0, 1 CMP0 to 3 VREF0, 1 CMP0 to 3 CMP0 to 3 When the feedback resistor option is not selected When the feedback resistor option is selected When the feedback resistor option is not selected –1.0 –1.0 460 Applicable pins/notes VREF0, 1 CMP0 to 3 VCMIN = VSS to VDD – 1.7 V See Figure 5. See Figure 5. 4 to 6 Conditions Ratings VDD [V] min VSS + 0.3 VSS ±50 1.0 1.0 typ max VDD – 1.7 VDD – 1.7 ±300 5.0 200 1.0 5.0 Unit V V mV µs µs µA µA µA µA kΩ Feedback resistance Table 1 Guaranteed Ceramic Oscillator Circuit Constants Standard type Oscillator type 4 MHz Manufacturer Murata Mfg. Co., Ltd. Oscillator element C1 C2 33 pF ±10% 33 pF ±10% 33 pF ±10% 47 pF ±10% Rd — — — — Manufacturer Murata Mfg. Co., Ltd. — Murata Mfg. Co., Ltd. — — — — — — Kyocera Corporation — Kyocera Corporation Chip type Oscillator element CSAC4.00MGC — CSAC2.00MGC — — — — — — KBR-4.0MWS — KBR-2.0MWS C1 33 pF ±10% — 33 pF ±10% — — — — — — — — — C2 33 pF ±10% — 33 pF ±10% — — — — — — — — — CSA4.00MG 33 pF ±10% External capacitor type Kyocera Corporation KBR-4.0MSA 33 pF ±10% Murata Mfg. Co., Ltd. CSA2.00MG 33 pF ±10% 2 MHz Kyocera Corporation KBR-2.0MS 47 pF ±10% Murata Mfg. Co., Ltd. CSB800J 800 kHz 100 pF ±10% 100 pF ±10% 3.3 KΩ — 220 pF ±10% 220 pF ±10% 3.3 KΩ — — — — — — — — — — — — — Kyocera Corporation KBR-800F/Y 150 pF ±10% 150 pF ±10% Murata Mfg. Co., Ltd. CSB400P 400 kHz Kyocera Corporation KBR-400BK/Y 330 pF ±10% 330 pF ±10% Murata Mfg. Co., Ltd. CST4.00MGW Internal capacitor type 4 MHz Kyocera Corporation KBR-4.0MKS Murata Mfg. Co., Ltd. — CST2.00MG — 2 MHz Figure 1 External Clock Input Waveform No. 5894-12/14 LC65P29 Figure 2 Two-Pin RC Oscillator Circuit Figure 3 Ceramic Oscillator Circuit Figure 4 Oscillator Stabilization Time Figure 5 Comparator Response Speed TRS Timing Note: The reset period due to a CRES with a value of 0.68 µF will be 10 to 100 ms when the power supply rise time is zero. If the power supply rise time is relatively long, increase the value of CRES so that the reset time is at least 10 ms, which is the oscillator stabilization time. Figure 6 Reset Circuit No. 5894-13/14 LC65P29 Notes on Mounting Preconditions for One-Time Programmable Microcontrollers This product is provided in both DIP and MFP packages. Since the mounting preconditions are different for these two package types, implement the flowchart appropriate for the product used. DIP product MFP product Program write and verify Program write and verify Screening Screening Mounting Mounting See the following item for details on the screening conditions. Notes on One-Time Programmable Microcontroller Screening Due to the structure of their circuits, it is not possible for Sanyo to fully test one-time programmable microcontroller products before the PROM has been written. To increase the reliability after the PROM has been written, we strongly recommend screening these products after writing according to the following flowchart. Recommended Screening Flowchart High-temperature bake with no power applied +1 150 ±5°C, 24 Hr –0 Program readout verification VDD = 5 V ±0.5 V Due to the structure of the one-time programmable microcontroller PROM circuit in the state before writing, it is not possible to write test all the bits in the device. This means that it is impossible to guarantee a yield of 100%. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1998. Specifications and information herein are subject to change without notice. PS No. 5894-14/14