LC66E516

CMOS LSI No. 5483 LC662304A, 662306A, 662308A, 662312A, 662316A Four-Bit Single-Chip Microcontrollers with 4, 6, 8, 12, and 16 KB of On-Chip ROM Preliminary Overview The LC662304A, LC662306A, LC662308A, LC662312A, and LC662316A are 4-bit CMOS microcontrollers that integrate on a single chip all the functions required in a special-purpose telephone controller, including ROM, RAM, I/O ports, a serial interface, a DTMF generator, timers, and interrupt functions. These microcontrollers are available in a 42-pin package. Package Dimensions unit: mm 3025B-DIP42S [LC662304A/662306A/662308A/662312A/662316A] 42 22 15.24 Features and Functions • On-chip ROM capacities of 4, 6, 8, 12, and 16 kilobytes, and an on-chip RAM capacity of 512 × 4 bits. • Fully supports the LC66000 Series common instruction set (128 instructions). • I/O ports: 36 pins • DTMF generator This microcontroller incorporates a circuit that can generate two sine wave outputs, DTMF output, or a melody output for software applications. • 8-bit serial interface: one circuit • Instruction cycle time: 0.95 to 10 µs (at 3.0 to 5.5 V) • Powerful timer functions and prescalers — Time limit timer, event counter, pulse width measurement, and square wave output using a 12-bit timer. — Time limit timer, event counter, PWM output, and square wave output using an 8-bit timer. — Time base function using a 12-bit prescaler. • Powerful interrupt system with 10 interrupt factors and 7 interrupt vector locations. — External interrupts: 3 factors/3 vector locations — Internal interrupts: 4 factors/4 vector locations (Waveform output internal interrupts: 3 factors and 1 vector; shared with external expansion interrupts) • Flexible I/O functions Selectable options include 20-mA drive outputs, inverter circuits, pull-up and open drain circuits. • Optional runaway detection function (watchdog timer) • 8-bit I/O functions • Power saving functions using halt and hold modes. • Packages: DIP42S, QIP48E (QFP48E) • Evaluation LSIs: LC66599 (evaluation chip) + EVA800/850-TB662YXX2 LC66E2316(on-chip EPROM microcontroller) 1 37.9 4.25 13.8 21 0.95 0.48 1.78 0.51 min 1.15 SANYO: DIP42S unit: mm 3156-QFP48E [LC662304A/662306A/662308A/662312A/662316A] 17.2 1.5 36 1.5 37 1.0 14.0 1.6 1.5 25 24 0.15 17.2 14.0 1.6 1.5 1.0 48 1 0.35 13 12 0.1 2.70 (STAND OFF) 3.0max 0.8 15.6 SANYO: QFP48E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 22897HA (OT) No. 5483-1/25 3.8 5.1 max 0.25 LC662304A, 662306A, 662308A, 662312A, 662316A Series Organization Type No. LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B/562B/566B LC66354C/356C/358C LC662104A/06A/08A LC662304A/06A/08A/12A/16A LC662508A/12A/16A LC665304A/06A/08A/12A/16A LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 LC66E2108* LC66E2316 LC66E2516 LC66E5316 LC66P2108* LC66P2316* LC66P2516 LC66P5316 Note: * Under development No. of pins 42 42 64 42 42 64 42 64 42 30 42 64 48 42 42 42 42 64 64 30 42 64 52/48 30 42 64 48 ROM capacity 4 K/6 K/8 KB 4 K/6 K/8 KB 6 K/8 K/12 K/16 KB 4 K/6 K/8 KB 4 K/6 K/8 KB 6 K/8 K/12 K/16 KB 4 K/6 K/8 KB 6 K/8 K/12 K/16 KB 4 K/6 K/8 KB 4 K/6 K/8 KB RAM capacity 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 384 W DIP64S DIP42S DIP64S DIP42S DIP30SD DIP42S DIP64S DIP48S DIC42S with window DIP42S DIC42S with window DIP42S DIC64S with window DIP64S DIP42S DIP42S DIP64S DIP42S Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP48E MFP30S QFP48E QFP64E QFP48E QFC48 with window QFP48E QFC48 with window QFP48E QFC64 with window QFP64E Window and OTP evaluation versions 4.5 to 5.5 V/0.92 µs Dual oscillator support 3.0 to 5.5 V/0.95 µs On-chip DTMF generator versions 3.0 to 5.5 V/0.95 µs Low-voltage versions 2.2 to 5.5 V/3.92 µs Low-voltage high-speed versions 3.0 to 5.5 V/0.92 µs 2.5 to 5.5 V/0.92 µs Normal versions 4.0 to 6.0 V/0.92 µs Features 4 K/6 K/8 K/12 K/16 KB 512 W 8 K/12 K/16 KB 512 W 4 K/6 K/8 K/12 K/16 KB 512 W EPROM 8 KB OTPROM 8 KB EPROM 8 KB OTPROM 8 KB EPROM 16 KB OTPROM 16 KB EPROM 8 KB EPROM 16 KB EPROM 16 KB EPROM 16 KB OTPROM 8 KB OTPROM 16 KB OTPROM 16 KB OTPROM 16 KB 512 W 512 W 512 W 512 W 512 W 512 W 384 W 512 W 512 W 512 W 384 W 512 W 512 W 512 W DIC42S with window DIC64S with window DIC52S with window DIP30SD DIP42S DIP64S DIP48S QFC48 with window QFC64 with window QFC48 with window MFP30S QFP48E QFP64E QFP48E Window evaluation versions 4.5 to 5.5 V/0.92 µs OTP 4.0 to 5.5 V/0.95 µs No. 5483-2/25 LC662304A, 662306A, 662308A, 662312A, 662316A Pin Assignments DIP42S P20/SI0 P21/SO0 P22/SCK0 P23/INT0 P30/INT1 P31/POUT0 P32/POUT1 VSS OSC1 OSC2 VDD RES PE0 PE1 TEST P33/HOLD P40/INV01 P41/INV00 P42/INV11 P43/INV10 P50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P13 P12 P11 P10 P03 P02 P01 P00 PD3/INV30 PD2/INV31 PD1/INV20 PD0/INV21 PC3 PC2 P63/PIN1 P62/DT P61 P60/ML P53/INT2 P52 P51 LC662304A 2306A 2308A 2312A 2316A QFP48E P03 P10 P11 P12 P13 NC NC P20/SI0 P21/SO0 P22/SCK0 P23/INT0 P30/INT1 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 LC662304A 41 20 2306A 42 19 2308A 43 18 2312A 44 17 2316A 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 P31/POUT0 P32/POUT1 VSS OSC1 OSC2 NC VDD RES PE0 PE1 TEST P33/HOLD P02 P01 P00 PD3/INV3O PD2/INV3I PD1/INV2O NC PD0/INV2I PC3 PC2 P63/PIN P62/DT P61 P60/ML P53/INT2 P52 P51 NC NC P50 P43/INV1O P42/INV1I P41/INV0O P40/INV0I Top view We recommend the use of reflow-soldering techniques to solder-mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques). No. 5483-3/25 LC662304A, 662306A, 662308A, 662312A, 662316A System Block Diagram RAM STACK (512W) SYSTEM CONTROL FLAG E DD DD SP M P P P P R HL XY C Z ROM 4K/6K/8K/12K/16KB RES TEST OSC1 OSC2 HOLD E A ALU PC ML DT DTMF GEN. PRESCALER MPX TIMER0 SERIAL I/O 0 POUT0 SI0 SO0 SCK0 INT0 INT1, INT2 PE PD PC MPX INTERRUPT CONTROL MPX TIMER1 PIN1, POUT1 INVxO INVxI (x=0 to 3) P0 P1 P2 P3 P4 P5 P6 Differences between the LC663XX Series and the LC6623XX Series Item System differences • Hardware wait time (number of cycles) when hold mode is cleared LC6630X Series (Including the LC66599 evaluation chip) 65536 cycles About 64 ms at 4 MHz (Tcyc = 1 µs) LC6635XB Series 16384 cycles About 16 ms at 4 MHz (Tcyc = 1 µs) LC6623XX Series 16384 cycles About 16 ms at 4 MHz (Tcyc = 1 µs) • Value of timer 0 after a reset (Including the value after hold mode Set to FF0. is cleared) • DTMF generator • Inverter array • SIO1 • Three-value inputs/comparator inputs • Three-state output from P31 and P32 • Using P0 to clear halt mode • External extended interrupts None (Tools are handled with external devices.) None (Tools are handled with external devices.) Yes Yes None In 4-bit groups None for INT3, INT4, and INT5. (Tools are handled with external devices.) Shared with INT2 (Tools are handled with external devices.) • LC66304A/306A/308A 4.0 to 6.0 V/0.92 t 10 µs • LC66E308/P308 4.5 to 5.5 V/0.92 to 10 µs P0, P1, P4, and P5: about 3 to 10 kΩ • P2 to P6 and PC: 15-V handling • P0, P1, PD, PE: Normal voltage handling Set to FFC. Set to FFC. None None Yes Yes None In 4-bit groups None for INT3, INT4, and INT5. Yes Yes None None Yes Can be specified for each bit. INT3, INT4, and INT5 can be used with the internal functions. • Other P53 functions Shared with INT2 • 3.0 to 5.5 V/0.92 to 10 µs • LC6635XA 2.2 to 5.5 V/3.92 to 10 µs 3.0 to 5.5 V/1.96 to 10 µs P0, P1, P4, and P5: about 3 to 10 kΩ • P2 to P6 and PC: 15-V handling • P0, P1, PD, PE: Normal voltage handling Shared with INT2 Differences in main characteristics • Operating power-supply voltage and operating speed (cycle time) • Pull-up resistors • Port voltage handling 3.0 to 5.5 V/0.95 to 10 µs P0, P1, P4, and P5: about 100 kΩ P2, P3, P61, and P63: 12-V voltage handling Others: normal voltage handling No. 5483-4/25 LC662304A, 662306A, 662308A, 662312A, 662316A Pin Function Overview Pin I/O Overview Output driver type Options State after a Standby mode reset operation Hold mode: Output off High or low (option) Halt mode: Output retained Hold mode: Output off High or low (option) Halt mode: Output retained P00 P01 P02 P03 I/O I/O ports P00 to P03 • Input or output in 4-bit or 1-bit units • P00 to P03 support the halt mode control function (This function can be specified in bit units.) • Pch: Pull-up MOS type • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset P10 P11 P12 P13 I/O I/O ports P10 to P13 Input or output in 4-bit or 1-bit units • Pch: Pull-up MOS type • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset P20/SI0 P21/SO0 P22/SCK0 P23/INT0 I/O I/O ports P20 to P23 • Input or output in 4-bit or 1-bit units • P20 is also used as the serial input SI0 pin. • P21 is also used as the serial output SO0 pin. • P22 is also used as the serial clock SCK0 pin. • P23 is also used as the INT0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input. I/O ports P30 to P32 • Input or output in 3-bit or 1-bit units • P30 is also used as the INT1 interrupt request. • P31 is also used for the square wave output from timer 0. • P32 is also used for the square wave and PWM output from timer 1. • P31 and P32 also support 3-state outputs. • Pch: CMOS type • Nch: Intermediate sink current type • Nch: +12-V handling when OD option selected Hold mode: Output off CMOS or Nch OD output H Halt mode: Output retained P30/INT1 P31/POUT0 P32/POUT1 I/O • Pch: CMOS type • Nch: Intermediate sink current type • Nch: +12-V handling when OD option selected Hold mode: Output off CMOS or Nch OD output H Halt mode: Output retained P33/HOLD I Hold mode control input • Hold mode is set up by the HOLD instruction when HOLD is low. • In hold mode, the CPU is restarted by setting HOLD to the high level. • This pin can be used as input port P33 along with P30 to P32. • When the P33/HOLD pin is at the low level, the CPU will not be reset by a low level on the RES pin. Therefore, applications must not set P33/HOLD low when power is first applied. P40/INV0I P41/INV0O P42/INV1I P43/INV1O I/O I/O ports P40 to P43 • Input or output in 4-bit or 1-bit units • Input or output in 8-bit units when used in conjunction with P50 to P53. • Can be used for output of 8-bit ROM data when used in conjunction with P50 to P53. • Dedicated inverter circuit (option) • Pch: Pull-up MOS type • CMOS type when the inverter circuit option is selected • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset • Inverter circuit High or low or inverter I/O (option) Hold mode: Port output off, inverter output off Halt mode: Port output retained, inverter output continues Continued on next page. No. 5483-5/25 LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. Pin I/O Overview I/O ports P50 to P53 • Input or output in 4-bit or 1-bit units • Input or output in 8-bit units when used in conjunction with P40 to P43. • Can be used for output of 8-bit ROM data when used in conjunction with P40 to P43. • P53 is also used as the INT2 interrupt request. Output driver type Options State after a Standby mode reset operation P50 P51 P52 P53/INT2 I/O • Pch: Pull-up MOS type • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset Hold mode: Output off High or low (option) Halt mode: Output retained P60/ML P61 P62/DT P63/PIN1 I/O I/O ports P60 to P63 • Input or output in 4-bit or 1-bit units • P60 is also used as the melody output ML pin. • P62 is also used as the tone output DT pin. • P63 is also used for the event count input to timer 1. • Pch: CMOS type • Nch: Intermediate sink current type • Nch: +12-V handling when OD option selected (P61 and P63 only) Hold mode: Output off CMOS or Nch OD output H Halt mode: Output retained PC2 PC3 I/O I/O ports PC2 to PC3 Output in 2-bit or 1-bit units • Pch: CMOS type • Nch: Intermediate sink current type Hold mode: Port output off CMOS or Nch OD output H Halt mode: Port output retained Inverter • Hold mode: output off • Halt mode: output continues PD0/INV2I PD1/INV2O PD2/INV3I PD3/INV4O I Dedicated input ports PD0 to PD3 Dedicated inverter circuits (option) • When the inverter circuit option is selected. • Pch: CMOS type • Nch: Intermediate sink current type Inverter circuits Normal input or inverter I/O (option) PE0 PE1 I Dedicated input ports Normal input Hold mode: Oscillator stops Halt mode: Oscillator continues OSC1 OSC2 I O System clock oscillator connections When an external clock is used, leave OSC2 open and connect the clock signal to OSC1. System reset input When the P33/HOLD pin is at the high level, a low level input to the RES pin will initialize the CPU. CPU test pin This pin must be connected to VSS during normal operation. Power supply pins Ceramic oscillator or external clock selection Option selection RES I TEST I VDD VSS Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD. CMOS output: Complementary output. OD output: Open-drain output. No. 5483-6/25 LC662304A, 662306A, 662308A, 662312A, 662316A User Options 1. Port 0, 1, 4, and 5 output level at reset option The output levels at reset for I/O ports 0, 1, 4, and 5 in independent 4-bit groups, can be selected from the following two options. Option 1. Output high at reset 2. Output low at reset Conditions and notes The four bits of ports 0, 1, 4, or 5 are set in a group The four bits of ports 0, 1, 4, or 5 are set in a group 2. Oscillator circuit options • Main clock Option Circuit Conditions and notes 1. External clock OSC1 The input has Schmitt characteristics C1 2. Ceramic oscillator Ceramic oscillator OSC1 C2 OSC2 Note: There is no RC oscillator option. 3. Watchdog timer option A runaway detection function (watchdog timer) can be selected as an option. 4. Port output type options • The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be selected individually from the following two options. Option Circuit Conditions and notes Output data 1. Open-drain output Input data The port P2, P3, P5, and P6 inputs have Schmitt characteristics. DSB Output data 2. Output with built-in pull-up resistor The port P2, P3, P5, and P6 inputs have Schmitt characteristics. The CMOS outputs (ports P2, P3, P6, and PC) and the pull-up MOS outputs (P0, P1, P4, and P5) are distinguished by the drive capacity of the p-channel transistor. Input data DSB No. 5483-7/25 LC662304A, 662306A, 662308A, 662312A, 662316A 5. Inverter array circuit option One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PD0/PD1, and PD2/PD3. (PDs do not use option 1 because they are dedicated to input.) Option Circuit Output data Input data When the open-drain output type is selected Conditions and notes DSB 1. Normal port I/O circuit Output data When the built-in pull-up resistor output type is selected Input data DSB Input Output data high Input data DSB 2. Inverter I/O circuit Output Output data high Input data If this option is selected, The I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected. DSB No. 5483-8/25 LC662304A, 662306A, 662308A, 662312A, 662316A LC662316 Series Option Data Area and Definitions ROM area Bit 7 6 5 3FF0H 4 3 2 1 0 7 6 5 3FF1H 4 3 2 1 0 7 6 5 3FF2H 4 3 2 1 0 7 6 5 3FF3H 4 3 2 1 0 7 6 5 3FF4H 4 3 2 1 0 7 6 5 3FF5H 4 3 2 1 0 7 6 5 3FF6H 4 3 2 1 0 Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. P63 P62 P61 P60 Output type 0 = OD, 1 = PU Unused This bit must be set to 0. P5 P4 Unused Oscillator option Unused P1 P0 Output level at reset Option specified Output level at reset Option/data relationship 0 = high level, 1 = low level This bit must be set to 0. 0 = external clock, 1 = ceramic oscillator This bit must be set to 0. 0 = low level, 1 = high level 0 = none, 1 = yes Watchdog timer option P13 P12 P11 P10 P03 P02 P01 P00 Unused P32 P31 P30 P23 P22 P21 P20 P53 P52 P51 P50 P43 P42 P41 P40 Output type Output type Output type Output type Output type Output type 0 = OD, 1 = PU 0 = OD, 1 = PU This bit must be set to 0. 0 = OD, 1 = PU 0 = OD, 1 = PU 0 = OD, 1 = PU 0 = OD, 1 = PU Continued on next page. LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. ROM area Bit 7 6 5 3FF7H 4 3 2 1 0 7 6 5 3FF8H 4 3 2 1 0 7 6 5 3FF9H 4 3 2 1 0 7 6 5 3FFAH 4 3 2 1 0 7 6 5 3FFBH 4 3 2 1 0 7 6 5 3FFCH 4 3 2 1 0 7 6 5 3FFDH 4 3 2 1 0 Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to ‘00’. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. PC3 PC2 Unused ML disabled option Unused Unused PD3 PD1 Unused P43 P41 Inverter output This bit must be set to 1. 0 = inverter output, 1 = none Inverter output Output type 0 = OD, 1 = PU Unused This bit must be set to 0. Option specified Option/data relationship This bit must be set to 0. 0 = disabled, 1 = enabled This bit must be set to 1. This bit must be set to 1. 0 = inverter output, 1 = none Continued on next page. No. 5483-10/25 LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. ROM area Bit 7 6 5 3FFEH 4 3 2 1 0 7 6 5 3FFFH 4 3 2 1 0 Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to ‘00’. Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to ‘00’. Option specified Option/data relationship Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 Output voltage VOUT1 VOUT2 ION1 Output current per pin ION2 –IOP1 –IOP2 –IOP3 Σ ION1 Total pin current Σ ION2 Σ IOP1 Σ IOP2 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD P2, P3 (except for the P33/HOLD pin), P61, and P63 All other inputs P2, P3 (except for the P33/HOLD pin), P61, and P63 All other inputs P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, PC P41, P43, PC3, PD1, PD3 P0, P1, P4, P5 P2, P3 (except for the P33/HOLD pin), P6, and PC P41, P43, PC3, PD1, PD3 P0, P1, P2, P3 (except for the P33/HOLD pin), PD P4, P5, P6, PC P0, P1, P2, P3 (except for the P33/HOLD pin), PD P4, P5, P6, PC Ta = –30 to +70°C: DIP42S (QFP48E) Conditions Ratings –0.3 to +7.0 –0.3 to +12.0 –0.3 to VDD + 0.3 –0.3 to +12.0 –0.3 to VDD + 0.3 20 20 2 4 10 75 75 25 25 600 (430) –30 to +70 –55 to +125 Unit V V V V V mA mA mA mA mA mA mA mA mA mW °C °C 1 2 1 2 3 3 4 4 4 3 3 4 4 5 Note Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that pin apply. 2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed. 3. Sink current (Applies to PD when the inverter array specifications are selected.) 4. Source current (Applies to all pins except PD for which the pull-up output specifications, the CMOS output specifications, or the inverter array specifications have been selected. Applies to PD pins for which the inverter array specifications have been selected.) 5. We recommend the use of reflow soldering techniques to solder mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques). No. 5483-11/25 LC662304A, 662306A, 662308A, 662312A, 662316A Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified. Parameter Operating supply voltage Memory retention supply voltage Symbol VDD VDDH VIH1 Input high-level voltage VIH2 VIH3 VIL1 Input low-level voltage VIL2 VIL3 Operating frequency (instruction cycle time) [External clock input conditions] OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) fop (Tcyc) VDD VDD: During hold mode P2, P3 (except for the P33/HOLD pin), P61, and P63: N-channel output transistor off P33/HOLD, RES, OSC1: N-channel output transistor off P0, P1, P4, P5, PC, PD, PE: N-channel output transistor off P2, P3 (except for the P33/HOLD pin), P6, RES, and OSC1: N-channel output transistor off P33/HOLD: VDD = 1.8 to 5.5 V P0, P1, P4, P5, PC, PD, PE, TEST: N-channel output transistor off Conditions min 3.0 1.8 0.8 VDD 0.8 VDD 0.8 VDD VSS VSS VSS 0.4 (10) typ max 5.5 5.5 10.0 VDD VDD 0.2 VDD 0.2 VDD 0.2 VDD 4.20 (0.95) Unit V V V V V V V V MHz (µs) 2 2 2 1 Note Frequency fext 0.4 4.20 MHz Pulse width textH, textL 100 ns Rise and fall times textR, textF 30 ns Note: 1. Applies to pins with open-drain specifications. However, VIH2 applies to the P33/HOLD pin. When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins. 2. PC port pins with CMOS output specifications cannot be used as input pins. Contact Sanyo for details on the allowable operating ranges for P4 and PD pins with inverter array specifications. No. 5483-12/25 LC662304A, 662306A, 662308A, 662312A, 662316A Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified. Parameter Symbol IIH1 Conditions P2, P3 (except for the P33/HOLD pin), P61, and P63: VIN = 10.0 V, with the output Nch transistor off P0, P1, P4, P5, P6, PC, OSC1, RES, and P33/HOLD (Does not apply to PD, PE, PC2, PC3, P61, and P63.): VIN = VDD, with the output Nch transistor off PD, PE, PC2, PC3: VIN = VDD, with the output Nch transistor off Input ports other than PD, PE, PC2, and PC3: VIN = VSS, with the output Nch transistor off PC2, PC3, PD, PE: VIN = VSS, with the output Nch transistor off P2, P3 (except for the P33/HOLD pin), P6, and PC: IOH = –1 mA P2, P3 (except for the P33/HOLD pin), P6, and PC: IOH = –0.1 mA P0, P1, P4, P5 P0, P1, P2, P3, P4, P5, P6, and PC (except for the P33/HOLD pin): IOL = 1.6 mA P0, P1, P2, P3, P4, P5, P6, and PC (except for the P33/HOLD pin): IOL = 8 mA P2, P3, P61, P63: VIN = VDD Does not apply to P2, P3, P61, and P63: VIN = VDD 0.1 VDD P2, P3, P5, P6, OSC1 (EXT), RES 0.5 VDD 0.2 VDD OSC1, OSC2: Figure 2, 4 MHz Figure 3, 4 MHz 4.0 10.0 0.8 VDD 0.5 VDD –1.0 –1.0 VDD – 1.0 V VDD – 0.5 30 100 150 0.4 1.5 5.0 1.0 kΩ V V µA µA 5 5 4 3 min typ max 5.0 Unit µA Note 1 Input high-level current IIH2 1.0 µA 1 IIH3 IIL1 Input low-level current IIL2 1.0 µA µA µA 1 2 2 Output high-level voltage VOH1 Value of the output pull-up resistor RPO VOL1 Output low-level voltage VOL2 IOFF1 Output off leakage current [Schmitt characteristics] Hysteresis voltage High-level threshold voltage Low-level threshold voltage [Ceramic oscillator] Oscillator frequency Oscillator stabilization time [Serial clock] Cycle time Input Output tCKCY tCKL tCKH tCKR, tCKF fCF fCFS VHYS Vt H Vt L IOFF2 V V V MHz ms 0.9 2.0 SCK0: With the timing of Figure 4 and the test load of Figure 5. 0.4 1.0 0.1 µs Tcyc µs Tcyc µs Low-level and high-level Input pulse widths Output Rise an fall times [Serial input] Data setup time Data hold time [Serial output] Output delay time Output tICK tCKI SI0: With the timing of Figure 4. Stipulated with respect to the rising edge (↑) of SCK0. 0.3 0.3 µs µs tCKO SO0: With the timing of Figure 4 and the test load of Figure 5. Stipulated with respect to the falling edge (↓) of SCK0. 0.3 µs Continued on next page. No. 5483-13/25 LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. Parameter [Pulse conditions] INT0: Figure 6, conditions under which the INT0 interrupt can be accepted, conditions under which the timer 0 event counter or pulse width measurement input can be accepted INT1, INT2: Figure 6, conditions under which the corresponding interrupt can be accepted PIN1: Figure 6, conditions under which the timer 1 event counter input can be accepted RES: Figure 6, conditions under which reset can be applied. Symbol Conditions min typ max Unit Note INT0 high and low-level tIOH, tIOL 2 Tcyc High and low-level pulse widths for interrupt inputs other than INT0 PIN1 high and low-level pulse widths RES high and low-level pulse widths tIIH, tIIL tPINH, tPINL tRSH, tRSL 2 2 3 Tcyc Tcyc Tcyc Operating current drain IDD OP IDDHALT IDDHOLD VDD: 4-MHz ceramic oscillator VDD: 4-MHz external clock VDD: 4-MHz ceramic oscillator VDD: 4-MHz external clock VDD: VDD = 1.8 to 5.5 V 4.5 4.5 2.5 2.5 0.01 8.0 8.0 5.5 5.5 10 mA mA mA mA µA 6 Halt mode current drain Hold mode current drain Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the CMOS output specifications are selected. 2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected. 3. With the output Nch transistor off for CMOS output specification pins. 4. With the output Nch transistor off for pull-up output specification pins. 5. With the output Nch transistor off for open-drain output specification pins. 6. Reset state Tone (DTMF) Output Characteristics DC Characteristics at Ta = –30 to +70°C, VSS = 0 V 1. When the MLOUT enable option is selected (the ML output function can be used) Parameter Tone output voltage (p-p) Row/column tone output voltage ratio Tone distortion Symbol VT1 DBCR1 THD1 Conditions DT: Dual tones, VDD = 3.5 to 5.5 V* DT: Dual tones, VDD = 3.5 to 5.5 V* DT: Single tone, VDD = 3.5 to 5.5 V* min 0.9 1.0 typ 1.3 2.0 2 max 2.0 3.0 7 Unit V dB % Note * See item 2. below if the MLOUT disable mask option was selected. 2. When the MLOUT disable option is selected (the ML output function cannot be used) Parameter Tone output voltage (p-p) Row/column tone output voltage ratio Tone distortion Symbol VT1 DBCR1 THD1 Conditions DT: Dual tones, VDD = 3.0 to 5.5 V* DT: Dual tones, VDD = 3.0 to 5.5 V* DT: Single tone, VDD = 3.0 to 5.5 V* min 0.9 1.0 typ 1.3 2.0 2 max 2.0 3.0 7 Unit V dB % Note * See item 1. above if the MLOUT enable mask option was selected. No. 5483-14/25 LC662304A, 662306A, 662308A, 662312A, 662316A VDD 0.8VDD 0.2VDD VSS External clock OPEN OSC1 (OSC2) textL textF textR 1/fext textH Figure 1 External Clock Input Waveform VDD OSC1 OSC2 OSC C1 Ceramic oscillator OV C2 Oscillator unstable period tCFS 
Table 1 Guaranteed Ceramic Oscillator Constants External capacitor type External capacitor type Built-in capacitor type 4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG 4 MHz (Kyocera Corporation) KBR4.0MS C1 = 33 pF ± 10% C2 = 33 pF ± 10% C1 = 33 pF ± 10% C2 = 33 pF ± 10% 4 MHz (Murata Mfg. Co., Ltd.) CST4.00MG 4 MHz (Kyocera Corporation) KBR4.0MES Figure 2 Ceramic Oscillator Circuit Figure 3 Oscillator Stabilization Period tCKCY tCKL SCK0 SCK1 0.2VDD 0.4VDD tCKR tCKH tCKF 0.8VDD (input) VDD-1 (output) tICK tCKI 0.8VDD 0.2VDD tCK0 TEST point VDD-1 0.4VDD SI0 SI1 R=1kΩ C=50pF SO0 SO1 Figure 4 Serial I/O Timing Figure 5 Timing Load No. 5483-15/25 LC662304A, 662306A, 662308A, 662312A, 662316A tI0H tI1H tPINH tRSH 0.8VDD 0.2VDD tI0L tI1L tPINL tRSL Figure 6 Input Timing for the INT0, INT1, INT2, PIN1, and RES pins P60/ML P62/DT R=10kΩ Figure 7 Tone Output Pin Load No. 5483-16/25 LC662304A, 662306A, 662308A, 662312A, 662316A LC66XXXX Series Instruction Table (by function) Abbreviations: AC: Accumulator E: E register CF: Carry flag ZF: Zero flag HL: Data pointer DPH, DPL XY: Data pointer DPX, DPY M: Data memory M (HL): Data memory pointed to by the DPH, DPL data pointer M (XY): Data memory pointed to by the DPX, DPY auxiliary data pointer M2 (HL): Two words of data memory (starting on an even address) pointed to by the DPH, DPL data pointer SP: Stack pointer M2 (SP): Two words of data memory pointed to by the stack pointer M4 (SP): Four words of data memory pointed to by the stack pointer in: n bits of immediate data t2: Bit specification t2 Bit 11 23 10 22 01 21 00 20 PCh: PCm: PCl: Fn: TIMER0: TIMER1: SIO: P: P (i4): INT: ( ), [ ]: ←: : : : +: –: —: Bits 8 to 11 in the PC Bits 4 to 7 in the PC Bits 0 to 3 in the PC User flag, n = 0 to 15 Timer 0 Timer 1 Serial register Port Port indicated by 4 bits of immediate data Interrupt enable flag Indicates the contents of a location Transfer direction, result Exclusive or Logical and Logical or Addition Subtraction Taking the one's complement No. 5483-17/25 LC662304A, 662306A, 662308A, 662312A, 662316A Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Accumulator manipulation instructions] CLA DAA Clear AC Decimal adjust AC in addition Decimal adjust AC in subtraction Clear CF Set CF Complement AC Increment AC Decrement AC Rotate AC right through CF Rotate AC left through CF Transfer AC to E Transfer E to AC Exchange AC with E 1000 1100 0010 1100 0010 0001 0001 0001 0001 0010 0001 0000 1111 0110 1111 1010 1110 1111 1000 0100 0100 0000 1 2 1 2 AC ← 0 Clear AC. (Equivalent to LAI 0.) AC ← (AC) + 6 Add six to AC. (Equivalent to ADI 6.) AC ← (AC) + 10 (Equivalent to ADI 0AH.) CF ← 0 CF ← 1 AC ← (AC) AC ← (AC) + 1 AC ← (AC) – 1 AC3 ← (CF), ACn ← (ACn + 1), CF ← (AC0) AC0 ← (CF), ACn + 1 ← (ACn), CF ← (AC3) E ← (AC) AC ← (E) (AC) ↔ (E) Add 10 to AC. Clear CF to 0. Set CF to 1. Take the one’s complement of AC. Increment AC. Decrement AC. Shift AC (including CF) right. ZF ZF Has a vertical skip function. Number of bytes Number of cycles Affected status bits Operation Description Note DAS CLC STC CMA IA DA RAR 2 1 1 1 1 1 1 2 1 1 1 1 1 1 ZF CF CF ZF ZF, CF ZF, CF CF RAL TAE TEA XAE 0000 0100 0100 0100 0001 0101 0110 0100 1 1 1 1 1 1 1 1 Shift AC (including CF) left. Move the contents of AC to E. CF, ZF Move the contents of E to AC. ZF Exchange the contents of AC and E. [Memory manipulation instructions] IM DM IMDR i8 Increment M Decrement M Increment M direct 0001 0010 1100 I7 I6 I5 I4 1100 I7 I6 I5 I4 0000 0010 0010 0010 0111 I3 I2 I1 I0 0011 I3 I2 I1 I0 1 1 t1 t0 1 1 t1 t0 1 1 2 2 1 1 1 1 2 2 1 1 M (HL) ← [M (HL)] + 1 M (HL) ← [M (HL)] – 1 M (i8) ← [M (i8)] + 1 M (i8) ← [M (i8)] – 1 [M (HL), t2] ← 1 [M (HL), t2] ← 0 Increment M (HL). Decrement M (HL). Increment M (i8). Decrement M (i8). Set the bit in M (HL) specified by t0 and t1 to 1. Clear the bit in M (HL) specified by t0 and t1 to 0. ZF ZF, CF ZF, CF ZF, CF ZF, CF DMDR i8 Decrement M direct SMB t2 RMB t2 Set M data bit Reset M data bit [Arithmetic, logic and comparison instructions] AC ← (AC) + [M (HL)] Add the contents of AC and M (HL) as two’s complement values and store the result in AC. AD Add M to AC 0000 0110 1 1 ZF, CF ADDR i8 Add M direct to AC 1100 I7 I6 I5 I4 1001 I3 I2 I1 I0 2 2 Add the contents of AC and M (i8) as two’s complement AC ← (AC) + [M (i8)] values and store the result in AC. AC ← (AC) + [M (HL)] + (CF) Add the contents of AC, M (HL) and C as two’s complement values and store the result in AC. Add the contents of AC and the immediate data as two’s complement values and store the result in AC. Subtract the contents of AC and CF from M (HL) as two’s complement values and store the result in AC. Take the logical and of AC and M (HL) and store the result in AC. Take the logical or of AC and M (HL) and store the result in AC. ZF, CF ADC Add M to AC with CF 0 0 0 0 0010 1 1 ZF, CF ADI i4 Add immediate data to AC 1100 0010 1111 I3 I2 I1 I0 2 2 AC ← (AC) + I3, I2, I1, I0 ZF SUBC Subtract AC from M with CF 0001 0111 1 1 AC ← [M (HL)] – (AC) – (CF) AC ← (AC) [M (HL)] AC ← (AC) [M (HL)] ZF, CF CF will be zero if there was a borrow and one otherwise. ANDA And M with AC then store AC Or M with AC then store AC 0000 0111 1 1 ZF ORA 0000 0101 1 1 ZF Continued on next page. No. 5483-18/25 LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Arithmetic, logic and comparison instructions] EXL Exclusive or M with AC then store AC And M with AC then store M Or M with AC then store M 0001 0101 1 1 AC ← (AC) [M (HL)] M (HL) ← (AC) [M (HL)] M (HL) ← (AC) [M (HL)] Take the logical exclusive or of AC and M (HL) and store the result in AC. Take the logical and of AC and M (HL) and store the result in M (HL). Take the logical or of AC and M (HL) and store the result in M (HL). Compare the contents of AC and M (HL) and set or clear CF and ZF according to the result. CM Compare AC with M 0001 0110 1 1 [M (HL)] + (AC) + 1 Magnitude comparison [M (HL)] > (AC) [M (HL)] = (AC) [M (HL)] < (AC) CF ZF 0 1 1 0 1 0 ZF, CF ZF Number of bytes Number of cycles Affected status bits Operation Description Note ANDM 0000 0011 1 1 ZF ORM 0000 0100 1 1 ZF Compare the contents of AC and the immediate data I3 I2 I1 I0 and set or clear CF and ZF according to the result. CI i4 Compare AC with immediate data 1100 1010 1111 I3 I2 I1 I0 2 2 I3 I2 I1 I0 + (AC) + 1 Magnitude comparison I3 I2 I1 I0 > AC I3 I2 I1 I0 = AC I3 I2 I1 I0 < AC ZF ← 1 if (DPL) = I3 I2 I1 I0 ZF ← 0 if (DPL) ≠ I3 I2 I1 I0 ZF ← 1 if (AC, t2) = [M (HL), t2] ZF← 0 if (AC, t2) ≠ [M (HL), t2] AC ← M (HL), E ← M (HL + 1) AC ← I3 I2 I1 I0 AC ← [M (i8)] M (HL) ← (AC) M (HL) ← (AC) M (HL + 1) ← (E) CF ZF 0 1 1 0 1 0 ZF, CF CLI i4 Compare DPL with immediate data 1100 1011 1111 I3 I2 I1 I0 2 2 Compare the contents of DPL with the immediate data. Set ZF if identical and clear ZF if not. Compare the corresponding bits specified by t0 and t1 in AC and M (HL). Set ZF if identical and clear ZF if not. ZF CMB t2 Compare AC bit with M data bit 1100 1101 1111 0 0 t1 t0 2 2 ZF [Load and store instructions] LAE LAI i4 LADR i8 S SAE Load AC and E from M2 (HL) Load AC with immediate data Load AC from M direct Store AC to M Store AC and E to M2 (HL) 0101 1000 1100 I7 I6 I5 I4 0100 0101 1100 I3 I2 I1 I0 0001 I3 I2 I1 I0 0111 1110 1 1 2 1 1 1 1 2 1 1 Load the contents of M2 (HL) into AC, E. Load the immediate data into AC. Load the contents of M (i8) into AC. Store the contents of AC into M (HL). Store the contents of AC, E into M2 (HL). Load the contents of M (reg) into AC. The reg is either HL or XY depending on t0. ZF reg HL XY T0 0 1 ZF ZF Has a vertical skip function LA reg Load AC from M (reg) 0100 1 0 t0 0 1 1 AC ← [M (reg)] Continued on next page. No. 5483-19/25 LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Load and store instructions] Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. Exchange the contents of M (reg) and AC. The reg is either HL or XY depending on t0. reg HL XY T0 0 1 ZF is set according to the result of incrementing DPL or DPY. Number of bytes Number of cycles Affected status bits Operation Description Note LA reg, I Load AC from M (reg) 0100 then increment reg 1 0 t0 1 1 2 AC ← [M (reg)] DPL ← (DPL) + 1 or DPY ← (DPY) + 1 Load AC from M (reg) LA reg, D 0101 then decrement reg 1 0 t0 1 1 2 AC ← [M (reg)] DPL ← (DPL) – 1 or DPY ← (DPY) – 1 ZF is set according to the result of decrementing DPL or DPY. XA reg Exchange AC with M (reg) 0100 1 1 t0 0 1 1 (AC) ← [M (reg)] Exchange AC with XA reg, I M (reg) then increment reg 0100 1 1 t0 1 1 2 (AC) ← [M (reg)] DPL ← (DPL) + 1 or DPY ← (DPY) + 1 Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. The relationship between t0 and reg is the same as that for the XA reg instruction. Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. The relationship between t0 and reg is the same as that for the XA reg instruction. Exchange the contents of AC and M (i8). Load the immediate data i8 into E, AC. Load into E, AC the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC. Output from ports 4 and 5 the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC. ZF ZF is set according to the result of incrementing DPL or DPY. Exchange AC with XA reg, D M (reg) then decrement reg 0101 1 1 t0 1 1 2 (AC) ← [M (reg)] DPL ← (DPL) – 1 or DPY ← (DPY) – 1 ZF ZF is set according to the result of decrementing DPL or DPY. XADR i8 LEAI i8 Exchange AC with M direct Load E & AC with immediate data 1100 I7 I6 I5 I4 1100 I7 I6 I5 I4 1000 I3 I2 I1 I0 0110 I3 I2 I1 I0 2 2 2 2 (AC) ← [M (i8)] E ← I7 I6 I5 I4 AC ← I3 I2 I1 I0 E, AC ← [ROM (PCh, E, AC)] RTBL Read table data from 0101 program ROM 1010 1 2 RTBLP Read table data from program ROM then 0101 output to P4, 5 1000 1 2 Port 4, 5 ← [ROM (PCh, E, AC)] [Data pointer manipulation instructions] Load DPH with zero and DPL with immediate data respectively Load DPH with immediate data Load DPL with immediate data Load DPH, DPL with immediate data Load DPX, DPY with immediate data DPH ← 0 DPL ← I3 I2 I1 I0 DPH ← I3 I2 I1 I0 DPL ← I3 I2 I1 I0 DPH ← I7 I6 I5 I4 DPL ← I3 I2 I1 I0 DPX ← I7 I6 I5 I4 DPY ← I3 I2 I1 I0 Load zero into DPH and the immediate data i4 into DPL. Load the immediate data i4 into DPH. Load the immediate data i4 into DPL. Load the immediate data into DLH, DPL. Load the immediate data into DLX, DPY. LDZ i4 0110 I3 I2 I1 I0 1111 I3 I2 I1 I0 1111 I3 I2 I1 I0 0000 I3 I2 I1 I0 0000 I3 I2 I1 I0 1 1 LHI i4 LLI i4 LHLI i8 LXYI i8 1100 0000 1100 0001 1100 I7 I6 I5 I4 1100 I7 I6 I5 I4 2 2 2 2 2 2 2 2 Continued on next page. No. 5483-20/25 LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Data pointer manipulation instructions] IL DL IY DY TAH THA XAH TAL TLA XAL TAX TXA XAX TAY TYA XAY Increment DPL Decrement DPL Increment DPY Decrement DPY Transfer AC to DPH Transfer DPH to AC Exchange AC with DPH Transfer AC to DPL Transfer DPL to AC Exchange AC with DPL Transfer AC to DPX Transfer DPX to AC Exchange AC with DPX Transfer AC to DPY Transfer DPY to AC Exchange AC with DPY 0001 0010 0001 0010 1100 1111 1100 1110 0100 1100 1111 1100 1110 0100 1100 1111 1100 1110 0100 1100 1111 1100 1110 0100 0001 0001 0011 0011 1111 0000 1111 0000 0000 1111 0001 1111 0001 0001 1111 0010 1111 0010 0010 1111 0011 1111 0011 0011 1 1 1 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 1 2 2 1 2 2 1 2 2 1 2 2 1 DPL ← (DPL) + 1 DPL ← (DPL) – 1 DPY ← (DPY) + 1 DPY ← (DPY) – 1 DPH ← (AC) AC ← (DPH) (AC) ↔ (DPH) DPL ← (AC) AC ← (DPL) (AC) ↔ (DPL) DPX ← (AC) AC ← (DPX) (AC) ↔ (DPX) DPY ← (AC) AC ← (DPY) (AC) ↔ (DPY) Increment the contents of DPL. Decrement the contents of DPL. Increment the contents of DPY. Decrement the contents of DPY. Transfer the contents of AC to DPH. Transfer the contents of DPH to AC. Exchange the contents of AC and DPH. Transfer the contents of AC to DPL. Transfer the contents of DPL to AC. Exchange the contents of AC and DPL. Transfer the contents of AC to DPX. Transfer the contents of DPX to AC. Exchange the contents of AC and DPX. Transfer the contents of AC to DPY. Transfer the contents of DPY to AC. Exchange the contents of AC and DPY. Set the flag specified by n4 to 1. Reset the flag specified by n4 to 0. ZF ZF ZF ZF ZF ZF ZF ZF ZF Number of bytes Number of cycles Affected status bits Operation Description Note [Flag manipulation instructions] SFB n4 RFB n4 Set flag bit Reset flag bit 0111 0011 n 3 n2 n1 n0 n 3 n2 n1 n0 1 1 1 1 Fn ← 1 Fn ← 0 [Jump and subroutine instructions] PC13, 12 ← PC13, 12 PC11 to 0 ← P11 to P8 PC13 to 8 ← PC13 to 8, PC7 to 4 ← (E), PC3 to 0 ← (AC) PC13 to 11 ← 0, PC10 to 0 ← P10 to P0, M4 (SP) ← (CF, ZF, PC13 to 0), SP ← (SP)-4 Jump to the location in the same bank specified by the immediate data P12. Jump to the location determined by replacing the lower 8 bits of the PC by E, AC. This becomes PC12 + (PC12) immediately following a BANK instruction. JMP addr Jump in the current bank 1 1 1 0 P11P10P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2 2 JPEA Jump to the address stored at E and AC in the current page 0010 0111 1 1 CAL addr Call subroutine 0 1 0 1 0 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2 2 Call a subroutine. CZP addr Call subroutine in the 1010 zero page P3 P2 P1 P0 1 2 PC13 to 6, PC10 ← 0, PC5 to 2 ← P3 to P0, Call a subroutine on page 0 M4 (SP) ← in bank 0. (CF, ZF, PC12 to 0), SP ← SP-4 Change the memory bank and register bank. BANK Change bank 0001 1011 1 1 Continued on next page. No. 5483-21/25 LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Jump and subroutine instructions] Store the contents of reg in M2 (SP). Subtract 2 from SP after the store. PUSH reg Push reg on M2 (SP) 1100 1111 1111 1 i 1 i0 0 2 2 M2 (SP) ← (reg) SP ← (SP) – 2 reg HL XY AE Illegal value i1 0 0 1 1 i0 0 1 0 1 Number of bytes Number of cycles Affected status bits Operation Description Note POP reg Pop reg off M2 (SP) 1100 1110 1111 1 i 1 i0 0 2 2 SP ← (SP) + 2 reg ← [M2 (SP)] Add 2 to SP and then load the contents of M2(SP) into reg. The relation between i1i0 and reg is the same as that for the PUSH reg instruction. Return from a subroutine or interrupt handling routine. ZF and CF are not restored. Return from a subroutine or interrupt handling routine. ZF and CF are restored. ZF, CF RT Return from subroutine Return from interrupt routine 0001 1100 1 2 SP ← (SP) + 4 PC ← [M4 (SP)] SP ← (SP) + 4 PC ← [M4 (SP)] CF, ZF ← [M4 (SP)] PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (AC, t2) = 1 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (AC, t2) = 0 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [M (HL),t2] =1 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [M (HL),t2] =0 RTI 0001 1101 1 2 [Branch instructions] BAt2 addr 1 1 0 1 0 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch to the location in the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1 t0 is one. Branch to the location in the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1 t0 is zero. Branch to the location in the same page specified by P7 to P0 if the bit in M (HL) specified by the immediate data t1 t0 is one. Branch to the location in the same page specified by P7 to P0 if the bit in M (HL) specified by the immediate data t1 t0 is zero. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers that can be read out. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers that can be read out. Branch on AC bit 2 2 BNAt2 addr Branch on no AC bit 1 0 0 1 0 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 BMt2 addr Branch on M bit 1 1 0 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 BNMt2 addr Branch on no M bit 1 0 0 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 BPt2 addr Branch on Port bit 1 1 0 1 1 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] =1 Branch to the location in the same page specified by P7 to P0 if the bit in port (DPL) specified by the immediate data t1 t0 is one. BNPt2 addr 1 0 0 1 1 0 t1 t0 Branch on no Port bit P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] =0 Branch to the location in the same page specified by P7 to P0 if the bit in port (DPL) specified by the immediate data t1 t0 is zero. Continued on next page. No. 5483-22/25 LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Branch instructions] 1101 1100 P7 P6 P5 P4 P3 P2 P1 P0 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (CF) = 1 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (CF) = 0 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (ZF) = 1 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (ZF) = 0 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (Fn) = 1 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (Fn) = 0 Branch to the location in the same page specified by P7 to P0 if CF is one. Branch to the location in the same page specified by P7 to P0 if CF is zero. Branch to the location in the same page specified by P7 to P0 if ZF is one. Branch to the location in the same page specified by P7 to P0 if ZF is zero. Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is one. Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is zero. Number of bytes Number of cycles Affected status bits Operation Description Note BC addr Branch on CF 2 2 BNC addr Branch on no CF 1001 1100 P7 P6 P5 P4 P3 P2 P1 P0 2 2 BZ addr Branch on ZF 1101 1101 P7 P6 P5 P4 P3 P2 P1 P0 2 2 BNZ addr Branch on no ZF 1001 1100 P7 P6 P5 P4 P3 P2 P1 P0 2 2 BFn4 addr Branch on flag bit 1 1 1 1 n 3 n2 n1 n0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 BNFn4 addr Branch on no flag bit 1 0 1 1 n 3 n2 n1 n0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 [I/O instructions] IP0 IP IPM IPDR i4 Input port 0 to AC Input port to AC Input port to M Input port to AC direct Input port 4, 5 to E, AC respectively Output AC to port Output M to port Output AC to port direct Output E, AC to port 4, 5 respectively 0010 0010 0001 1100 0110 1100 1101 0010 0001 1100 0111 1100 1101 0000 0110 1001 1111 I3 I2 I1 I0 1111 0100 0101 1010 1111 I3 I2 I1 I0 1111 0101 1 1 1 2 1 1 1 2 AC ← (P0) AC ← [P (DPL)] M (HL) ← [P (DPL)] AC ← [P (i4)] E ← [P (4)] AC ← [P (5)] P (DPL) ← (AC) P (DPL) ← [M (HL)] P (i4) ← (AC) P (4) ← (E) P (5) ← (AC) [P (DPL), t2] ← 1 Input the contents of port 0 to AC. Input the contents of port P (DPL) to AC. Input the contents of port P (DPL) to M (HL). Input the contents of P (i4) to AC. Input the contents of ports P (4) and P (5) to E and AC respectively. Output the contents of AC to port P (DPL). Output the contents of M (HL) to port P (DPL). Output the contents of AC to P (i4). Output the contents of E and AC to ports P (4) and P (5) respectively. Set to one the bit in port P (DPL) specified by the immediate data t1 t0. Clear to zero the bit in port P (DPL) specified by the immediate data t1 t0. ZF ZF ZF ZF IP45 2 2 OP OPM OPDR i4 1 1 2 1 1 2 OP45 2 2 SPB t2 Set port bit 0000 1 0 t1 t0 1 1 RPB t2 Reset port bit 0010 1 0 t1 t0 1 1 [P (DPL), t2] ← 0 P (P3 to P0) ← [P (P3 to P0)] I3 to I0 P (P3 to P0) ← [P (P3 to P0)] I3 to I0 And port with ANDPDR immediate data then i4, p4 output Or port with immediate data then output 1100 0101 I3 I2 I1 I0 P3 P2 P1 P0 2 2 Take the logical and of P (P3 to P0) and the immediate data ZF I3 I2 I1 I0 and output the result to P (P3 to P0). Take the logical or of P (P3 to P0) and the immediate data ZF I3 I2 I1 I0 and output the result to P (P3 to P0). ORPDR i4, p4 1100 0100 I3 I2 I1 I0 P3 P2 P1 P0 2 2 Continued on next page. No. 5483-23/25 LC662304A, 662306A, 662308A, 662312A, 662316A Continued from preceding page. Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Timer control instructions] WTTM0 Write timer 0 1100 1010 1 2 Write the contents of M2 (HL), TIMER0 ← [M2 (HL)], AC into the timer 0 reload (AC) register. Write the contents of E, AC TIMER1 ← (E), (AC) into the timer 1 reload register A. M2 (HL), AC ← (TIMER0) E, AC ← (TIMER1) Start timer 0 counter Start timer 1 counter Stop timer 0 counter Stop timer 1 counter Read out the contents of the timer 0 counter into M2 (HL), AC. Read out the contents of the timer 1 counter into E, AC. Start the timer 0 counter. Start the timer 1 counter. Stop the timer 0 counter. Stop the timer 1 counter. Number of bytes Number of cycles Affected status bits Operation Description Note WTTM1 Write timer 1 1100 1111 1111 0100 2 2 RTIM0 Read timer 0 1100 1100 1111 1100 1110 1100 1110 1100 1111 1100 1111 1011 1111 0101 1111 0110 1111 0111 1111 0110 1111 0111 1 2 RTIM1 Read timer 1 2 2 2 2 2 2 2 2 2 2 START0 Start timer 0 START1 Start timer 1 STOP0 STOP1 Stop timer 0 Stop timer 1 [Interrupt control instructions] MSET MRESET EIH i4 EIL i4 DIH i4 DIL i4 WTSP RSP Set interrupt master enable flag Reset interrupt master enable flag Enable interrupt high Enable interrupt low Disable interrupt high Disable interrupt low Write SP Read SP 1100 0101 1100 1001 1100 0101 1100 0100 1100 1001 1100 1000 1100 1101 1100 1101 1101 0000 1101 0000 1101 I3 I2 I1 I0 1101 I3 I2 I1 I0 1101 I3 I2 I1 I0 1101 I3 I2 I1 I0 1111 1010 1111 1011 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MSE ← 1 MSE ← 0 EDIH ← (EDIH) EDIL ← (EDIL) EDIH ← (EDIH) EDIL ← (EDIL) SP ← (E), (AC) E, AC ← (SP) i4 i4 i4 i4 Set the interrupt master enable flag to one. Clear the interrupt master enable flag to zero. Set the interrupt enable flag to one. Set the interrupt enable flag to one. Clear the interrupt enable flag to zero. Clear the interrupt enable flag to zero. Transfer the contents of E, AC to SP. Transfer the contents of SP to E, AC. ZF ZF [Standby control instructions] HALT HOLD HALT HOLD 1100 1101 1100 1101 1111 1110 1111 1111 2 2 2 2 HALT HOLD Enter halt mode. Enter hold mode. [Serial I/O control instructions] STARTS Start serial I O WTSIO RSIO Write serial I O Read serial I O 1100 1110 1100 1110 1100 1111 1111 1110 1111 1111 1111 1111 2 2 2 2 2 2 START SI O SIO ← (E), (AC) E, AC ← (SIO) Start SIO operation. Write the contents of E, AC to SIO. Read the contents of SIO into E, AC. [Other instructions] NOP No operation 0000 1100 1100 0000 1111 0 0 I1 I0 1 1 No operation PC13, PC12 ← I1 I0 Consume one machine cycle without performing any operation. Specify the memory bank. SB i2 Select bank 2 2 No. 5483-24/25 LC662304A, 662306A, 662308A, 662312A, 662316A s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5483-25/25