LC72131KM

Ordering number : ENA0788 LC72131K LC72131KM Overview CMOS IC PLL Frequency Synthesizer The LC72131K and LC72131KM are PLL frequency synthesizers for use in tuners in radio/cassette players. They allow high-performance AM/FM tuners to be implemented easily. Features • High speed programmable dividers • FMIN: 10 to 160MHz …………………….. pulse swallower (built-in divide-by-two prescaler) • AMIN: 2 to 40MHz ………………………. pulse swallower 0.5 to 10MHz …………………….. direct division • IF counter • IFIN: 0.4 to 12MHz ………………………. AM/FM IF counter • Reference frequencies • Twelve selectable frequencies (4.5 or 7.2MHz crystal) • 100, 50, 25, 15, 12.5, 6.25, 3.125, 10, 9, 5, 3, 1kHz • Phase comparator • Dead zone control • Unlock detection circuit • Deadlock clear circuit • Built-in MOS transistor for forming an active low-pass filter • I/O ports • Dedicated output ports: 4 • Input or output ports: 2 • Support clock time base output Continued on next page. • • CCB is a registered trademark of SANYO Semiconductor Co., Ltd. CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO Semiconductor for this format. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 51309HKIM 20070328-S00008,S00009 No.A0788-1/22 LC72131K, 72131KM Continued from preceding page. • Serial data I/O • Support CCB format communication with the system controller. • Operating ranges • Supply voltage ........................4.5 to 5.5V • Operating temperature ............ -40 to +85°C • Packages • DIP22S/MFP20 Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Supply voltage Maximum input voltage Symbol VDD max VIN1 max VIN2 max VIN3 max Maximum output voltage VO1 max VO2 max VO3 max Maximum output current IO1 max IO2 max IO3 max Allowable power dissipation Pd max VDD CE, CL, DI, AIN XIN, FMIN, AMIN, IFIN IO1, IO2 DO XOUT, PD BO1 to BO4, IO1, IO2, AOUT BO1 DO, AOUT BO2 to BO4, IO1, IO2 Ta≤85°C [LC72131K] Ta≤85°C [LC72131KM] Operating temperature Storage temperature Topr Tstg Pins Conditions Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to +15 -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to +15 0 to 3.0 0 to 6.0 0 to 10 350 180 -40 to +85 -55 to +125 Unit V V V V V V V mA mA mA mW mW °C °C Note 1: Power pins VDD and VSS: Insert a capacitor with a capacitance of 2,000pF or higher between these pins when using the IC. No.A0788-2/22 LC72131K, 72131KM Allowable Operating Ranges at Ta = -40°C to +85°C, VSS = 0V Parameter Supply voltage Input high-level voltage Symbol VDD VIH1 VIH2 Input low-level voltage Output voltage VIL VO1 VO2 Input frequency fIN1 fIN2 fIN3 fIN4 fIN5 Supported crystals Input amplitude High-level clock pulse width tφH CL [Figure 1][Figure 2] 160 ns Low-level clock pulse width X'tal VIN1 VIN2-1 VIN2-2 VIN3 VIN4 VIN5 VIN6 Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time Data latch change time Data output time tSU tHD tCL tCH tEL tES tEH tLC tDC tDH DO, CL DO, CE VDD CE, CL, DI IO1, IO2 CE, CL, DI, IO1, IO2 DO BO1 to BO4, IO1, IO2, AOUT XIN FMIN AMIN AMIN IFIN XIN, XOUT XIN FMIN FMIN AMIN AMIN IFIN IFIN DI, CL DI, CL CL CL CE, CL CE, CL CE, CL VIN1 VIN2 VIN3 VIN4 VIN5 Note 1 fIN1 f=10 to 130MHz f=130 to 160MHz fIN3 fIN4 fIN5 (IFS=1) fIN5 (IFS=0) Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Differs depending on the value of the pull-up resistor. Note 2 0.35 μs Pins Conditions Ratings min 4.5 0.7VDD 0.7VDD 0 0 0 1.0 10 2.0 0.5 0.4 4.0 400 40 70 40 40 40 70 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 typ max 5.5 6.5 13 0.3VDD 6.5 13 8.0 160 40 10 12 8.0 1500 1500 1500 1500 1500 1500 1500 unit V V V V V V MHz MHz MHz MHz MHz MHz mVrms mVrms mVrms mVrms mVrms mVrms mVrms μs μs μs μs μs μs μs μs Note 1: Recommended crystal oscillator CI values: CI≤120Ω (For a 4.5MHz crystal) CI≤70Ω (For a 7.2MHz crystal) The characteristics of the oscillation circuit depends on the printed circuit board, circuit constants, and other factors. Therefore we recommend consulting with the anufacturer of the crystal for evaluation and reliability. Note 2: Refer to "Serial Data Timing". No.A0788-3/22 LC72131K, 72131KM Electrical Characteristics in the Allowable Operating Ranges Parameter Built-in feedback resistance Symbol Rf1 Rf2 Rf3 Rf4 Built-in pull-down resistor Rpd1 Rpd2 Hysteresis Output high-level voltage Output low-level voltage VHYS VOH VOL1 VOL2 VOL3 VOL4 XIN FMIN AMIN IFIN FMIN AMIN CE, CL, DI, IO1, IO2 PD PD BO1 IO=1mA IO=1mA IO=0.5mA IO=1mA DO IO=1mA IO=5mA BO2 to BO4, IO1, IO2 IO=1mA IO=5mA IO=8mA VOL5 Input high-level current IIH1 IIH2 IIH3 IIH4 IIH5 IIH6 Input low-level current IIL1 IIL2 IIL3 IIL4 IIL5 IIL6 Output off leakage current IOFF1 IOFF2 High-level three-state off leakage current Low-level three-state off leakage current Input capacitance Current drain CIN IDD1 FMIN VDD X'tal=7.2MHz fIN2=130MHz IDD2 VDD VIN2=40mVrms PLL block stopped (PLL INHIBIT) X'tal oscillator operating (X'tal=7.2MHz) IDD3 VDD PLL block stopped X'tal oscillator operating 10 μA 0.5 mA 5 10 mA IOFFL PD VO=0V IOFFH AOUT CE, CL, DI IO1, IO2 XIN FMIN, AMIN IFIN AIN CE, CL, DI IO1, IO2 XIN FMIN, AMIN IFIN AIN BO1 to BO4, AOUT, IO1, IO2 DO PD IO=1mA AIN=1.3V VI=6.5V VI=13V VI=VDD VI=VDD VI=VDD VI=6.5V VI=0V VI=0V VI=0V VI=0V VI=0V VI=0V VO=13V VO=6.5V VO=VDD 0.01 0.01 6 2.0 4.0 8.0 2.0 4.0 8.0 VDD-0.1 1.0 0.5 1.0 0.2 1.0 0.2 1.0 1.6 0.5 5.0 5.0 11 22 44 200 5.0 5.0 11 22 44 200 5.0 5.0 200 200 Pins Conditions Ratings min typ 1.0 500 500 250 200 200 0.1VDD max unit MΩ kΩ kΩ kΩ kΩ kΩ V V V V V V V V V V V μA μA μA μA μA nA μA μA μA μA μA nA μA μA nA nA pF No.A0788-4/22 LC72131K, 72131KM Serial Data Timing CE tCH CL VIH DI VIL DO tSU tHD VIL VIH VIL VIH tCL VIH ≈ ≈≈ VIL VIH VIH ≈≈≈≈≈≈ tEL tES ≈≈≈≈≈≈≈ VIL VIL tEH tDC tDC tDH tLC Old New Internal data latch When stopped with CL low CE tCH CL VIH VIL VIH DI VIL DO tSU tHD VIH tCL VIH ≈ ≈ VIL VIH ≈ VIL tEL tES VIH tEH ≈≈≈≈≈≈≈ VIL tDC ≈≈≈≈≈≈ tDH tLC Old New Internal data latch When stopped with CL high Package Dimensions unit : mm (typ) 3059A [LC72131K] 21.0 22 12 Package Dimensions unit : mm (typ) 3036C [LC72131KM] 20 11 7.62 6.4 0.25 0.95 12.5 0.15 3.3 3.9 max (3.25) 0.35 1.27 SANYO : MFP20(300mil) 0.51min (0.8) 1.78 0.48 SANYO : DIP22S(300mil) 0.1 (0.4) No.A0788-5/22 0.63 1 11 (1.5) 1.7max 1 10 5.4 7.6 LC72131K, 72131KM Pin Assignments XOUT AOUT AMIN FMIN VDD VSS IFIN 12 11 IO1 Top view XOUT AOUT AMIN FMIN VDD VSS IFIN 11 10 IO1 Top view AIN PD IO2 12 9 BO4 AIN 22 21 20 19 18 17 16 15 14 13 LC72131K 1 XIN 2 NC 3 CE 4 DI 5 CL 6 DO 7 BO1 8 BO2 9 BO3 10 BO4 20 19 18 17 16 15 14 13 LC72131KM 1 XIN 2 CE 3 DI 4 CL 5 DO 6 BO1 7 BO2 8 BO3 Block Diagram IO2 NC PD XIN XOUT REFERENCE DIVIDER PHASE DETECTOR CHARGE PUMP PD FMIN 1/2 SWALLOW COUNTER 1/16,1/17 4bits UNLOCK DETECTOR AIN AOUT AMIN 12bits PROGRAMMABLE DIVIDER CE DI CL DO VDD VSS POWER ON RESET CCB I/F DATA SHIFT REGISTER LATCH UNIVERSAL COUNTER IFIN BO1 BO2 BO3 BO4 IO1 IO2 No.A0788-6/22 LC72131K, 72131KM Pin Functions Symbol XIN XOUT Pin No. LC72131K 1 22 LC72131KM 1 20 Type X'tal OSC Functions Crystal resonator connection (4.5MHz/7.2MHz) Circuit configuration FMIN 16 14 Local oscillator signal input FMIN is selected when the serial data input DVS bit is set to 1. The input frequency range is from 10 to 160MHz. The input signal passes through the internal divide-by-two prescaler and is input to the swallow counter. The divisor can be in the range 272 to 65535. However, since the signal has passed through the divide-by-two prescaler, the actual divisor is twice the set value. AMIN 15 13 Local oscillator signal input AMIN is selected when the serial data input DVS bit is set to 0. When the serial data input SNS bit is set to 1: • The input frequency range is 2 to 40MHz. • The signal is directly input to the swallow counter. • The divisor can be in the range 272 to 65535, and the divisor used will be the value set. When the serial data input SNS bit is set to 0: • The input frequency range is 0.5 to 10MHz. • The signal is directly input to a 12-bit programmable divider. • The divisor can be in the range 4 to 4095, and the divisor used will be the value set. CE DI CL DO 3 4 5 6 2 3 4 5 Chip enable Input data Clock Output data Set this pin high when inputting (DI) or outputting (DO) serial data. Inputs serial data transferred from the controller to the LC72131. Used as the synchronization clock when inputting (DI) or outputting (DO) serial data. Outputs serial data transferred from the LC72131 to the controller. The content of the output data is determined by the serial data DOC0 to DOC2. S S S VDD VSS BO1 BO2 BO3 BO4 17 21 7 8 9 10 15 19 6 7 8 9 Power supply Ground Output port The LC72131 power supply pin (VDD=4.5 to 5.5V) The power on reset circuit operates when power is first applied. The LC72131 ground Dedicated output pins The output states are determined by BO1 to BO4 bits in the serial data. Data: 0=open, 1=low A time base signal (8Hz) can be output from the BO1 pin. (When the serial data TBC bit is set to 1.) Care is required when using the BO1 pin, since it has a higher on impedance that the other output ports (pins BO2 to BO4). - IO1 IO2 11 13 10 12 I/O port I/O dual-use pins The direction (input or output) is determined by bits IOC1 and IOC2 in the serial data. Data: 0=input port, 1=output port When specified for use as input ports: The state of the input pin is transmitted to the controller over the DO pin. Input state: low=0 data value high=1 data value When specified for use as output ports: The output states are determined by the IO1 and IO2 bits in the serial data. Data: 0=open, 1=low These pins function as input pins following a power on reset. S Continued on next page. No.A0788-7/22 LC72131K, 72131KM Continued from preceding page. Symbol PD Pin No. LC72131K 18 LC72131KM 16 Type Charge pump output PLL charge pump output When the frequency generated by dividing the local oscillator frequency by N is higher than the reference frequency, a high level is output from the PD pin. Similarly, when that frequency is lower, a low level is output. The PD pin goes to the high impedance state when the frequencies match. AIN AOUT 19 20 17 18 LPF amplifier transistors The n-channel MOS transistor used for the PLL active low-pass filter. Functions Circuit configuration IFIN 12 11 IF counter Accepts an input in the frequency range 0.4 to 12MHz. The input signal is directly transmitted to the IF counter. The result is output starting the MSB of the IF counter using the DO pin. Four measurement periods are supported: 4, 8, 32, and 64ms. DI Control Data (Serial Data Input) Structure [1] IN1 mode address DI 0 0 0 1 0 1 0 0 First Data IN1 SNS DVS CTE P10 P11 P12 P13 P14 P15 XS R0 R1 R2 TEST1 (12) TEST (1) P-CTR (3) IF-CTR [2] IN2 mode address DI 1 0 0 1 0 1 0 0 First Data IN2 TEST0 TEST2 DOC0 DOC1 DOC2 IOC1 IOC2 DNC TBC DLC BO1 BO2 BO3 BO4 GT0 GT1 DZ0 DZ1 UL0 UL1 IO1 IO2 (10) PD-C (5) O-PORT (7) UNLOCK (3) IF-CTR (6) DO-C (8) DZ-C (13) Don’t care (9) TIME (11) IFS (4) IO-C IFS (2) R-CTR R3 No.A0788-8/22 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 LC72131K, 72131KM Control Data Functions No. (1) Control block/data Programmable divider data P0 to P15 Functions Data that sets the divisor of the programmable divider. A binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS. (*: don’t care) DVS 1 0 0 SNS * 1 0 LSB P0 P0 P4 Divisor setting (N) 272 to 65535 272 to 65535 4 to 4095 Actual divisor Twice the value of the setting The value of the setting The value of the setting Related data Note: P0 to P3 are ignored when P4 is the LSB. DVS, SNS Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches the input frequency range. (*: don’t care) DVS 1 0 0 SNS * 1 0 Input pin FMIN AMIN AMIN Input frequency range 10 to 160MHz 2 to 40MHz 0.5 to 10MHz Note: See the “Programmable Divider Structure” item for more information. (2) Reference divider data R0 to R3 Reference frequency (fref) selection data. R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference frequency 100kHz 50 25 25 12.5 6.25 3.125 3.125 10 9 5 1 3 15 * PLL INHIBIT + X'tal OSC STOP * PLL INHIBIT Note *: PLL INHIBIT The programmable divider block and the IF counter block are stopped, the FMIN, AMIN, and IFIN pins are set to the pull-down state (ground), and the charge pump goes to the high impedance state. XS Crystal resonator selection XS=0: 4.5MHz XS=1: 7.2MHz The 7.2MHz frequency is selected after the power-on reset. (3) IF counter control data CTE GT0, GT1 IF counter measurement start data CTE=1: Counter start =0: Counter reset Determines the IF counter measurement period. GT1 0 0 1 1 GT0 0 1 0 1 Measurement time (ms) 4 8 32 64 Wait time (ms) 3 to 4 3 to 4 7 to 8 7 to 8 IFS Note: See the “IF Counter Structure” item for more information. Continued on next page. No.A0788-9/22 LC72131K, 72131KM Continued from preceding page. No. (4) Control block/data I/O port specification data IOC1, IOC2 (5) Output port data BO1 to BO4 IO1, IO2 (6) DO pin control data DOC0 DOC1 DOC2 Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports Data: 0=open, 1=low The data=0 (open) state is selected after the power-on reset. Data that determines the DO pin output DOC2 0 0 0 0 1 1 1 1 DOC1 0 0 1 1 0 0 1 1 DOC0 0 1 0 1 0 1 0 1 Do pin state Open Low when the unlock state is detected end-UC *1 Open Open The IO1 pin state *2 The IO2 pin state *2 Open UL0, UL1 CTE IOC1 IOC2 Data: 0=input mode, 1=output mode Functions Specifies the I/O direction for the bidirectional pins IO1 and IO2. Related data IOC1 IOC2 The open state is selected after the power-on reset. Note: 1. end-UC: Check for IF counter measurement completion (1) Count start (2) Count end ≈ (3)CE: High zero to one), the DO pin automatically goes to the open state. measurement completion state. DO pin (1) When end-UC is set and the IF counter is started (i.e., when CTE is changed from (2) When the IF counter measurement completes, the DO pin goes low to indicate the (3) Depending on serial data I/O (CE: high) the DO pin goes to the open state. Note: 2. Goes to the open state if the I/O pin is specified to be an output port. Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE high) will be open, regardless of the state of the DO control data (DOC0 to DOC2). Also, the DO pin during a data output period (an OUT mode period with CE high) will output the contents of the internal DO serial data in synchronization with the CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2). (7) Unlock detection data UL0, UL1 Selects the phase error (φE) detection width for checking PLL lock. A phase error in excess of the specified detection width is seen as an unlocked state. UL1 0 0 1 1 UL0 0 1 0 1 φE detection width stopped 0 ±0.55μs ±1.11 Detector output Open φE is output directry φE is extended by 1 to 2ms ↑ DOC0 DOC1 DOC2 Note: In the unlocked state the DO pin goes low and the UL bit in the serial data becomes zero. ≈ Continued on next page. No.A0788-10/22 LC72131K, 72131KM Continued from preceding page. No. (8) Control block/data Phase comparator control data DZ0, DZ1 Functions • Controls the phase comparator dead zone. DZ1 0 0 1 1 DZ0 0 1 0 1 Dead zone mode DZA DZB DZC DZD Related data Dead zone width: DZA