LC72133M

Ordering number : ENN5427B CMOS IC LC72133M, 72133V PLL Frequency Synthesizer for Electronic Tuning Overview The LC72133M and LC72133V are a phase-locked loop frequency synthesizer LSI circuits for use in radio tuners. It supports low-voltage (2.7 to 3.6 V) operation and can implement high-performance AM/FM tuners easily. Functions • High speed programmable dividers — FMIN: 10 to 120 MHz ..........pulse swallower (built-in divide-by-two prescaler), VDD ≥ 2.7 V 10 to 130 MHz ..........pulse swallower (built-in divide-by-two prescaler), VDD ≥ 3.0 V — AMIN: 2 to 40 MHz ..............pulse swallower 0.5 to 10 MHz ...........direct division • IF counter — IFIN: 0.4 to 12 MHz ...........AM/FM IF counter • Reference frequencies — Twelve selectable frequencies (4.5 or 7.2 MHz crystal) 1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50 and 100 kHz • Phase comparator — Dead zone control — Unlock detection circuit — Deadlock clear circuit • Built-in MOS transistor for forming an active low-pass filter • I/O ports — Dedicated output ports: 4 — Input or output ports: 2 — Support clock time base output • Serial data I/O — Support CCB format communication with the system controller. (Compatible with LC72131) • Operating ranges — Supply voltage........................2.7 to 3.6 V — Operating temperature............–20 to +70°C • Package MFP20 SSOP20 • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 91099TH (OT)/22897HA (OT)/63196HA (OT) No. 5427-1/23 LC72133M, 72133V Package Dimensions unit: mm 3036B-MFP20 [LC72133M] 20 11 unit: mm 3179A-SSOP20 [LC72133V] 20 11 1.0 4.4 1.6max 0.15 0.43 0.1 6.35 5.4 7.6 1.8 max 12.6 1.5 0.15 0.625 1 10 1 6.7 10 0.1 0.22 0.65 0.35 1.27 0.59 SANYO: MFP20 SANYO: SSOP20 Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Supply voltage Maximum input voltage Symbol VDD max VIN1 max VIN2 max VIN3 max VO1 max Maximum output voltage VO2 max VO3 max IO1 max Maximum output current IO2 max IO3 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD CE, CL, DI, AIN XIN, FMIN, AMIN, IFIN IO1, IO2 DO XOUT, PD BO1 to BO4, IO1, IO2, AOUT BO1 AOUT, DO BO2 to BO4, IO1, IO2 Ta ≤ 70°C: LC72133M Ta ≤ 70°C: LC72133V Pins Ratings –0.3 to +5.5 –0.3 to +5.5 –0.3 to VDD + 0.3 –0.3 to +15 –0.3 to +5.5 –0.3 to VDD + 0.3 –0.3 to +15 0 to 3.0 0 to 6.0 0 to 6.0 180 160 –20 to +70 –40 to +125 Unit V V V V V V V mA mA mA mW mW °C °C 0.5 6.4 No. 5427-2/23 LC72133M, 72133V Allowable Operating Ranges at Ta = –20 to +70°C, VSS = 0 V Parameter Supply voltage Input high-level voltage Input low-level voltage Output voltage VO 2 fIN1 fIN2-1 fIN2-2 Input frequency fIN2-3 fIN3 fIN4 fIN5 VIN1 VIN2-1 VIN2-2 Input amplitude VIN3 VIN4 VIN5-1 VIN5-2 Supported crystals Xtal Symbol VDD VIH1 VIH2 VIL VO 1 VDD CE, CL, DI IO1, IO2 CE, CL, DI, IO1, IO2 DO BO1 to BO4, IO1, IO2, AOUT XIN FMIN FMIN FMIN AMIN AMIN IFIN XIN FMIN FMIN AMIN AMIN IFIN IFIN XIN, XOUT VIN1 VIN2-1 VIN2-2 VIN2-1, VDD ≥ 3.0 V VIN3, SNS = 1 VIN4, SNS = 0 VIN5 fIN1 fIN2-1, fIN2-3 fIN2-2 fIN3, SNS = 1 fIN4, SNS = 0 fIN5, IFS = 1 fIN6, IFS = 0 * Pins Conditions min 2.7 0.7 VDD 0.7 VDD 0 0 0 1 10 10 10 2 0.5 0.4 400 70 100 70 70 70 100 4.0 typ max 3.6 5.5 13 0.3 VDD 5.5 13 8 90 120 130 40 10 12 900 900 900 900 900 900 900 8.0 Unit V V V V V V MHz MHz MHz MHz MHz MHz MHz mVrms mVrms mVrms mVrms mVrms mVrms mVrms MHz Note: * Recommended crystal oscillator CI values: CI ≤ 120Ω (For a 4.5 MHz crystal) CI ≤ 70Ω (For a 7.2 MHz crystal) Crystal oscillator: HC-49/U (manufactured by Kinseki, Ltd.), CL = 12 pF C1 = C2 = 15 pF The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and other items. Therefore we recommend consulting with the manufacturer of the crystal for evaluation and reliability. C2 XOUT C1 XIN LC72133M LC72133V A11904 No. 5427-3/23 LC72133M, 72133V Electrical Characteristics for the Allowable Operating Ranges at Ta = –20 to +70°C, VSS = 0 V Parameter Symbol Rf1 Built-in feedback resistance Rf2 Rf3 Rf4 Built-in pull-down resistor Hysteresis Output high level voltage Rpd1 Rpd2 VHIS VOH1 VOL1 VOL2 Output low level voltage VOL3 VOL4 VOL5 IIH1 IIH2 Input high level current IIH3 IIH4 IIH5 IIH6 IIL1 IIL2 Input low level current IIL3 IIL4 IIL5 IIL6 Output off leakage current High level three-state off leakage current Low level three-state off leakage current Input capacitance IOFF1 IOFF2 IOFFH IOFFL CIN IDD1 XIN FMIN AMIN IFIN FMIN AMIN CE, CL, DI, IO1, IO2 PD PD BO1 DO BO2 to BO4, IO1, IO2 AOUT CE, CL, DI IO1, IO2 XIN FMIN, AMIN IFIN AIN CE, CL, DI IO1, IO2 XIN FMIN, AMIN IFIN AIN BO1 to BO4, AOUT, IO1, IO2 DO PD PD FMIN VDD Xtal = 7.2 MHz, fIN2 = 130 MHz, VIN2 = 70 mVrms PLL block stopped (PLL INHIBIT), Xtal oscillator operating (Xtal = 7.2 MHz) PLL block stopped Xtal oscillator stopped IO = –1 mA IO = 1 mA IO = 0.5 mA IO = 1 mA IO = 1 mA IO = 3 mA IO = 1 mA IO = 5 mA IO = 1 mA, AIN = 1.3 V VI = 5.5 V VI = 13 V VI = VDD VI = VDD VI = VDD VI = 5.5 V VI = 0 V VI = 0 V VI = 0 V VI = 0 V VI = 0 V VI = 0 V VO = 13 V VO = 5.5 V VO = VDD VO = 0 V 0.01 0.01 6 2 5 1.3 2.7 5.4 1.3 2.7 5.4 VDD – 1.0 1.0 0.6 1.2 0.25 0.75 0.25 1.25 0.5 5.0 5.0 8 15 30 200 5.0 5.0 8 15 30 200 5.0 5.0 200 200 Pins Conditions min typ 1.0 500 500 250 200 200 0.1 VDD max Unit MΩ kΩ kΩ kΩ kΩ kΩ V V V V V V V V V V μA μA μA μA μA nA μA μA μA μA μA nA μA μA nA nA pF mA Current drain IDD2 VDD 0.3 mA IDD3 VDD 30 μA No. 5427-4/23 LC72133M, 72133V Pin Assignment XIN 1 20 XOUT CE 2 S 19 VSS DI 3 S 18 AOUT CL 4 S 17 AIN DO 5 16 PD BO1 6 15 VDD BO2 7 14 FMIN BO3 8 13 AMIN BO4 9 S 12 IO2 IO1 10 S 11 IFIN Top view A11902 Block Diagram XIN 1 REFERENCE DIVIDER PHASE DETECTOR CHARGE PUMP 16 PD XOUT 20 17 AIN FMIN 14 1/2 SWALLOW COUNTER 1/16, 1/17 4bits UNLOCK DETECTOR 18 AOUT AMIN 13 12bits PROGRAMMABLE DIVIDER CE DI 2 3 CCB I/F DATA SHIFT REGISTER LATCH UNIVERSAL COUNTER 11 IFIN CL 4 DO 5 VDD 15 VSS 19 POWER ON RESET 6 7 8 9 10 IO1 12 IO2 A11903 BO1 BO2 BO3 BO4 No. 5427-5/23 LC72133M, 72133V Pin Functions Symbol Pin No. Type Functions Circuit configuration XIN XOUT 1 20 Xtal OSC • Crystal resonator connection (4.5/7.2 MHz) A11905 FMIN 14 Local oscillator signal input • FMIN is selected when the serial data input DVS bit is set to 1. • The input frequency range is from 10 to 130 MHz. • The input signal passes through the internal divide-bytwo prescaler and is input to the swallow counter. • The divisor can be in the range 272 to 65535. However, since the signal has passed through the divide-by-two prescaler, the actual divisor is twice the set value. Operating FMIN input frequency conditions 10 to 90 MHz 10 to 120 MHz 10 to 130 MHz Operating power- 2.7 to 3.6 V 2.7 to 3.6 V 3.0 to 3.6 V supply voltage Operating input 70 to 900 100 to 900 70 to 900 levels mVrms mVrms mVrms A11906 AMIN 13 Local oscillator signal input • AMIN is selected when the serial data input DVS bit is set to 0. • When the serial data input SNS bit is set to 1: — The input frequency range is 2 to 40 MHz. — The signal is directly input to the swallow counter. — The divisor can be in the range 272 to 65535, and the divisor used will be the value set. • When the serial data input SNS bit is set to 0: — The input frequency range is 0.5 to 10 MHz. — The signal is directly input to a 12-bit programmable divider. — The divisor can be in the range 4 to 4095, and the divisor used will be the value set. A11907 CE 2 Chip enable Set this pin high when inputting (DI) or outputting (DO) serial data. S A11908 CL 4 Clock • Used as the synchronization clock when inputting (DI) or outputting (DO) serial data. S A11910 DI 3 Data input • Inputs serial data transferred from the controller to the LC72133. S A11910 DO 5 Data output • Outputs serial data transferred from the LC72133 to the controller. The content of the output data is determined by the serial data DOC0 to DOC2. A11911 VDD 15 Power supply • The LC72133 power supply pin (VDD = 2.7 to 3.6 V) • The power on reset circuit operates when power is first applied. Continued on next page. No. 5427-6/23 LC72133M, 72133V Continued from preceding page. Symbol Pin No. Type Functions Circuit configuration VSS 19 Ground • The LC72133 ground — BO1 BO2 BO3 BO4 6 7 8 9 Output port • Dedicated output pins • The output states are determined by BO1 to BO4 bits in the serial data. Data: 0 = open, 1 = low • A time base signal (8 Hz) can be output from the BO1 pin. (When the serial data TBC bit is set to 1.) • Care is required when using the BO1 pin, since it has a higher on impedance than the other output ports (pins BO2 to BO4). • The data = 0 (open) state is selected after the power-on reset. A11912 IO1 IO2 10 12 I/O port • I/O dual-use pins • The direction (input or output) is determined by bits IOC1 and IOC2 in the serial data. Data: 0 = input port, 1 = output port • When specified for use as input ports: The state of the input pin is transmitted to the controller over the DO pin. Input state: low = 0 data value high = 1 data value • When specified for use as output ports: The output states are determined by the IO1 and IO2 bits in the serial data. Data: 0 = open, 1 = low • These pins function as input pins following a power on reset. S A11913 PD 16 Charge pump output • PLL charge pump output When the frequency generated by dividing the local oscillator frequency by N is higher than the reference frequency, a high level is output from the PD pin. Similarly, when that frequency is lower, a low level is output. The PD pin goes to the high impedance state when the frequencies match. A11914 AIN AOUT 17 18 LPF amplifier transistor • The n-channel MOS transistor used for the PLL active low-pass filter. A11915 IFIN 11 IF counter • Accepts an input in the frequency range 0.4 to 12 MHz. • The input signal is directly transmitted to the IF counter. • The result is output starting the MSB of the IF counter using the DO pin. • Four measurement periods are supported: 4, 8, 32, and 64 ms. A11916 No. 5427-7/23 LC72133M, 72133V Serial Data I/O Methods The LC72133 inputs and outputs data using the Sanyo CCB (computer control bus) audio LSI serial bus format. This LSI adopts an 8-bit address format CCB. I/O mode Address B0 B1 B2 B3 A0 A1 A2 A3 Function 1 IN1 (82) 0 0 0 1 0 1 0 0 • Control data input mode (serial data input) • 24 data bits are input. • See the “DI Control Data (serial data input) Structure” item for details on the meaning of the input data. 2 IN2 (92) 1 0 0 1 0 1 0 0 • Control data input mode (serial data input) • 24 data bits are input. • See the “DI Control Data (serial data input) Structure” item for details on the meaning of the input data. 3 OUT (A2) 0 1 0 1 0 1 0 0 Data output mode (serial data output) • The number of bits output is equal to the number of clock cycles. • See the “DO Output Data (Serial Data Output) Structure” item for details on the meaning of the output data. I/O mode determined CE ➀ CL ➁ DI B0 B1 B2 B3 A0 A1 A2 A3 First Data IN1/2 ➀ DO ➁ First Data OUT ➀ CL: Normal high ➁ CL: Normal low A11917 First Data OUT No. 5427-8/23 • IN2 Mode • IN1 Mode DI 1 0 DI (4) IO-C 0 0 P1 0 P2 P3 P4 P5 P6 P7 (1) P-CTR P8 P9 P10 P11 P12 P13 P14 P15 SNS DVS (3) IF-CTR CTE XS R0 (2) R-CTR R1 R2 R3 A11918 IOC1 P0 IOC2 0 IO1 1 1 IO2 0 0 Address Address First Data IN2 First Data IN1 (5) O-PORT 1 0 BO1 1 BO2 0 1. DI Control Data (Serial Data Input) Structure BO3 0 0 BO4 (13) Don't care DNC DOC0 (6) DO-C DOC1 DOC2 LC72133M, 72133V (7) UNLOCK UL0 UL1 (8) DZ-C DZ0 DZ1 (3) IF-CTR GT0 GT1 (9) TIME TBC (10) PD-C DLC (11) IFS IFS TEST0 (12) TEST TEST1 TEST2 A11919 No. 5427-9/23 LC72133M, 72133V 2. DI Control Data Functions No. Control block/data P0 to P15 Functions A binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS. (*: don’t care) DVS 1 0 0 (1) DVS, SNS SNS * 1 0 LSB P0 P0 P4 Divisor setting (N) 272 to 65535 272 to 65535 4 to 4095 Actual divisor Twice the value of the setting The value of the setting The value of the setting Related data Programmable divider data • Data that sets the programmable divider. Note: P0 to P3 are ignored when P4 is the LSB. • Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches the input frequency range. (*: don’t care) DVS 1 0 SNS * 1 Input pin FMIN AMIN Input frequency range 10 to 130 MHz 2 to 40 MHz 0 0 AMIN 0.5 to 10 MHz Note: See the “Programmable Divider” item for more information. Reference divider data R0 to R3 • Reference frequency (fref) selection data. R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Reference frequency (kHz) 100 50 25 25 12.5 6.25 3.125 3.125 10 9 5 1 3 15 PLL INHIBIT + Xtal OSC STOP (2) 1 1 1 1 PLL INHIBIT Note: PLL INHIBIT The programmable divider block and the IF counter block are stopped, the FMIN, AMIN, and IFIN pins are set to the pull-down state (ground), and the charge pump goes to the high impedance state. XS • Crystal resonator selection XS = 0: 4.5 MHz XS = 1: 7.2 MHz The 7.2 MHz frequency is selected after the power-on reset. • IF counter measurement start data CTE = 1: Counter start CTE = 0: Counter reset • Determines the IF counter measurement period. GT1 0 0 1 1 I/O port specification data IOC1, IOC2 Output port data BO1 to BO4, IO1, IO2 GT0 0 1 0 1 Measurement time (ms) 4 8 32 64 Wait time (ms) 3 to 4 3 to 4 7 to 8 7 to 8 IFS IF counter control data CTE GT0, GT1 (3) Note: See the “IF Counter” item for more information. (4) • Specifies the I/O direction for the bidirectional pins IO1 and IO2. Data: 0 = input mode, 1 = output mode • Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports Data: 0 = open, 1 = low • The data = 0 (open) state is selected after the power-on reset. IOC1 IOC2 (5) Continued on next page. No. 5427-10/23 LC72133M, 72133V Continued from preceding page. No. Control block/data DO pin control data DOC0, DOC1, DOC2 Functions • Data that determines the DO pin output DOC2 0 0 0 0 1 1 1 1 DOC1 0 0 1 1 0 0 1 1 DOC0 0 1 0 1 0 1 0 1 DO pin state Open Low when the unlock state is detected end-UC*1 Open Open The IO1 pin state*2 The IO2 pin state*2 Open Related data The open state is selected after the power-on reset. Note: 1. end-UC: Check for IF counter measurement completion (6) UL0, UL1, CTE, IOC1, IOC2 DO pin ➀ Counter start ➁ Counter complete ➂ CE: high A11920 ➀ When end-UC is set and the IF counter is started (i.e., when CTE is changed from zero to one), the DO pin automatically goes to the open state. ➁ When the IF counter measurement completes, the DO pin goes low to indicate the measurement completion state. ➂ Depending on serial data I/O (CE: high) the DO pin goes to the open state. 2. Goes to the open state if the I/O pin is specified to be an output port. Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE high) will be open, regardless of the state of the DO control data (DOC0 to DOC2). Also, the DO pin during a data output period (an OUT mode period with CE high) will output the contents of the internal DO serial data in synchronization with the CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2). Unlock detection data UL0, UL1 • Selects the phase error (øE) detection width for checking PLL lock. A phase error in excess of the specified detection width is seen as an unlocked state. UL1 0 (7) 0 1 1 UL0 0 1 0 1 0 ±0.55 μs ±1.11 øE detection width Stopped Open øE is output directly øE is extended by 1 to 2 ms øE is extended by 1 to 2 ms Detector output DOC0, DOC1, DOC2 Note: In the unlocked state the DO pin goes low and the UL bit in the serial data becomes zero. Phase comparator control data DZ0, DZ1 • Controls the phase comparator dead zone. DZ1 0 (8) 0 1 1 DZ0 0 1 0 1 DZA DZB DZC DZD Dead zone mode Dead zone widths: DZA < DZB < DZC < DZD (9) Clock time base TBC Charge pump control data DLC Setting TBC to one causes an 8 Hz, 40% duty clock time base signal to be output from the BO1 pin. (BO1 data is invalid in this mode.) • Forcibly controls the charge pump output. DLC 0 (10) 1 Normal operation Forced low Charge pump output BO1 Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO oscillator stopping, deadlock can be cleared by forcing the charge pump output to low and setting Vtune to VCC. (This is the deadlock clearing circuit.) Continued on next page. No. 5427-11/23 LC72133M, 72133V Continued from preceding page. No. (11) Control block/data IF counter control data IFS LSI test data TEST 0 to TEST 2 (12) Functions • Note that if this value is set to zero the system enters input sensitivity degradation mode, and the sensitivity is reduced to 10 to 30 mV rms. * See the “IF Counter Operation” item for details. • LSI test data TEST0 TEST1 These values must all be set to 0. TEST2 These test data are set to 0 automatically after the power-on reset. (13) DNC Don’t care. This data must be set to 0. Related data 3. DO Output Data (Serial Data Output) • OUT Mode Address DI 0 1 0 1 0 1 0 0 First Data OUT C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 UL C9 C8 C7 C6 C5 C4 C3 C2 C1 (1) IN-PORT (2) UNLOCK (3) IF-CTR ✩ : "0" data A11921 4. DO Output Data No. Control block/data I/O port data I2, I1 (1) Functions • Latched from the pin states of the IO1 and IO2 I/O ports. • These values follow the pin states regardless of the input or output setting. • Data is latched at the point where the circuit enters data output mode (OUT mode). I1 ← IO1 pin state I2 ← IO2 pin state (2) PLL unlock data UL IF counter binary data C19 to C0 High: 1 Low: 0 UL0, UL1 CTE, GT0, GT1 Related data IOC1, IOC2 • Latched from the state of the unlock detection circuit. UL ← 0: Unlocked UL ← 1: Locked or detection stopped mode • Latched from the value of the IF counter (20-bit binary counter). C19 ← MSB of the binary counter C0 ← LSB of the binary counter (3) C0 No. 5427-12/23 I2 I1 ✩ DO LC72133M, 72133V 5. Serial Data Input (IN1/IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75 μs, tLC < 0.75 μs ➀ CL: Normal high CE tEL tES tEH CL tSU DI Internal data A11922 tHD B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC ➁ CL: Normal low tEL CE tES tEH CL tSU DI Internal data A11923 tHD B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC 6. Serial Data Output (OUT) tSU, tHD, tEL, tES, tEH ≥ 0.75 μs, tDC, tDH < 0.35 μs ➀ CL: Normal high tEL CE tES tEH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I2 tDC I1 UL C3 C2 C1 tDH C0 A11924 ➁ CL: Normal low tEL CE tES tEH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I2 tDC I1 UL C3 C2 C1 tDH C0 A11925 Note: Since the DO pin is an n-channel open-drain circuit, the time for the data to change (t DC and tDH) will differ depending on the value of the pull-up resistor and printed circuit, board capacitance. No. 5427-13/23 LC72133M, 72133V 7. Serial Data Timing VIH VIL tCH CL VIH VIL tCL VIL tEL DI VIH VIL tSU DO tLC Internal data Latch When stopped with CL low Old New A11926 CE VIH tES VIL VIH tEH VIH VIL tHD tDC tDC tDH CE tCL CL VIH VIL tCH VIH VIH VIL VIL tEL tES VIH tEH DI VIH VIL tSU VIH VIL tHD tDC tDH DO tLC Internal data Latch When stopped with CL high Old New A11927 Parameter Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time Data latch change time Symbol tSU tHD tCL tCH tEL tES tEH tLC tDC DO, CL DO, CE DI, CL DI, CL CL CL CE, CL CE, CL CE, CL Pins Conditions min 0.75 0.75 0.75 0.75 0.75 0.75 0.75 typ max Unit μs μs μs μs μs μs μs 0.75 Differs depending on the value of the pull-up resistor and the printed circuit board capacitances. μs Data output time tDH 0.35 μs No. 5427-14/23 LC72133M, 72133V Programmable Divider Structure 4bits FMIN 1/2 (A) 12bits Swallow Counter (B) AMIN (C) Programmable Divider fvco/N PD fref øE DVS SNS fvco = fref × N A11928 DVS A B C 1 0 0 SNS * 1 0 Input pin FMIN AMIN AMIN Set divisor 272 to 65535 272 to 65535 4 to 4095 Actual divisor: N Twice the set value The set value The set value Input frequency range (MHz) 10 to 130 2 to 40 0.5 to 10 Note: * Don’t care. 1. Programmable Divider Calculation Examples • FM, 50 kHz steps (DVS = 1, SNS = *, FMIN selected) FM RF = 80.0 MHz (IF = –10.7 MHz) FM VCO = 69.3 MHz PLL fref = 25 kHz (R0 to R1 = 1, R2 to R3 = 0) 69.3 MHz (FM VCO) ÷ 25 kHz (fref) ÷ 2 (FMIN: divide-by-two prescaler) = 1386 → 056A (HEX) A 0 P0 1 P1 0 P2 1 P3 0 P4 1 P5 6 1 P6 0 P7 1 P8 0 P9 5 1 P10 0 P11 0 P12 0 P13 0 0 P14 0 P15 * SNS 1 DVS CTE XS 1 R0 1 R1 0 R2 0 R3 A11929 • SW, 5 kHz steps (DVS = 0, SNS = 1, AMIN high speed side selected) SW RF = 21.75 MHz (IF = +450 kHz) SW VCO = 22.20 MHz PLL fref = 5 kHz (R0 = R2 = 0, R1 = R3 = 1) 22.2 MHz (SW VCO) ÷ 5 kHz (fref) = 4440 → 1158 (HEX) 8 0 P0 0 P1 0 P2 1 P3 1 P4 0 P5 5 1 P6 0 P7 1 P8 0 P9 1 0 P10 0 P11 1 P12 0 P13 1 0 P14 0 P15 1 SNS 0 DVS CTE XS 0 R0 1 R1 0 R2 1 R3 A11930 • MW, 10 kHz steps (DVS = 0, SNS = 0, AMIN low-speed side selected) MW RF = 1000 kHz (IF = +450 kHz) MW VCO = 1450 kHz PLL fref = 10 kHz (R0 to R2 = 0, R3 = 1) 1450 kHz (MW VCO) ÷ 10 kHz (fref) = 145 → 091 (HEX) 1 9 0 P6 0 P7 1 P8 0 P9 0 P10 1 P11 0 P12 0 P13 0 0 P14 0 P15 0 SNS 0 DVS CTE XS 0 R0 0 R1 0 R2 1 R3 **** P0 P1 P2 P3 1 P4 0 P5 A11931 No. 5427-15/23 LC72133M, 72133V IF Counter Structure The LC72133 IF counter is a 20-bit binary counter. The result, i.e., the counter’s MSB, can be read serially from the DO pin. IF counter (20-bit binary counter) (Fc) IFIN L S B (GT) 0 to 3 M S B 4 to 7 8 to 11 12 to 15 16 to 19 CTE DO pin (C) 4/8/32/64 ms GT0 GT1 C = Fc × GT A11932 GT1 0 0 1 1 GT0 0 1 0 1 Measurement time Measurement period (GT) (ms) 4 8 32 64 Wait time (twu) (ms) 3 to 4 3 to 4 7 to 8 7 to 8 The IF frequency (Fc) is measured by determining how many pulses were input to an IF counter in a specified measurement period, GT. Fc = C GT (C = Fc × GT) C: Count value (number of pulses) 1. IF Counter Frequency Calculation Examples • When the measurement period (GT) is 32 ms, the count (C) is 53980 hexadecimal (342400 decimal): IF frequency (Fc) = 342400 ÷ 32 ms = 10.7 MHz 5 0 C19 UL I2 I1 1 C18 0 C17 1 C16 0 C15 0 C14 3 1 C13 1 C12 1 C11 0 C10 9 0 C9 1 C8 1 C7 0 C6 8 0 C5 0 C4 0 C3 0 C2 0 0 C1 0 C0 A11933 • When the measurement period (GT) is 8 ms, the count (C) is E10 hexadecimal (3600 decimal): IF frequency (Fc) = 3600 ÷ 8 ms = 450 kHz 0 0 C19 UL I2 I1 0 C18 0 C17 0 C16 0 C15 0 C14 0 0 C13 0 C12 1 C11 1 C10 E 1 C9 0 C8 0 C7 0 C6 1 0 C5 1 C4 0 C3 0 C2 0 0 C1 0 C0 A11934 No. 5427-16/23 LC72133M, 72133V 2. IF Counter Operation CE Data with CTE = 1 Measurement period Frequency measurement period GT Wait time IFIN Count end (end-UC) A11935 Count start Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0. The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the LC72133 when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the period between the point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF counter at the end of the measurement period must be read out during the period that CTE is 1. This is because the IF counter is reset when CTE is set to 0. Note: When operating the IF counter, the control microprocessor must first check the state of the IF-IC SD (station detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an IF count operation. Autosearch techniques that use only the IF counter are not recommended, since it is possible for IF buffer leakage output to cause incorrect stops at points where there is no station. IFIN minimum input sensitivity standard f (MHz) IFS 1: Normal mode 0: Degradation mode 0.4 ≤ f < 0.5 70 mVrms (0.5 to 5 mVrms) 100 mVrms (10 to 15 mVrms) 0.5 ≤ f < 8 70 mVrms 100 mVrms 8 ≤ f ≤ 12 70 mVrms (2 to 10 mVrms) 100 mVrms (30 to 50 mVrms) Note: Values in parentheses are actual performance values presented as reference data. No. 5427-17/23 LC72133M, 72133V Unlock Detection Timing 1. Unlock Detection Determination Timing Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle, unlock determination requires a time longer than the period of the reference frequency. However, immediately after changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the reference frequency. CE DATA LATCH VCO/N Ncounter fref Old data New data Old divisor N New divisor N' øERROR (unlock) The divisor N is not updated in the first period. Note: After changing the divisor, øERROR is output after two fref periods. A11936 Figure 1 Unlocked State Detection Timing For example, if fref is 1 kHz, i.e., the period is 1 ms, after changing the divisor N, the system must wait at least 2 ms before checking for the unlocked state. Unlock detection circuit UNLOCK ÷R VCO ÷N fref VCO/N Preset Phase comparator øERROR L. P. F DATA LATCH A11937 Figure 2 Circuit Structure No. 5427-18/23 LC72133M, 72133V 2. Unlock Detection Software Data input Data output ➀ Data output ➁ CE N Old data New data VCO frequency øERROR Unlock (UL) serial data input Unlock detection pin output Locked Unlocked Locked Figure 3 3. Unlocked State Data Output Using Serial Data Output A11938 In the LC72133, once an unlocked state occurs, the unlocked state serial data (UL) will not be reset until a data input (or output) operation is performed. At the data output ① point in Figure 3, although the VCO frequency has stabilized (locked), since no data output has been performed since the divisor N was changed the unlocked state data remains in the unlocked state. As a result, even though the frequency has stabilized (locked), the system remains (from the standpoint of the data) in the unlocked state. Therefore, the unlocked state data acquired at data output ①, which occurs immediately after the divisor N was changed, should be treated as a dummy data output and ignored. The second data output (data output ➁) and following outputs are valid data. Divisor N modification (data input) ............... Wait for at least two reference frequency periods. Dummy data output Valid data output ............... Valid data can be output at intervals of one reference frequency period or longer Locked? * YES NO Note: Locking state determination is more reliable if it is based on reading valid output data several times. Locked State Determination Flowchart 4. Directly Outputting Unlocked State Data from the DO Pin (Set by the DO pin control data) Since the locking state (high = locked, low = unlocked) is output directly from the DO pin, the dummy data processing described in section 3 above is not required. After changing the divisor N, the locking state can be checked after waiting at least two reference frequency periods. No. 5427-19/23 LC72133M, 72133V Clock Time Base Usage Notes The pull-up resistor used on the clock time base output pin (BO1) should be at least 100 kΩ. Also, to prevent chattering we recommend using a Schmitt input at the controller (microprocessor) that receives this signal. This is to prevent degrading the VCO C/N characteristics when a loop filter is formed using the built-in low-pass filter transistor. Since the clock time base output pin and the low-pass filter have a common ground internal to the IC, it is necessary to minimize the time base output pin current fluctuations and to suppress their influence on the low-pass filter. VDD LC72133M LC72133V Rt ≥ 100 kΩ BO1 Time base output Microprocessor S Schmitt input PD VCC AIN AOUT Loop filter VCO Vt A11939 Other Items 1. Notes on the Phase Comparator Dead Zone DZ1 0 0 1 1 DZ0 0 1 0 1 Dead zone mode DZA DZB DZC DZD Charge pump ON/ON ON/ON OFF/OFF OFF/OFF Dead zone – –0 s –0 s +0 s + +0 s Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the ON/ON state, the loop can easily become unstable. This point requires special care when designing application circuits. The following problems may occur in the ON/ON state. • Side band generation due to reference frequency leakage • Side band generation due to both the correction pulse envelope and low frequency leakage Schemes in which a dead zone is present (OFF/OFF) have good loop stability, but have the problem that acquiring a high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with schemes in which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective to select DZA or DZB, which have no dead zone, in applications which require an FM S/N ratio in excess of 90 to 100 dB, or in which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting DZC or DZD, which provide a dead zone, for applications which do not require such a high FM signal-to-noise ratio and in which either AM stereo is not used or an adequate AM stereo pilot margin can be achieved. No. 5427-20/23 LC72133M, 72133V Dead Zone The phase comparator compares fp to a reference frequency (fr) as shown in Figure 4. Although the characteristics of this circuit (see Figure 5) are such that the output voltage is proportional to the phase difference ø (line A), a region (the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide a high S/N ratio. However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularlypriced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF signal. RF MIX Reference Divider fr fp Phase Detector LPF VCO (B) ø (ns) Dead Zone A11941 V (A) Programmable Divider Figure 4 A11940 Figure 5 2. Notes on the FMIN, AMIN, and IFIN Pins Coupling capacitors must be placed as close as possible to their respective pin. A capacitance of about 100 pF is desirable. In particular, if a capacitance of 1000 pF or over is used for the IF pin, the time to reach the bias level will increase and incorrect counting may occur due to the relationship with the wait time. 3. Notes on IF Counting → SD must be used in conjunction with the IF counting time When using IF counting, always implement IF counting by having the microprocessor determine the presence of the IF-IC SD (station detect) signal and turn on the IF counter buffer only if the SD signal is present. Schemes in which auto-searches are performed with only IF counting are not recommended, since they can stop at points where there is no signal due to leakage output from the IF counter buffer. 4. DO Pin Usage Techniques In addition to data output mode times, the DO pin can also be used to check for IF counter count completion and for unlock detection output. Also, an input pin state can be output unchanged through the DO pin and input to the controller. 5. Power Supply Pins A capacitor of at least 2000 pF must be inserted between the power supply VDD and VSS pins for noise exclusion. This capacitor must be placed as close as possible to the VDD and VSS pins. 6. VCO setup Applications must be designed so that the VCO (local oscillator) does not stop, even if the control voltage (Vtune) goes to 0V. If it is possible for the oscillator to stop, the application must use the control data (DLC) to temporarily force Vtune to VCC to prevent the deadlock from occuring. (Deadlock clear circuit) 7. Front end connection example Since this product is designed with the relatively high resistance of 200 kΩ for the pull-down (on) resistors built in to the FMIN and AMIN pins, a common AM/FM local oscillator buffer can be used as shown in the following circuit. No. 5427-21/23 LC72133M, 72133V FMIN FM OSC OSC buffer out On resistance: 200 kΩ AMIN AM OSC On resistance: 200 kΩ FE PLL A10186 Pin States After the Power ON Reset XIN CE DI XOUT VSS AOUT Open Open Open Open Open Input port DO BO1 BO2 BO3 BO4 IO1 LC72133M LC72133V CL AIN PD VDD FMIN AMIN IO2 IFIN A11943 Input port No. 5427-22/23 LC72133M, 72133V Application System Example This section is susceptible to noise due to its high impedance. Therefore, the pattern lines should be kept as short as possible and this area should be coverd with a ground pattern. μ-COM CE XIN 1 20 XOUT VCC CE 2 S 19 VSS 18 AOUT DI DI 3 S CL Unlock SD end-UC IFcount ST-Indie CL 4 S 17 AIN FMVCO DO DO 5 LC72133M LC72133V 16 PD BO1 6 15 VDD 14 FMIN AMVCO BO2 7 BO3 8 S 13 AMIN SD TUNER-System BO4 9 S 12 IO2 IO1 10 11 IFIN FM/AM-IF IF-Request FM/AM MONO/ST ST-Indicate A11944 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1999. Specifications and information herein are subject to change without notice. PS No.5427-23/23