LC74731

Ordering number : ENN*6526 CMOS IC LC74731W,74732W On-Screen Display Controller Preliminary Overview The LC74731W and LC74732W are on-screen display CMOS ICs that display characters and patterns on a TV screen under the control of a microcontroller. These ICs display 16 × 16-dot characters and up to 12 lines of text with 24 characters per line. • Character color: Eight colors in character units (in internal synchronization mode): 2 fsc and 4 fsc (Black, red, green, yellow, blue, magenta, cyan, and white) • Character background color: Eight colors (in internal synchronization mode): 2 fsc and 4 fsc (Black, red, green, yellow, blue, magenta, cyan, and transparent) • Screen background color: Eight colors (in internal synchronization mode): 2 fsc and 4 fsc (Black, red, green, yellow, blue, magenta, cyan, and white) • External control inputs: Serial interface with an 8-bit data size. • Built-in sync separator circuit • Video outputs: NTSC, PAL, PALM, PALN, NTSC 4.43, and PAL 60 composite video signal outputs • Supports Y/C input Features • Text structure: 12 lines × 24 characters (Up to 288 characters) • Character format: 16 × 16 dots Character display clock frequency: about 9 MHz • Character sizes: Four sizes each in the horizontal and vertical directions with the size set in line units. • Number of characters supported: LC74731W:256 (internal) LC74732W:512 (internal) Up to 8192 using an external ROM (for Japanese) [Reference] JIS X0298 (1990): 6877 characters JIS level 1 kanji: 2965 characters JIS level 2 kanji: 3388 characters Special characters: 524 characters • Display start positions: 128 positions each in the horizontal and vertical directions • Blinking, reverse video, reversed blinking, and character outlining: May be specified in individual character units. • Blinking types: Two types with periods of about 1.0 and about 0.5 seconds. • Blanking: The whole font area (16 ×16 dots) can be blanked in line units (Four types: no blanking, character size blanking, character plus outlining size blanking, and whole area up to adjacent character blanking) • Line spacing control: Zero to seven scan lines, in line units Package Dimensions [LC74731W,74732W] 12.0 10.0 1.25 48 49 0.5 0.18 1.25 33 32 0.15 12.0 10.0 0.5 1.25 64 17 1 16 0.5 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 63000RM (OT) No. 6526-1/38 0.1 0.5 SANYO: SQFP64 1.7max 1.25 LC74731W,74732W Pin Assignment OE CE D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 50 A5 49 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS1 XTALin XTALout CTRL1 OSCin OSCout MUTE CDLR SYNCjdg/Rout CHARA/Gout BLANK/Bout IEOUT/BLKout OUTMOD CS SIN SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (V) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VDD1 RST SEPin SEPout 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CVout SYNin (H) No. 6526-2/38 HFTin VDD2 VSS2 Cbias Cout CVcr -NC- -NC- Yout CVin -NC- -NC- Cin Yin LC74731W,74732W Pin Functions Pin No. 1 2 3 4 5 6 Pin VSS1 Xtalin Xtalout CTRL1 OSCin OSCout This is an active-low input with hysteresis characteristics (MORE+). When low, the CVout, Yout, and Cout outputs are set to either, (1) CSYNC, CSYNC, PE, or (2) PE PE, PE. In the initial state, (1) is selected. This setting is switched by commands. Connection for the resistor used to adjust the background color phase Ground Crystal oscillator connections Function Ground connection. (Digital system ground) Connections for the crystal element and capacitors that form the internal sync signal generating crystal oscillator. Xtalin can also be used to input an external clock signal. (2fsc or 4fsc) Description Switches the crystal oscillator Selects external clock input mode or crystal oscillator mode. Low: crystal oscillator mode, high: input external clock input mode. LC oscillator connections Connections for the coil and capacitor that form the character output dot clock generation oscillator. 7 MUTE Muting control input 8 CDLR Background color phase adjustment 9 SYNCJDG /Rout Outputs the result of the judgment as to whether or not the external sync signal is present. External sync signal judgment A high level is output when a sync signal is present. output (Rout output) The dot clock (LC oscillator) is output when RST is low. (The IC can be set up to not output this signal during resets by commands.) Character output (Gout output) Blank output (Bout output) Character signal output Blank signal output pin Internal synchronization (high)/external synchronization (low) state output pin Switches between output from pins 9 to 12 and input to pin 32. Low: normal operation, high: RGB output supported Serial data input enable Serial data input is enabled when low. more+ (Hysteresis input characteristics) Serial data input more+ (Hysteresis input characteristics) Serial data input clock input more+ (Hysteresis input characteristics) Composite video signal level adjustment power supply. (Analog system power supply) Color (C) signal output This pin must either be left open or connected to ground. Color signal input Chrominance bias output Color (C) signal input Chrominance signal bias level output This pin must be either left open or connected to ground. Luminance signal output Luminance signal (Y) output This pin must be either left open or connected to ground. Luminance signal input Ground Video signal output Luminance signal (Y) input Ground Composite video signal output This pin must either be left open or connected to ground. Video signal input Video signal input Halftone signal input Sync separator circuit input Composite video signal input SECAM chrominance signal input Halftone signal input Video signal input to the internal sync separator circuit 10 11 12 13 CHARA/Gout BLANK/Bout Internal/external output IEout/BLKout (BLKout output) OUTMOD Output switching input 14 CS Enable input 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SIN SCLK VDD2 COUT NC CIN CBIAS NC YOUT NC YIN VSS2 CVOUT NC CVIN CVCR HFTin SYNin SEPout SEPin RST VDD1 Data input Clock input Power supply Color signal output Composite sync signal output Composite sync signal output from the internal sync separator circuit Vertical sync signal input Reset input Power supply (+5 V) Vertical sync signal input MORE+ (Hysteresis input characteristics) System reset input A built-in pull-up resistor can be included in this pin’s input circuit. (Hysteresis input characteristics) Power supply (+5 V: digital system power supply) Continued on next page. No. 6526-3/38 LC74731W,74732W Continued from preceding page. Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OE CE D7 D6 D5 D4 D3 D2 D1 D0 Function Address output 17 Address output 16 Address output 15 Address output 14 Address output 13 Address output 12 Address output 11 Address output 10 Address output 9 Address output 8 Address output 7 Address output 6 Address output 5 Address output 4 Address output 3 Address output 2 Address output 1 Address output 0 Output enable Chip enable Data input 7 Data input 6 Data input 5 Data input 4 Data input 3 Data input 2 Data input 1 Data input 0 ROM address output 17 ROM address output 16 ROM address output 15 ROM address output 14 ROM address output 13 ROM address output 12 ROM address output 11 ROM address output 10 ROM address output 9 ROM address output 8 ROM address output 7 ROM address output 6 ROM address output 5 ROM address output 4 ROM address output 3 ROM address output 2 ROM address output 1 ROM address output 0 ROM output enable output. This is an active-low output. ROM chip enable output. This is an active-low output. ROM data input 7. MORE+ (Hysteresis input characteristics) ROM data input 6. MORE+ (Hysteresis input characteristics) ROM data input 5. MORE+ (Hysteresis input characteristics) ROM data input 4. MORE+ (Hysteresis input characteristics) ROM data input 3. MORE+ (Hysteresis input characteristics) ROM data input 2. MORE+ (Hysteresis input characteristics) ROM data input 1. MORE+ (Hysteresis input characteristics) ROM data input 0. MORE+ (Hysteresis input characteristics) Description No. 6526-4/38 LC74731W,74732W Specifications Maximum Ratings at Ta = 25°C Parameter Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD VIN VOUT Pdmax Topr Tstg VDD1 and VDD2 All input pins SYNCJDG, BLANK, CHARA, SEPOUT, A0 to A17, CE, and OE Conditions Ratings min VSS – 0.3 VSS – 0.3 VSS – 0.3 — –30 –40 max VSS + 6.5 VDD1 + 0.3 VDD1 + 0.3 275 +70 +125 Unit V V V mW °C °C Recommended Operating Conditions Parameter Symbol VDD1 VDD2 VDD1 VDD2 VIH1 High-level input voltage VIH2 VIH3 VIH4 VIL1 Low-level input voltage VIL2 VIL3 Pull-up resistor Composite video signal input voltage Input voltage RPU VIN1 VIN2 VIN3 VDD1 VDD2 VDD1 VDD2 CS, SIN, SCLK, SEPIN, and MUTE RST CTRL1 and OUTMOD D0 to D7 RST, CS, SIN, SCLK, SEPIN, and MUTE CTRL1 and OUTMOD D0 to D7 RST, CS, SIN, SCLK, and MUTE (when the pull-up resistor option is specified) CVIN and CVCR SYNIN XtalIN (when an external clock input is used) fin = 2 fsc, 4 fsc VDD1 = 5 V VDD1 = 5 V VDD1 = 5 V Conditions Ratings min 4.5 4.5 2.7 2.7 0.8 VDD1 0.8 VDD1 0.7 VDD1 0.8 VDD1 VSS – 0.3 VSS – 0.3 VSS – 0.3 25 — 1.5 — typ 5.0 5.0 5.0 5.0 — — — — — — — 50 2.0 2.0 — 7.159 14.318 — — — 8.867 17.734 10 — — — max 5.5 6.5 5.5 6.5 5.5 VDD1 + 0.3 VDD1 + 0.3 5.5 0.2 VDD1 0.3 VDD1 0.2 VDD1 90 — 2.5 5.0 Unit V V V V V V V V V V V kΩ Vp-p Vp-p Vp-p MHz MHz MHz MHz MHz Supply voltage Supply voltage [Only for RGB output] The XtalIN and XtalOUT oscillator pins (2 fsc: NTSC) FOSC1 The XtalIN and XtalOUT oscillator pins (4 fsc: NTSC) The XtalIN and XtalOUT oscillator pins (2 fsc: PAL) The XtalIN and XtalOUT oscillator pins (4 fsc: PAL) FOSC2 The OSCin and OSCout oscillator pins (LC oscillator) Oscillator frequency Note: If the Xtalin pin is used in clock input mode, applications must take adequate input noise prevention and reduction measures. No. 6526-5/38 LC74731W,74732W Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified. Parameter Input off leakage current Output off leakage current Symbol Ileak1 Ileak2 VOH11 VOH12 High-level output voltage VOH21 VOH22 VOL11 VOL12 Low-level output voltage VOL21 VOL22 IIH Input current IIL IDD1 IDD2 Pin CVIN, CVCR, CIN, and YIN CVOUT, COUT, and YOUT SYNCJDG, SETPOUT, BLANK, CHARA, and IEOUT SYNCJDG, SETPOUT, BLANK, CHARA, and IEOUT A0 to A17, OE, and CE A0 to A17, OE, and CE SYNCJDG, SEPOUT, BLANK, CHARA, and IEOUT SYNCJDG, SEPOUT, BLANK, CHARA, and IEOUT A0 to A17, OE, and CE A0 to A17, OE, and CE RST, CS, SIN, SCLK, CTRL1, MUTE, and OUTMOD CS, SIN, SCLK, CTRL1, and OUTMOD VDD1 VDD2 VDD1 = 5.5 to 4.5 V IOH = –1.0 mA VDD1 = 4.4 to 2.7 V IOH = –0.5 mA VDD1 = 5.5 to 4.5 V IOH = –1.0 mA VDD1 = 4.4 to 2.7 V IOH = –0.5 mA VDD1 = 5.5 to 4.5 V IOL = 1.0 mA VDD1 = 4.4 to 2.7 V IOL = 0.5 mA VDD1 = 5.5 to 4.5 V IOL = 1.0 mA VDD1 = 4.4 to 2.7 V IOL = 0.5 mA VIN = VDD1 VIN = VSS1 All outputs: open Xtal: 17.734 MHz LC: 10 MHz VDD2 = 5 V Conditions Ratings min — — 0.9 VDD1 0.9 VDD1 0.9 VDD1 0.9 VDD1 — — — — — –1 typ — — — — — — — — — — — — max 1 1 — — — — 0.1 VDD1 0.1 VDD1 0.1 VDD1 0.1 VDD1 1 — Unit µA µA V V V V V V V V µA µA Operating current drain — — 40 20 mA mA Continued on next page. No. 6526-6/38 LC74731W,74732W Continued from preceding page. Parameter Symbol Pin Conditions (1) SYNC level VSN (2) (3) (1) Pedestal level VPD (2) (3) (1) Color burst low level VCBL (2) (3) (1) Color burst high level VCBH CVOUT Background color 1 low level VRSL1 (1): When SYNC – LEVEL = 0.8 V VDD1 = 5.0 V (2): When SYNC – LEVEL = 1.0 V VDD2 = 5.0 V (3): When SYNC – LEVEL = 1.4 V Background color 1 high level VRSH1 (2) (3) (1) (2) (3) (1) (2) (3) (1) Background color 2 low level VRSL2 (2) (3) (1) Background color 2 high level VRSH2 (2) (3) (1) Outlining level 1 VBK1 (2) (3) (1) Outlining level 2 VBK2 (2) (3) (1) Outlining level 3 VBK3 (2) (3) (1) Character level 1 VCHA1 (2) (3) (1) Character level 3 VCHA3 (2) (3) Ratings min typ 0.80 1.00 1.40 1.37 1.57 1.97 1.07 1.27 1.67 1.67 1.87 1.27 1.23 1.43 1.83 2.37 2.57 2.97 1.52 1.72 2.12 2.01 2.21 2.61 1.50 1.70 2.10 1.80 2.00 2.40 2.08 2.28 2.68 2.65 2.85 3.25 2.23 2.43 2.83 V V V V V V V V V V V V V max Unit No. 6526-7/38 LC74731W,74732W OSD Write (See figure 1.) at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V Parameter Symbol tw (sclk) tw (cs) tsu (cs) tsu (sin) th (cs) th (sin) tword twt SCLK CS (the period when CS is high) CS SIN CS SIN The time to write 8 bits of data RAM data write time Conditions Ratings min 200 1 200 200 2 200 4.2 1 typ — — — — — — — — max — — — — — — — — Unit ns µs ns ns µs ns µs µs Minimum input pulse width Data setup time Data hold time One word write time Supplementary Materials tw(cs) CS tsu(cs) tw(sclk) tw(sclk) th(cs) SCLK tsu(sin) th(sin) SIN CS tword twt SCLK 0 1 5 6 7 0 1 4 5 6 7 Figure 1 OSD Serial Data Input Timing No. 6526-8/38 CS SIN SCLK Serial to parallel converter 8-bit latch and command decoder System Block Diagram RST Horizontal character size register Display control register RAM write address counter Vertical character size register Horizontal display position register Vertical display position register Blinking and reverse video control register MUTE OUTMOD CHARA Horizontal size counter Vertical size counter Horizontal dot counter Vertical dot counter BLANK IEOUT Horizontal display position detection Vertical display position detection A0 to A17, OE, CE Decoder LC74731W,74732W SYNC JDG Character control counter Line control counter Synchronous judgment Decoder Blinking and reverse video control circuit Display RAM SEP OUT Font ROM D0 to D7 OSC IN OSC OUT Timing generator Character output dot clock oscillator Shift register Character output control Background control Video output control Sync signal generator SYN IN SEP C Sync separator circuit Composite sync separator control SEP IN VDD1, VDD2 CTRL1 Xtal IN Xtal OUT CVCR CDLR CV IN CV OUT Yout Yin CIN Cout Cbias VSS1, VSS2 No. 6526-9/38 LC74731W,74732W Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. Display Control Commands First byte Command Command identification code 7 COMMAND0 (Write address setup) 1 6 0 5 0 4 0 3 V3 2 V2 Data 1 V1 0 V0 7 0 at2 COMMAND1 (Character write) 1 0 0 1 IR SD2 SD1 SD0 0 C7 COMMAND20 (Vertical display start position) COMMAND21 (Horizontal display start position) COMMAND22 (Character size) COMMAND23 (Character size - in line units) COMMAND3 (Display control) COMMAND4 (Display control) COMMAND50 (Sync signal detection 1) COMMAND51 (Sync signal detection 2) COMMAND52 (Display control) COMMAND53 (Display control) COMMAND60 (Outlining setting) COOMAND61 (Outlining setting - in line units) COMMAND62 (Line spacing) COMMAND63 (Line spacing - in line units) COMMAND70 (Display level) COMMAND71 (Display level - in line units) COMMAND72 (Halftone - in line units) COMMAND73 (RGB control) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 RRM1 RRM0 0 0 0 0 SRM LSZUD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 at1 0 C6 VP6 HP6 0 0 5 0 CB2 0 C5 VP5 HP5 0 4 H4 CB1 C12 C4 VP4 HP4 0 Second byte Data 3 H3 CB0 C11 C3 VP3 HP3 VS1 2 H2 CC2 C10 C2 VP2 HP2 VS0 1 H1 CC1 C9 C1 VP1 HP1 HS1 0 H0 CC0 C8 C0 VP0 HP0 HS0 LSZB5 LSZA4 LSZ93 LSZ82 LSZ71 LSZ60 BLKSEL TSTMOD RAMERS OSCSTP SYSRST LCSOFF XN53S LC CB SN3 FS PH2 SN2 BK PH1 SN1 DSPON NP2 0 0 1 1 0 0 1 1 0 0 1 1 NP1 0 1 0 1 0 1 0 1 0 1 0 1 NP0 DISLIN I/N I/E HLFINT BCL1 BCL0 RN2 O CINSEL PH0 SN0 RN1 RN0 MUT1 MUT0 EVEBSS LSPSS RNE0 SJN3 SJN2 SJN1 SJC1 SJC0 CINCTL VNPSEL VSPSEL MSKERS MSKSEL EGLSEL RSLG1 RSLG0 0 CTL3 SPOSEL PALAL4 IHSEL VSSEL HSSEL 0 0 0 0 0 0 BRM LFCUD GRM LGYUD LRM LCLUD BXBLV1 BXBLV0 BXWLV1 BXWLV0 ATSEL BLK1 BLK0 0 O 0 0 0 0 DASSS LFCB5 LFCA4 LFC93 LFC82 LFC71 LFC60 BXC1 GS1 LGYB5 LGYA4 GS0 LGY93 GY2 LGY82 GY1 LGY71 GY0 LGY60 BKLC1 BKLC0 CHLC1 CHLC0 RSLC1 RSLC0 LCLB5 LCLA4 LCL93 LCL82 LCL71 LCL60 LHTDAT LHTUD LHTB5 LHTA4 LHT93 LHT82 LHT71 LHT60 0 0 GBSEL OUTSEL HSPSW XONSS BLK01 BLK00 Note that when the display character data write command (COMMAND1) is written, tthese ICs lock into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the these ICs are set to the COMMAND0 (display memory write address setup mode) state. No. 6526-10/38 LC74731W,74732W COMMAND0 (Display memory write address setup command) • First byte DA0 to 7 7 6 5 4 3 Register — — — — V3 Content State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory line address (0 to B (hexadecimal)) Function Command 0 identification code Display memory write address setup Notes 2 V2 1 V1 0 V0 • Second byte DA0 to 7 7 6 5 4 Register — — — H4 Content State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory line address (0 to 17 (hexadecimal)) Function Second byte identification code Notes 3 H3 2 H2 1 H1 0 H0 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-11/38 LC74731W,74732W COMMAND1 (Display character data write setup command) • First byte DA0 to 7 7 6 5 4 3 Register — — — — IR Content State 1 0 0 1 0 1 0 1 0 1 0 1 Internal ROM External ROM White-on-black (convex) display Black-on-white (concave) display Character frame start: off Character frame start: on Character frame stop: off Character frame stop: on Character frame specification Switching between internal and external ROM Command 1 identification code Display character data write settings Note that when this command is input, the LC74731W/74732W lock into the display character data write mode until the CS pin is set high. Function Notes 2 SD2 1 SD1 0 SD0 • Second byte (1) DA0 to 7 Register Content State 0 7 at2 1 Character attribute 2: off (Character frame upper side: off) Character attribute 2: on (Character frame upper side: on) Character attribute 1: off (Character frame lower side: off) Character attribute 1: on (Character frame lower side: on) cb2 (B 0 0 0 0 3 cb0 1 1 1 1 1 2 cc2 0 1 0 1 0 cc2 (B 0 0 0 0 0 cc0 1 1 1 1 1 cb1 G 0 0 1 1 0 0 1 1 cc1 G 0 0 1 1 0 0 1 1 cb0 R) 0 1 0 1 0 1 0 1 cc0 R) 0 1 0 1 0 1 0 1 Black Red Green Yellow Blue Magenta Cyan White Black Red Green Yellow Blue Magenta Cyan Transparent Character color Character color specification Character background color Character background color specification Reverse video specification Selected by COM60 second byte and ATSEL. Function Blinking specification Selected by COM60 second byte and ATSEL. Notes 0 6 at1 1 0 1 0 1 0 5 cb2 4 cb1 1 cc1 No. 6526-12/38 LC74731W,74732W • Second byte (2) DA0 to 7 7 6 5 4 Register — — — c12 Content State 0 0 0 0 1 0 1 0 1 0 1 0 1 Character code (00xx to 1Fxx (hexadecimal)) External ROM upper address Function Notes 3 c11 2 c10 1 c09 0 c08 Note that all registers are set to 0 when these ICs are reset by the RST pin. • Second byte (3) DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Character code (00 to FF (hexadecimal)) FE (hexadecimal): Space character FF (hexadecimal): Transparent space character Notes External ROM lower address Internal ROM address 7 c07 6 c06 5 c05 4 c04 3 c03 2 c02 1 c01 0 c00 Note that all registers are set to 0 when these ICs are reset by the RST pin. Continuous mode (cleared by setting CS high) operates as follows according to IR. When internal ROM is specified: 1-1 1-2-1 1-2-1 1-2-2 1-2-2 1-2-3 1-2-3 1-2-3 1-2-2 1-2-3 1-2-3 1-2-3 1-2-2 1-2-3 When external ROM is specified: 1-1 No. 6526-13/38 LC74731W,74732W COMMAND20 (Vertical display start position setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 Register — — — — — — RRM1 Content State 1 0 1 0 0 0 0 1 0 0 RRM0 1 RRM1 0 0 1 1 RRM0 0 1 0 1 Initial value (depends on IR) 1-2-1 1-2-2 1-2-3 1-2-2 1-2-3 Fixed 1-2-3 Fixed Fixed Continuous RAM write mode specification Extended command 0 identification code Function Command 2 identification code Vertical display position and vertical direction character size settings Notes • Second byte DA0 to 7 7 6 Register — VP6 (MSB) VP5 Content State 0 0 1 0 1 0 1 0 1 0 VSYNC 1 0 1 0 1 VS Function Second byte identification bit If VS is the vertical display start position then: VS = α + H × ( 2 ∑ 2 n V P n ) n=0 6 Notes The vertical display start position is set by the 7 bits VP0 to VP6. The weight of bit 1 is 2H. 5 H: the horizontal synchronization pulse period α = 20H (525H systems) = 25H (625H systems) HSYNC 4 VP4 3 VP3 2 VP2 1 VP1 VP0 (LSB) HS Character display area 0 No. 6526-14/38 LC74731W,74732W COMMAND21 (Horizontal display start position setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 0 1 0 0 1 0 0 Extended command 1 identification code Function Command 2 identification code Horizontal display position setup and horizontal direction character size settings Notes • Second byte DA0 to 7 7 6 Register — HP6 (MSB) HP5 Content State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. HS =Tc × ( 2 ∑ 2 n H P n ) n=0 6 Function Second byte identification bit If HS is the horizontal start position then: Notes The horizontal display start position is set by the 7 bits HP0 to HP6. The weight of bit 1 is 2Tc. 5 4 HP4 3 HP3 2 HP2 1 HP1 HP0 (LSB) 0 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-15/38 LC74731W,74732W COMMAND22 (Character size setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — SRM Content State 1 0 1 0 1 0 0 0 1 Continuous mode: off Continuous mode: on Character size continuous mode specification Extended command 2 identification code Function Command 2 identification code Horizontal display position setup and horizontal direction character size settings Notes • Second byte DA0 to 7 7 6 5 4 3 Register — — — — VS1 Content State 0 0 0 0 0 1 0 2 VS0 1 0 1 0 0 HS0 1 VS1 0 0 1 1 HS1 0 0 1 1 VS0 0 1 0 1 HS0 0 1 0 1 Character size 1× 2× 3× 4× Character size 1× 2× 3× 4× Horizontal direction character size, in line units Vertical direction character size, in line units Function Second byte identification bit Notes 1 HS1 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-16/38 LC74731W,74732W COMMAND23 (Character size and line setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — LSZUD Content State 1 0 1 0 1 1 0 0 1 Lower lines: 0 to 5 (hexadecimal) Upper lines: 6 to B (hexadecimal) Upper/lower line specification Extended command 3 identification code Function Command 2 identification code Horizontal display position setup and horizontal direction character size settings Notes • Second byte DA0 to 7 7 6 5 Register — — LSZB5 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Line 6 (line 12) specification: off Line 6 (line 12) specification: on Line 5 (line 11) specification: off Line 5 (line 11) specification: on Line 4 (line 10) specification: off Line 4 (line 10) specification: on Line 3 (line 9) specification: off Line 3 (line 9) specification: on Line 2 (line 8) specification: off Line 2 (line 8) specification: on Line 1 (line 7) specification: off Line 1 (line 7) specification: on The line shown in parentheses is specified when LSZUD is 1. Function Second byte identification bit Notes 4 LSZA4 3 LSZ93 2 LSZ82 1 LSZ71 0 LSZ60 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-17/38 LC74731W,74732W COMMAND3 (Display control setup command) • First byte DA0 to 7 7 6 5 4 3 Register — — — — TSTMOD Content State 1 0 1 1 0 1 0 1 0 1 0 1 Reset all registers. This turns the display off. Erase display RAM (sets the data to FF (hexadecimal)) Do not stop the crystal and LC oscillator circuits. Stop the crystal and LC oscillator circuits. Normal operating mode Test mode The RAM erase operation takes about 500 µs. (It must be executed in the DSPOFF state.) This setting is valid in external synchronization mode when character display is off. The reset occurs when the CS pin is low, and is cleared when CS is set high. This bit must always be 0. Function Command 3 identification code Display character data write settings Notes 2 RAMERS 1 OSCSTP 0 SYSRST • Second byte DA0 to 7 7 6 Register — LCSOFF Content State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Second byte identification bit Normal operation LC oscillator STOP: Disabled Normal Switching Character display area Video display area The LC oscillator is used as the dot clock. The crystal oscillator is used as the dot clock. Crystal oscillator frequency: 2 fsc Crystal oscillator frequency: 4 fsc Blinking period: 0.5 s Blinking period: 1 s Character display: off Character display: on Switches the blinking period. Specifies the character size that fills the whole character area. Selects the dot clock used for character display in the horizontal direction. Sets the crystal oscillator frequency. Switches the crystal oscillator capability Switches the LC oscillator STOP control Notes 5 XN53S 4 BLKSEL 3 LC 2 FS 1 BK 0 DSPON Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-18/38 LC74731W,74732W COMMAND4 (Display control setup command) • First byte DA0 to 7 7 6 5 4 3 Register — — — — NP2 Content State 1 1 0 0 0 1 0 1 0 1 NP0 1 NP2 0 0 0 0 1 1 0 I/N 0 1 Interlaced Noninterlaced NP1 0 0 1 1 0 0 NP0 0 1 0 1 0 1 Signal format NTSC PAL-M PAL PAL-N NTSC4.43 PAL60 Switches between interlaced and noninterlaced Switches the signal format Function Command 4 identification code Display control settings Notes 2 NP1 • Second byte DA0 to 7 7 6 Register — HLFINT Content State 0 0 1 0 1 0 4 BCL0 1 0 1 0 1 0 1 0 Function Second byte identification bit Normal mode Semi-internal synchronization mode BCL1 0 0 1 1 BCL0 0 1 0 1 Background color shown No background color (RSL1) No background color (CBH) No background color (RSH1) Only valid when BCL is high. Only valid in internal synchronization mode. Notes 5 BCL1 3 CB The color burst signal is output. Color burst signal output is stopped. PH2 B 0 0 0 0 PH1 G 0 0 1 1 0 0 1 1 PH0 R 0 1 0 1 0 1 0 1 Black (RSLx) Red Green Yellow Blue Magenta Cyan White (RSHx) Background color 2 PH2 Background color specification 1 PH1 0 PH0 1 1 1 1 1 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-19/38 LC74731W,74732W COMMAND50 (Sync signal detection 1 setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 Register — — — — — — DISLIN Content State 1 1 0 1 0 0 0 1 0 1 12 lines 10 lines External synchronization Internal synchronization Switches between internal and external synchronization Switches the number of lines displayed. Extended command 0 identification code Function Command 5 identification code Sync signal control settings Notes 0 I/E • Second byte DA0 to 7 7 6 Register — RN2 Content State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SN3 SN2 SN1 SN0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 Number of times HSYNC detected Not detected 32 times 64 times 128 times 256 times Function Second byte identification bit RN2 0 0 0 1 RN1 0 0 1 0 RN0 0 1 0 0 Number of times HSYNC detected 0 times (32 times) 4 times (64 times) 8 times (128 times) 16 times (256 times) External sync signal detection control Recognition of the transition from the no signal state to the signal present state. Sets the sampling period in which the sync signal can be detected continuously in the horizontal sync signal period (1H). The values in parentheses apply when RNE0 (COM51) is 1. External sync signal detection control Recognition of the transition from the signal present state to the no signal state. Sets the sampling period time in which the sync signal cannot be detected continuously in the horizontal sync signal period (1H). Notes 5 RN1 4 RN0 3 SN3 2 SN2 1 SN1 0 SN0 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-20/38 LC74731W,74732W COMMAND51 (Sync signal detection 2 setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 Register — — — — — — MUT1 Content State 1 1 0 1 0 1 0 1 0 1 MUT1 MUT0 0 0 1 0 1 0 Output CSYNC PE A0-17 “Z” Video signal output muting function selection Valid when the MUTE pin is low. Extended command 1 identification code Function Command 5 identification code Display control settings Notes 0 MUT0 • Second byte DA0 to 7 7 6 Register — — Content State 0 0 0 5 RNE0 1 4 SJNS3 0 1 0 1 0 Sync signal no signal to signal present discrimination - Normal values Sync signal no signal to signal present discrimination - Values shown in parentheses SJNS3 SJNS2 SJNS1 0 0 0 0 1 2 SJNS1 1 1 1 1 1 SJCS1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PAL 677 ns (1/3) 903 ns (1/4) 450 ns (1/2) Times None 4 8 16 32 64 128 256 NTSC 558 ns (1/2) 838 ns (1/3) 1117 ns (1/4) Synchronization discrimination Selects the clock used to delimit the HSYNI signal. Changes the judgment criterion values for sync signal recognition for the no signal to signal present transition. (COM50) Function Second byte identification bit Notes Noise ignoring circuit setting for sync signal recognition for the no signal to signal present transition If more than the number of horizontal signals shown at the left are input during a 1H period, the circuit recognizes a no signal state. 3 SJNS2 SJCS1 SJCS0 0 0 1 0 1 0 0 SJCS0 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-21/38 LC74731W,74732W COMMAND52 (Display control setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 Register — — — — — — EVEBSS Content State 1 1 0 1 1 0 0 1 0 1 Normal Always high Normal HT12 “on” HT34 “off” LCSTOP control signal Switches the ENBVI signal Extended command 2 identification code Function Command 5 identification code Display control settings Notes 0 LSPSS • Second byte DA0 to 7 7 6 Register — CINSEL Content State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Second byte identification bit Blank area (the logical OR of the character and outlining signals) Video signal display area CVCR: off CVCR: on V signal falling edges detected V signal rising edges detected VSEP: About 8.9 µs (NTSC) VSEP: About 17.8 µs (NTSC) Mask enabled Mask disabled 3H (NTSC) 20H (NTSC) Outlining level 0 only (VBK0) Two-stage outlining level (VBK0, VBK1) Switches the outlining level (Only valid when BLK0 is 0 and BLK1 is 1.) Switches the VSYNC mask Clears the HSYNC and VSYNC masks Switches the V signal acquisition polarity when external mode/internal V separation is used Switches the internal vertical separation time CVCR on/off switching Switches the CVCR on state signal Notes 5 CINCTL 4 VNPSEL 3 VSPSEL 2 MSKERS 1 MSKSEL 0 EGL Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-22/38 LC74731W,74732W COMMAND53 (Display control setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 Register — — — — — — RSLG1 Content State 1 1 0 1 1 1 0 1 0 1 RSLG1 RSLG0 0 0 1 0 1 0 NO1 NO2 NO3 RS1 RS2 RS3 Switches the screen background color level Extended command 3 identification code Function Command 5 identification code Display control settings Notes 0 RDLG0 • Second byte DA0 to 7 7 6 5 Register — — CTL3 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Internal vertical separation circuit External input CSYNC (sync separator output) Halftone output Normal Always use 4 fsc timing (PAL) SYNin pin input signal SEPin pin input signal Negative polarity Positive polarity Negative polarity Positive polarity Switches the SYNin input polarity (Invalid for CVIDEO input) Switches the internal vertical separation input signal Switches the SEPin input polarity Switches the SEPout pin output Switches the VSYNC signal input Function Second byte identification bit Notes 4 SP0SEL 3 PALAL4 2 IHSEL 1 VSSEL 0 HSSEL Note that all registers are set to 0 when these ICs are reset by the RST pin. SYnin: CVIDEO (Built-in sync separator circuit) SEPin: None (internal vertical separation) or :VSYNC SYNin: HD SEPin: CSYNC (internal vertical separation) SYNin: HSYNC SEPin: VSYNC SYNin: CSYNC (internal vertical separation) SEPin: None No. 6526-23/38 LC74731W,74732W COMMAND60 (Outlining control setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — BRM Content State 1 1 1 0 0 0 0 0 1 Normal mode Continuous mode Specifies continuous mode Extended command 0 identification code Function Command 6 identification code Display control settings Notes • Second byte DA0 to 7 7 6 Register — BXBLV1 Content State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 BLK0 1 Function Second byte identification bit BXBLV1 BXBLV0 0 0 1 0 1 0 NO1 NO2 NO3 BK1 BK2 BK3 Character frame - white level specification NO1 NO2 NO3 CHA1 CHA2 CHA3 Setup for the at1 and at2 function In line units Outlining mode specification In line units In line units Character frame - black level specification In line units Notes 5 BXBLV0 4 BXWLV1 BXWLV1 BXWLV0 0 0 1 0 1 0 3 BXWLV0 2 ATSEL Reverse video, blinking Character frame specified BLK1 0 0 1 1 BLK0 0 1 0 1 Mode Normal Character size Outlining size Full area size 1 BLK1 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-24/38 LC74731W,74732W COMMAND61 (Outlining control and line specification setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — LFCUD Content State 1 1 1 0 0 1 0 0 1 Lower lines (0 to 5 (hexadecimal)) Upper lines (6 to B (hexadecimal)) Outlining control line specification Extended command 1 identification code Function Command 6 identification code Display control settings Notes • Second byte DA0 to 7 7 6 5 Register — — LFCB5 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Line 6 (line 12) setting: off Line 6 (line 12) setting: on Line 5 (line 11) setting: off Line 5 (line 11) setting: on Line 4 (line 10) setting: off Line 4 (line 10) setting: on Line 3 (line 9) setting: off Line 3 (line 9) setting: on Line 2 (line 8) setting: off Line 2 (line 8) setting: on Line 1 (line 7) setting: off Line 1 (line 7) setting: on Outlining line setting The values in parentheses apply when LFCUD is 1. Function Second byte identification bit Notes 4 LFCA4 3 LFC93 2 LFC82 1 LFC71 0 LFC60 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-25/38 LC74731W,74732W COMMAND62 (Line spacing control setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — GRM Content State 1 1 1 0 1 0 0 0 1 Normal mode Continuous mode Continuous mode specification Extended command 2 identification code Function Command 6 identification code Display control settings Notes • Second byte DA0 to 7 7 6 5 Register — — BXC1 Content State 0 0 0 1 0 1 0 3 GS0 1 0 1 0 1 0 Display outside the character area Forces display within the character area GS1 0 0 1 1 GY2 0 0 0 0 1 0 GY0 1 1 1 1 GS0 0 1 0 1 GY1 0 0 1 1 0 0 1 1 Mode Normal (character background color) Full area and reverse invalid (other than ±1) Transparent 1 (all) Transparent 2 (other than ±1) GY0 0 1 0 1 0 1 0 1 Line spacing 0 ±1 2 3 4 5 6 7 In line units Box left/right display specification In line units In line units Function Second byte identification bit Notes 4 GS1 2 GY2 1 GY1 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-26/38 LC74731W,74732W COMMAND63 (Line spacing control - line specification setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — LGYUD Content State 1 1 1 0 1 1 0 0 1 Lower lines (0 to 5 (hexadecimal)) Upper lines (6 to B (hexadecimal)) Line spacing control - line specification Extended command 3 identification code Function Command 6 identification code Display control settings Notes • Second byte DA0 to 7 7 6 5 Register — — LGYB5 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Line 6 (line 12) setting: off Line 6 (line 12) setting: on Line 5 (line 11) setting: off Line 5 (line 11) setting: on Line 4 (line 10) setting: off Line 4 (line 10) setting: on Line 3 (line 9) setting: off Line 3 (line 9) setting: on Line 2 (line 8) setting: off Line 2 (line 8) setting: on Line 1 (line 7) setting: off Line 1 (line 7) setting: on Line setting for line spacing control The values in parentheses apply when LGYUD is 1. Function Second byte identification bit Notes 4 LGYA4 3 LGY93 2 LGY82 1 LGY71 0 LGY60 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-27/38 LC74731W,74732W COMMAND70 (Display control setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — LRM Content State 1 1 1 1 0 0 0 0 1 Normal mode Continuous mode Continuous mode specification Extended command 0 identification code Function Command 7 identification code Display control settings Notes • Second byte DA0 to 7 7 6 5 Register — — BKLC1 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 BKLC1 0 0 1 CHLC1 0 0 1 RSLC1 0 0 1 BKLC0 0 1 0 CHLC0 0 1 0 RSLC0 0 1 0 NO1 NO2 NO3 RS1 RS2 RS3 NO1 NO2 NO3 CHA1 CHA2 CHA3 Character color and character background color: color level specification In line units NO1 NO2 NO3 BK1 BK2 BK3 Character color and character background color: white level specification In line units Character color and character background color: black level specification In line units Function Second byte identification bit Notes 4 BKLC0 3 CHLC1 2 CHLC0 1 RSLC2 0 RSLC1 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-28/38 LC74731W,74732W COMMAND71 (Display levels - line specification setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — LCLUD Content State 1 1 1 1 0 1 0 0 1 Lower lines (0 to 5 (hexadecimal)) Upper lines (6 to B (hexadecimal)) Display levels - line specification Extended command 1 identification code Function Command 7 identification code Display control settings Notes • Second byte DA0 to 7 7 6 5 Register — — LCLB5 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Line 6 (line 12) setting: off Line 6 (line 12) setting: on Line 5 (line 11) setting: off Line 5 (line 11) setting: on Line 4 (line 10) setting: off Line 4 (line 10) setting: on Line 3 (line 9) setting: off Line 3 (line 9) setting: on Line 2 (line 8) setting: off Line 2 (line 8) setting: on Line 1 (line 7) setting: off Line 1 (line 7) setting: on Display level line setting The values in parentheses apply when LCLUD is 1. Function Second byte identification bit Notes 4 LCLA4 3 LCL93 2 LCL82 1 LCL71 0 LCL60 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-29/38 LC74731W,74732W COMMAND72 (Halftone - line specification setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 Register — — — — — — LHTDAT Content State 1 1 1 1 1 0 0 1 0 1 Halftone: off Halftone: on Lower lines (0 to 5 (hexadecimal)) Upper lines (6 to B (hexadecimal)) Halftone line specification Halftone control Extended command 2 identification code Function Command 7 identification code Display control setup Notes 0 LHTUD • Second byte DA0 to 7 7 6 5 Register — — LHTB5 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Line 6 (line 12) setting: off Line 6 (line 12) setting: on Line 5 (line 11) setting: off Line 5 (line 11) setting: on Line 4 (line 10) setting: off Line 4 (line 10) setting: on Line 3 (line 9) setting: off Line 3 (line 9) setting: on Line 2 (line 8) setting: off Line 2 (line 8) setting: on Line 1 (line 7) setting: off Line 1 (line 7) setting: on Halftone line setting The values in parentheses apply when LHTUD is 1. Function Second byte identification bit Notes 4 LHTA4 3 LHT93 2 LHT82 1 LHT71 0 LHT60 Note that all registers are set to 0 when these ICs are reset by the RST pin. No. 6526-30/38 LC74731W,74732W COMMAND73 (RGB control setup command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 1 1 1 1 0 0 Extended command 3 identification code Function Command 7 identification code Display control setup Notes • Second byte DA0 to 7 7 6 Register — DASSS Content State 0 0 1 0 5 GBSEL 1 0 1 0 1 0 1 0 1 0 0 BLK01 1 RGB output switching Internal Sync separator used Internal Sync separator not used Operation depends on the CTRL1 pin Feedback resistor disconnected BLK01 0 0 1 1 BLK00 0 1 0 1 CHA + BK + CHAB CHA +BK only CHA only BK only Function Second byte identification bit Normal CLKD = CLKX Background color: off Background color: on Switches the XTALIN amplifier input Only valid when RGB output is specified. Switches the background color in RGB output mode The background color is specified by COM4 second byte. Switches the P9 to P12 outputs The logical OR with the OUTMOD input. Switches the SYNin input The logical OR with the OUTMOD input. Enables or disables the feedback resistor for the XTALIN clock. Switches the BLKout output Box is always on. Always on when GBSEL = 1. Notes 4 OUTSEL 3 HSPSW 2 XONSS 1 BLK02 No. 6526-31/38 LC74731W,74732W Display Screen Structure The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is less than the 288 maximum when enlarged characters are displayed. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses) 24 Characters 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 00 01 02 03 04 05 12 Rows 06 07 08 09 10 11 6 7 8 9 A B HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 HEX 0 1 2 3 4 5 No. 6526-32/38 LC74731W,74732W Composite Video Signal Output Levels (internally generated levels) • CVOUT Output Level Waveform (VDD2 = 5.00 V) x y z [V] 2.80 3.00 3.30 2.65 2.85 3.15 VCHA1 2.37 2.57 2.87 VRSH3 VRSH2 VCHA2 VCHA3 2.08 2.28 2.58 2.01 2.21 2.51 VBK3 VRSH1 VBK2 1.67 1.87 2.17 1.52 1.72 2.02 1.50 1.70 2.00 1.37 1.57 1.87 1.23 1.43 1.73 1.07 1.27 1.67 VCBL VPD VRSL2 VRSL3 VCBH VBK1 VRSL1 0.80 1.00 1.40 VSN 1H Output level VCHA1: Character 1 VRSH2: Background color 2: high VCHA3: Character 3 VBK3: Outlining: 3 VRSH1: Background color 1: high VBK2: Outlining: 2 VCBH: Color burst: high VRSL1: Background color 1: low VBK1: Outlining: 1 VPD: Pedestal VRSL2: Background color 2: low VCBL: Color burst: low VSN: Sync BCOL01: RSL1 BCOL0: CBH BCOL11:RSH1 Output voltage (1) [V] 2.65 2.37 2.23 2.08 2.01 1.80 1.67 1.52 1.50 1.37 1.23 1.07 0.80 Output voltage (2) [V] 2.85 2.57 2.43 2.28 2.21 2.00 1.87 1.72 1.70 1.57 1.43 1.27 1.00 Output voltage (3) [V] 3.25 2.97 2.83 2.68 2.61 2.40 2.27 2.12 2.10 1.97 1.83 1.67 1.40 No. 6526-33/38 LC74731W,74732W YOUT Output Level Waveform (VDD2 = 5.00 V) x y z [V] 2.80 3.00 3.30 2.65 2.85 3.15 YCHA2 YCHA3 YBK3 YRS3 YCHA1 2.08 2.28 2.58 YRS2 YBK2 YRS1 1.50 1.70 2.00 YCB 1.37 1.57 1.87 YPD YBK1 0.80 1.00 1.40 YSN 1H Output level YCHA1: Character 1 YCHA2: Character 2 YCHA3: Character 3 YBK3: Outlining: 3 YRS3: Background color 3 YRS2: Background color 2 YRS1: Background color 1 YBK1: Outlining: 1 YCB: Color burst YPD: Pedestal YSN: Sync Output voltage (1) [V] 2.65 2.37 2.23 2.08 2.02 1.80 1.76 1.50 1.37 1.37 0.80 Output voltage (2) [V] 2.85 2.57 2.43 2.28 2.22 2.00 1.96 1.70 1.57 1.57 1.00 Output voltage (3) [V] 3.25 2.97 2.83 2.68 2.62 2.40 2.36 2.10 1.97 1.97 1.40 BCOL01: YBK1 BCOL10: YRS1 BCOL11: YRS3 No. 6526-34/38 LC74731W,74732W • COUT Output Level Waveform (VDD2 = 5.00 V) CRSH2 CCBH CRSH1 2.50 V CBIAS CRSL1 CCBL CRSL3 CRSL2 Output level CRSH2: Background color 2: high CCBH: Color burst: high CRSH1: Background color 1: low CBIAS: Bias CRSL1: Background color 2: low CCBL: Color burst: low CRSL2: Background color 2: low Output voltage (1) [V] 3.07 2.80 2.74 2.50 2.25 2.20 1.93 Output voltage (2) [V] 3.07 2.80 2.74 2.50 2.25 2.20 1.93 Output voltage (3) [V] 3.07 2.80 2.74 2.50 2.25 2.20 1.93 BCOL01, 10, 11: CBIAS No. 6526-35/38 LC74731W,74732W Sample Application Circuit • Cvideo, Y/C 64 D1 D0 From external ROM A3 A4 OE A1 CE D2 D3 D5 D6 D7 A0 A2 49 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VDD1 RST SEPIN SEPOUT CVOUT CVIN HFTIN To external ROM SYNIN 32 1 D4 48 VSS1 XtalIN XtalOUT CTRL1 OSCIN OSCOUT MUTE CDLR SYNCJDG/ROUT CHARA/GOUT BLANK/BOUT IBOUT/BLKOUT OUTMOD CS SIN SCLK CBIAS COUT YOUT CVCR 16 VDD2 VSS2 CIN 33 YIN NC 17 +5 V Buffer Clamp NC Buffer Clamp NC Buffer Clamp NC No. 6526-36/38 LC74731W,74732W • RGB 64 D0 D1 From external ROM OE CE D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 49 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VDD1 RST SEPIN SEPOUT CVOUT To external ROM SYNIN 1 48 VSS1 XtalIN XtalOUT CTRL1 OSCIN OSCOUT MUTE CDLR SYNCJDG/ROUT CHARA/GOUT BLANK/BOUT IBOUT/BLKOUT OUTMOD CS SIN SCLK CBIAS COUT YOUT VDD2 CVCR CVIN 16 VSS2 CIN YIN NC NC NC HFTIN 33 vsync 32 17 +5 V NC hsync No. 6526-37/38 LC74731W,74732W Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 2000. Specifications and information herein are subject to change without notice. PS No. 6526-38/38