LC74735NW

Ordering number : ENN7545 CMOS IC LC74735NW On-Screen Display Controller Overview The LC74735NW is an on-screen display CMOS IC that displays characters and patterns on a TV screen. For QVGA display, the LC74735NW supports the use of both a 12 × 18 dot character font and a 12 × 18 dot graphics font with 16 colors with a total of 512 characters and glyphs. For WVGA display, the LC74735NW supports the use of both a 24 × 32 dot character font and a 12 × 16 dot graphics font with 16 colors with a total of 512 characters and glyphs. The LC74735NW can also implement extremely varied displays by the use of an external ROM. The LC74735NW supports both QVGA (480 × 234) and WVGA (800 × 480). • • Features • Screen structure — Main: QVGA mode: 40 characters × 13 lines (up to 520 characters) on a QVGA panel WVGA mode: 33 characters × 15 lines (up to 495 characters) on a WVGA panel — Wallpaper display screen: Permanent repetition of a 2 × 2 (horizontal × vertical) character pattern • Character structure — QVGA mode: 12 dots (horizontal) × 18 dots (vertical): Character display 12 dots (horizontal) × 18 dots (vertical): Graphic glyph display — WVGA mode: 24 dots (horizontal) × 32 dots (vertical): Character display • • 12 dots (horizontal) × 16 dots (vertical): Graphic glyph display (1 pixel: 2 × 2 dots) — Character display clock: About 9 MHz — QVGA with an LC oscillator 33.2 MHz (maximum: 40 MHz) WVGA with an external clock signal input *: The ROM image is known when QVGA or WVGA mode is specified. Number of characters: 512 (internal) Up to 2048 characters when an external 16-bit 4M ROM is used. Character sizes: Four horizontal sizes (1×, 2×, 3×, and 4×) Four vertical sizes (1×, 2×, 3×, and 4×) (The character size is specified in line units.) Display start positions: 512 positions in the horizontal direction and 256 positions in the vertical direction. QVGA mode WVGA mode Setting units: Horizontal: 1 dot 2 dots (In screen units) Vertical: 1 dot 2 dots (In screen units) Display functions — Blinking specification (in character units) Period: 1/64, 1/32, and 1/16 of the vertical sync signal (in screen units) Duty: Fixed at 50% — Box (raised or recessed) display Raised/recessed specification (in character units) Left: Off/on specification (in character units) Right: Off/on specification (in character units) Top: Off/on specification (in character units) Bottom: Off/on specification (in character units) Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O1003TN (OT) No. 7545-1/52 LC74735NW — Border specification (in line units): Only valid with glyphs from the character font. Color specification Character — Character color (in character units): 1 of 16 colors can be specified. — Character background color (in character units): 1 of 16 colors can be specified. — Border color (in line units): 1 of 16 colors can be specified. Graphic — 16 types can be specified by ROM data Box color (line units) : 1/16 colors Background color (screen units) : 1/16 colors Color table (palette) — Sixteen colors can be selected from a set of 512 colors (One of which is specified to be transparent.) — Number of color tables: 2. This allows up to 32 colors to be displayed at the same time. Wallpaper screen (Graphics glyphs only) Wallpaper display: Repeated display under the main screen (2 characters horizontally by 2 characters vertically). Sprite character display: Displayed above the main screen (2 characters horizontally by 2 characters vertically) Output — QVGA Analog RGB output BLK (OSD display period signal) — WVGA Digital RGB output (3 bits per color) BLK (OSD display period signal) Package: SQFP80 Voltage: 3.3 V Package Dimensions unit: mm 3220-SQFP80 [LC74735NW] 14.0 12.0 1.25 60 61 1.25 0.5 1.25 41 40 0.135 • • • • • 14.0 12.0 1.25 0.5 80 1 0.2 20 21 1.6max 1.4 0.1 0.5 0.5 • SANYO: SQFP80 • • • No. 7545-2/52 LC74735NW Pin Assignments VDD3 VDD3 VSS3 VSS3 A10 A11 A12 A13 A14 62 80 VSS1 OSCin OSCout CTRL1 SCLK SIN CS VDD1 VSYNC VBLK HSYNC HBLK TEST1 TEST2 RST VSS1 VDD1 CLKOUT VSS1 VDD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 61 60 A16 59 A17 58 CE 57 OE 56 VDD3 55 VSS3 54 D0 53 D1 52 D2 51 D3 50 D4 49 D5 48 D6 47 D7 46 VDD1 45 VSS1 44 D8 43 D9 42 D10 41 D11 21 RD2 22 RD1 23 RD0 24 GD2 25 GD1 26 GD0 27 BD2 28 BD1 29 BD0 30 BLK 31 VSS1 32 VDD2 33 OUTR 34 ROUT 35 GOUT 36 BOUT 37 CCOMP 38 CVREF 39 RREF A15 40 VSS2 Top view A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 No. 7545-3/52 LC74735NW Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol VSS1 OSCin OSCout CTRL1 SCLK SIN CS VDD1 VSYNC VBLK HSYNC HBLK TEST1 TEST2 RST VSS1 VDD1 CLKOUT VSS1 VDD1 RD2 RD1 RD0 GD2 GD1 GD0 BD2 BD1 BD0 BLK VSS1 VDD2 OUTR Rout Gout Bout CCOMP CVREF RREF VSS2 Ground LC oscillator OSCin oscillator input control Clock input Data input Enable input Power supply (+3.3 V) Vertical sync signal input Vertical blanking signal input Horizontal sync signal input Horizontal blanking signal input Test mode control 1 Test mode control 2 Reset input Ground Power supply (+3.3 V) Clock output Ground Power supply (+3.3 V) Rout output: bit 2 Rout output: bit 1 Rout output: bit 0 Gout output: bit 2 Gout output: bit 1 Gout output: bit 0 Bout output: bit 2 Bout output: bit 1 Bout output: bit 0 Blanking signal output Ground Power supply (+3.3 V) Outr output: analog Rout output: analog Gout output: analog Bout output: analog Bout output This is a 3-bit digital output with values from 000 to 111. This signal indicates the OSD display period. Connect a ground to this pin. (Digital system ground) Power supply: (+3.3 V: D/A converter) Output. Connect a resistor Ro (68 Ω) to this pin. D/A converter (3 bits) output. Connect a resistor Ro to this pin. D/A converter (3 bits) output. Connect a resistor Ro to this pin. D/A converter (3 bits) output. Connect a resistor Ro to this pin. Gout output This is a 3-bit digital output with values from 000 to 111. Rout output This is a 3-bit digital output with values from 000 to 111. Type Functional description Connect a ground to this pin. (Digital system ground) Connect to the character output dot clock generator oscillator coil and capacitor. May also be used for external clock input. Switches between external clock input mode and LC oscillator mode. Low: LC oscillator, high: external clock input MORE+ Clock input for the serial data input system MORE+ (This input has hysteresis characteristics.) Serial data input MORE+ (This input has hysteresis characteristics.) Enable input for the serial data input system. Serial data input is enabled when this pin is set low. MORE+ (This input has hysteresis characteristics.) Digital system power supply: +3.3 V Vertical sync signal input MORE+ (This input has hysteresis characteristics.) Vertical blanking signal input MORE+ (This input has hysteresis characteristics.) Horizontal sync signal input MORE+ (This input has hysteresis characteristics.) Horizontal blanking signal input MORE+ (This input has hysteresis characteristics.) Test mode control 1 Low: normal operation, high: test mode MORE+ Test mode control 2 Low: normal operation, high: test mode (scan mode) MORE+ System reset input MORE+ (This input has hysteresis characteristics.) Connect a ground to this pin. (Digital system ground) Power supply: (+3.3 V: Digital system) Clock output Connect a ground to this pin. (Digital system ground) Power supply: (+3.3 V: Digital system) Phase correction capacitor connection Capacitor connection: 1.5 µF Reference voltage output Reference resistor connection Ground Capacitor connection: 0.1 µF Connect a reference register to this pin. Connect a ground to this pin. (D/A converter ground) Continued on next page. No. 7545-4/52 LC74735NW Continued from preceding page. Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol D11 D10 D9 D8 VSS1 VDD1 D7 D6 D5 D4 D3 D2 D1 D0 VSS3 VDD3 OE CE A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 VSS3 VDD3 A7 A6 A5 A4 A3 A2 A1 A0 VSS3 VDD3 Type Data input 11 Data input 10 Data input 9 Data input 8 Ground Power supply (+3.3 V) Data input 7 Data input 6 Data input 5 Data input 4 Data input 3 Data input 2 Data input 1 Data input 0 Ground Power supply (+3.3 or +5.5 V) Output enable Chip enable Address output 17 Address output 16 Address output 15 Address output 14 Address output 13 Address output 12 Address output 11 Address output 10 Address output 9 Address output 8 Ground Power supply (+3.3 or +5.5 V) Address output 7 Address output 6 Address output 5 Address output 4 Address output 3 Address output 2 Address output 1 Address output 0 Ground Power supply (+3.3 or +5.5 V) ROM data input 11. MORE+ ROM data input 10. MORE+ ROM data input 9. MORE+ ROM data input 8. MORE+ Connect a ground to this pin. (Digital system ground) Power supply: (+3.3 V: Digital system) ROM data input 7. MORE+ ROM data input 6. MORE+ ROM data input 5. MORE+ ROM data input 4. MORE+ ROM data input 3. MORE+ ROM data input 2. MORE+ ROM data input 1. MORE+ ROM data input 0. MORE+ Connect a ground to this pin. (External ROM output system ground) Power supply (External ROM output system power supply) ROM output enable output. This is an active low output. ROM chip enable output. This is an active low output. ROM address output 17 ROM address output 16 ROM address output 15 ROM address output 14 ROM address output 13 ROM address output 12 ROM address output 11 ROM address output 10 ROM address output 9 ROM address output 8 Connect a ground to this pin. (External ROM output system ground) Power supply (External ROM output system power supply) ROM address output 7 ROM address output 6 ROM address output 5 ROM address output 4 ROM address output 3 ROM address output 2 ROM address output 1 ROM address output 0 Connect a ground to this pin. (External ROM output system ground) Power supply (External ROM output system power supply) Functional description No. 7545-5/52 LC74735NW Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Operating temperature Storage temperature Symbol VDD1 VDD3 VIN VOUT1 VOUT2 Pdmax Topg Tstg VDD1, VDD2 VDD3 All input pins RD2 to 0, GD2 to 0, BD2 to 0, and BLK outputs A0 to A17, CE, OE outputs Conditions Ratings VSS – 0.3 to VSS + 4.6 VSS – 0.3 to VSS + 6.0 VSS – 0.3 to VDD1 + 0.3 VSS – 0.3 to VDD1 + 0.3 VSS – 0.3 to VDD1 + 0.3 230 –30 to +70 –40 to +125 Unit V V V V V mW °C °C Recommended Operating Conditions Parameter Symbol VDD1 VDD3 VIH1 Input high-level voltage VIH2 VIH3 VIL1 Input low-level voltage VIL2 VIL3 Oscillator frequency External clock input FOSC1 FOSC2 VIN1 Vrefda D/A converter (3 bit, 3 ch) When maximum output voltage = 0.7 V Rfda Rfbda Rref VDD1, VDD2 VDD3 CTRL1, TEST1, TEST2 SCLK, SIN, CS, VSYNC, HSYNC, RST D0 to D11 CTRL1, TEST1, TEST2 SCLK, SIN, CS, VSYNC, HSYNC, RST D0 to D11 OSCin and OSCout oscillator pins (LC oscillator) OSCin, VDD1 = 3.3 V VDD1 = 3.3 V, CTRL1 = high Reference voltage Output load resistance ROUT, GOUT, and BOUT Output load resistance OUTR Reference load resistance, RREF Conditions Ratings min 3.0 3.0 0.7 VDD1 0.8 VDD1 0.7 VDD1 VSS – 0.3 VSS – 0.3 VSS – 0.3 — — 0.5 — 120 40 1232 typ 3.3 3.3 — — — — — — 10 33 — 1.1 — — — max 3.6 5.5 5.5 5.5 5.5 0.3 VDD1 0.2 VDD1 0.3 VDD1 — 40 3.3 — 225 75 2310 Unit V V V V V V V V MHz MHz Vp-p V Ω Ω Ω Supply voltage No. 7545-6/52 LC74735NW Electrical Characteristics at Ta = –30 to +70°C, VDD = 3.3 V unless otherwise specified. Parameter Symbol VOH1 Output high-level voltage VOH2 VOH3 VOL1 Output low-level voltage VOL2 VOL3 IIH1 IIH2 IIL1 IIL2 IDD1 Operating current drain IDD2 IDD3 CLK D/A converter Vmax Vmin Pin RD2 to 0, GD2 to 0, BD2 to 0, and BLK outputs A0 to 17, CE, and OE A0 to 17, CE, and OE RD2 to 0, GD2 to 0, BD2 to 0, and BLK outputs A0 to 17, CE, and OE A0 to 17, CE, and OE CTRL1, TEST1, TEST2, SCLK, SIN, CS, VSYNC, HSYNC, RST D0 to 11 CTRL1, TEST1, TEST2, SCLK, SIN, CS, VSYNC, HSYNC D0 to 11 VDD1 VDD2 VDD3 Clock frequency Maximum output voltage Minimum output voltage VDD2 = 3.3 V VDD2 = 3.3 V Conditions VDD1 = 3.0 V IOH1 = –8 mA VDD3 = 3.0 V IOH2 = –8 mA VDD3 = 4.5 V IOH3 = –8 mA VDD1 = 3.0 V IOL1 = 8 mA VDD3 = 3.0 V IOL2 = 8 mA VDD3 = 4.5 V IOL3 = 8 mA VIN = VDD1 VIN = VDD3 VIN = VSS VIN = VSS All outputs open OSCin: 40 MHz D/A on Ratings min VDD1 – 0.8 VDD3 – 0.8 VDD3 – 0.8 — — — typ — — — — — — max — — — 0.4 0.4 0.4 Unit V V V V V V — — –10 –10 — — — — 0.25 — — — — — — — — — — 0 10 10 — — 37 22 20 20 1.5 — µA µA µA µA mA mA mA MHz V V Input current No. 7545-7/52 LC74735NW Timing Characteristics OSD Write (See figure 1.) at Ta = –30 to +70°C, VDD1 = 3.3 ± 0.3 V Parameter Symbol tw (sclk) tw (cs) tsu (cs) tsu (sin) th (cs) th (sin) tword twt SCLK CS (The period CS is high) CS SIN CS SIN The time to write 8 bits of data RAM data write time Conditions Ratings min 200 1 200 200 2 200 4.2 1 typ — — — — — — — — max — — — — — — — — Unit ns µs ns ns µs ns µs µs Minimum input pulse width Data setup time Data hold time One word write time Supplementary Materials tw(cs) CS tsu(cs) tw(sclk) tw(sclk) th(cs) SCLK tsu(sin) th(sin) SIN CS tword twt SCLK 0 1 5 6 7 0 1 4 5 6 7 Figure 1 OSD Serial Data Input Timing No. 7545-8/52 LC74735NW System Block Diagram VDD1, VDD2,VDD3 CS SIN SCLK RST Serial-toparallel converter 16-bits latch + command decoder VSS1,VSS2,VSS3 Horizontal direction control register Address control circuit HSYNC HBLK Horizontal direction counter VRAM Vertical direction control register Address control circuit HSYNC HBLK Vertical direction counter External ROM control circuit OE, CE A0-17 RAM and ROM read and write control FROM D0-11 RD2-0 GD2-0 Output control circuit Character size control BD2-0 BLK OUTR OSCin OSCout Timing generator ROUT D/A GOUT BOUT CTRL1 CCOMP CVREF RREF No. 7545-9/52 LC74735NW Display Control Commands The display control commands have serial input format that consists of 8-bit units transmitted LSB first. A commands consists of a command identification code in the first byte and data in the second and following bytes. Both a first byte and a second byte (16 bits) must be transmitted for each command. Commands 10, 11, and 71 set the IC to continuous write mode. (Continuous write mode is cleared by setting the CS pin high.) Display Control Command Table First byte Command Command identification code 7 Command00 (Write address) Main Command01 (Write address) Sub (Wallpaper) 1 1 1 Command 10 (Character write) Main 6 0 0 0 5 0 0 0 4 0 0 1 3 0 0 0 2 0 1 0 Data 1 V3 0 0 V2 0 7 V1 0 0 6 V0 SV0 0 CB2 0 C6 0 0 0 C6 5 H5 0 at CB1 CT0 C5 0 0 CT0 C5 4 H4 0 BXS CB0 I/E C4 0 0 I/E C4 Second byte Data 3 H3 0 BXL CC3 M/G C3 0 0 M/G C3 2 H2 0 BXR CC2 C10 C2 0 0 C10 C2 1 H1 0 BXU CC1 C9 C1 0 0 C9 C1 0 H0 SH0 BXD CC0 C8 C0 0 0 C8 C0 RM2 RM1(1) (2) CB3 (3) (4) 1 0 0 1 0 1 RM2 RM1(1) (2) (3) (4) 0 C7 0 0 0 C7 Command 11 (Character write) Sub (Wallpaper) Command20 (System control) Command21 (Display control) Command22 (I/O polarity control 1) Command23 (Screen background color) Command24 (I/O polarity control 2) Command25 (Output control) Command30 (Vertical display start position: main) Command31 (Horizontal display start position: main) Command32 (Vertical display start position: sub) Command33 (Horizontal display start position: sub) Command34 (Vertical display start position: screen) Command35 (Horizontal display start position: screen) Command40 (Character size control) Command41 (Character size control: line setting U) Command42 (Character size control: line setting D) Command50 (Box control U) Command51 (Box control D) Command52 (Box control: line setting U) Command53 (Box control: line setting D) Command60 (Border control) Command61 (Border control: line setting U) Command62 (Border control: line setting D) Command70 (Write address) Color table Command71 (Data write) Color table 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 BLK1 0 0 0 0 0 1 0 1 0 1 0 TSTMD2 TSTMD1 Q/W2 Q/W1 SYSRST CTERS SRMERS MRMERS LCSOFF BK1 BK0 SBG1 SBG0 DSPBG DSPGS DSPGM VIP HIP BLD1 BLO0 BLOP BLO1 BLO0 CKP 0 0 BGCT1 BGCT0 BGC3 BGC2 BGC1 BGC0 HBP DSPMD1 DSPMD0 DASEL VBLKON HBLKON CKOP VBP CEHSL TOKSL VIPSL OTM2 OTM1 OTM0 QRM1 QRM0 VPM7 VPM6 VPM5 VPM4 VPM3 VPM2 VPM1 VPM0 HPM8 HPM7 HPM6 HPM5 HPM4 HPM3 HPM2 HPM1 HPM0 0 VPS7 VPS6 VPS5 VPS4 VPS3 VPS2 VPS1 VPS0 HPS8 HPS7 HPS6 HPS5 HPS4 HPS3 HPS2 HPS1 HPS0 0 VPG7 VPG6 VPG5 VPG4 VPG3 VPG2 VPG1 VPG0 HPG8 HPG7 HPG6 HPG5 HPG4 HPG3 HPG2 HPG1 HPG0 0 0 0 0 0 0 0 BLK0 0 0 0 RMB(1) (2) 0 LSZ7 0 LSZ6 0 LSZ5 0 LSZ4 SZV1 SZV0 SZH1 SZH0 LSZ3 LSZ2 LSZ1 LSZ0 LSZ8 LSZ15 LSZ14 LSZ13 LSZ12 LSZ11 LSZ10 LSZ9 BXUW BXLW BXDW BXRW LBX7 LBX6 0 0 LBX5 BXUCT0 BXUC3 BXUC2 BXUC1 BXUC0 BXDCT0 BXDC3 BXDC2 BXDC1 BXDC0 LBX4 LBX3 LBX2 LBX1 LBX0 LBX8 LBX15 LBX14 LBX13 LBX12 LBX11 LBX10 LBX9 0 LFC7 0 LFC6 0 LFC5 EGCT0 EGC3 EGC2 EGC1 EGC0 LFC4 LFC3 LFC2 LFC1 LFC0 LFC8 LFC15 LFC14 LFC13 LFC12 LFC11 LFC10 LFC9 0 0 0 0 0 0 0 0 TG2 CTN1 CTA3 CTA2 CTA1 CTA0 0 TG1 TCK TG0 TB2 TR2 TB1 TR1 TB0 TR0 No. 7545-10/52 LC74735NW Command 00 (Main screen write address set command) • First byte DA0 to 7 7 6 5 4 3 2 1 Register — — — — — — V3 V2 Content State 1 0 0 0 0 0 0 1 0 1 Sub-identification code: 0 Command 0 identification code Main screen write address setting Function Notes 0 • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Main screen memory character position address (00 to 27, hexadecimal) QVGA mode: 40 characters WVGA mode: 33 characters Function Main screen memory line address (0 to E, hexadecimal) QVGA mode: 13 lines WVGA mode: 15 lines Notes 7 V1 V0 H5 H4 6 5 4 3 H3 2 H2 1 H1 H0 0 No. 7545-11/52 LC74735NW Command 01 (Subscreen write address set command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 0 0 0 0 1 0 0 Sub-identification code: 1 Command 0 identification code Subscreen memory write address setting Function Notes • Second byte DA0 to 7 7 6 5 4 3 2 1 0 Register — V0 — — — — — H0 Content State 0 0 1 0 0 0 0 0 0 1 Subscreen memory character address (0 to 1, hexadecimal) 2 characters Subscreen memory line address (0 to 1, hexadecimal) 2 lines Function Notes No. 7545-12/52 LC74735NW Command 10 (Main screen display character data write setting command) • First byte DA0 to 7 7 6 5 4 3 2 Register — — — — — — Content State 1 0 0 1 0 0 0 1 RM2 1 0 0 RM1 1 Sub-identification code 0 Command 1 identification code Display character data write setting When this command has been issued, the IC remains in display character data write mode until the CS pin is set high. Function Notes RM2 0 0 1 1 RM1 0 1 0 1 Mode (1)(2)(3)(4) (1)(2)(3)(4) (3)(4) (2)(3)(4) End Continuous Continuous Continuous Continuous write mode selection • Second byte (1) DA0 to 7 7 6 5 Register — — at Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Blinking off Blinking on Raised Recessed None Box displayed None Box displayed None Box displayed None Box displayed Blinking specification Function Notes 4 BXS Box specification: raised/recessed 3 BXL Box specification: left side 2 BXR Box specification: right side 1 BXU Box specification: upper 0 BXD Box specification: lower • Second byte (2) DA0 to 7 Register CB3 [MSB] CB2 Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character color specification 0000 to 1111, or 0 to F (hexadecimal) Character color specification When a character glyph is specified, 1 of 16 colors may be selected. Character background color specification 0000 to 1111, or 0 to F (hexadecimal) Character background color specification When a character glyph is specified, 1 of 16 colors may be selected. Function Notes 7 6 5 CB1 CB0 [LSB] CC3 [MSB] CC2 4 3 2 1 CC1 CC0 0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-13/52 LC74735NW • Second byte (3) DA0 to 7 7 6 5 Register — — CT0 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Character code specification Color table number 1 Color table number 2 Internal ROM External ROM Character Graphic Color table selection Function Notes 4 I/E ROM selection 3 M/G C10 [MSB] C9 Character/graphic specification 2 1 0 C8 • Second byte (4) DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * Transparent character specification I/E = 0 (Internal ROM) M/G = 0 (Character) Code = 1FF (hexadecimal) External ROM: 2048 characters 000 to 7FF (hexadecimal) 0 to 2047 Character code specification Character code Internal ROM: 512 characters 000 to 1FF (hexadecimal) 0 to 511 Function Notes 7 C7 6 C6 5 C5 4 C4 3 C3 2 C2 1 C1 C0 [LSB] 0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-14/52 LC74735NW Command 11 (Subscreen display character data write setting command) • First byte DA0 to 7 7 6 5 4 3 2 Register — — — — — — Content State 1 0 0 1 0 1 0 1 RM2 1 0 0 RM1 1 Sub-identification code 1 Command 1 identification code Display character data write setting When this command has been issued, the IC remains in display character data write mode until the CS pin is set high. Function Notes RM2 0 0 1 1 RM1 0 1 0 1 [1][2][3][4] [1][2][3][4] [3][4] [2][3][4] Mode End Continuous Continuous Continuous Continuous write mode selection • Second byte (1) DA0 to 7 7 6 5 4 3 2 1 0 Register — — Content State 0 0 0 0 0 0 0 0 Function Notes • Second byte (2) DA0 to 7 7 6 5 4 3 2 1 0 Register Content State 0 0 0 0 0 0 0 0 Function Notes *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-15/52 LC74735NW • Second byte (3) DA0 to 7 7 6 5 Register — — CT0 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Character code specification Color table number 1 Color table number 2 Internal ROM External ROM Only when transparent is selected Graphic only Color table selection Function Notes 4 I/E ROM selection 3 M/G C10 [MSB] C9 Graphic only 2 1 0 C8 • Second byte (4) DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * Transparent character specification I/E = 0 (Internal ROM) M/G = 0 (Character) Code = 1FF (hexadecimal) External ROM: 2048 characters 000 to 7FF (hexadecimal) 0 to 2047 Character code specification Character code Internal ROM: 512 characters 000 to 1FF (hexadecimal) 0 to 511 Function Notes 7 C7 6 C6 5 C5 4 C4 3 C3 2 C2 1 C1 C0 [LSB] 0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-16/52 LC74735NW Command 20 (System control setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — Content State 1 0 1 0 0 0 0 0 Sub-identification code 0 Command 2 identification code System control settings Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SRMERS 1 0 0 MRMERS 1 Erase sub-RAM. (Sets all values to 00.) Main screen Applications must provide a wait time of about 1ms. Use DSPOFF to execute this operation. Erase main RAM. (Sets all values to 00.) Wallpaper Applications must provide a wait time of about 1ms. Use DSPOFF to execute this operation. Erase the color table. (Sets all values to 00.) Reset all registers (All bits set to 0.) Normal operation Test mode 2 Normal operation Test mode 1 Normal mode Independent mode QVGA mode WVGA mode Specified by COM24. QVGA / WVGA The registers are reset when the CS pin is low. The reset state is cleared when the CS pin goes high. Applications must provide a wait time of about 1ms. Use DSPOFF to execute this operation. D/A converter on, 40 characters × 13 lines D/A converter off, 33 characters × 15 lines Function Notes Do not use test mode. This bit must always be set to 0. Do not use test mode. This bit must always be set to 0. Normal / Independent 7 TSTMD2 6 TSTMD1 5 Q/W2 4 Q/W1 3 SYSRST 2 CTERS No. 7545-17/52 LC74735NW Command 21 (Display control setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — Content State 1 0 1 0 0 0 0 1 Extended command 1 identification code Command 2 identification code Display control Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Enables stopping the LC oscillator Disables stopping the LC oscillator BK1 0 0 1 BK0 0 1 0 Blinking period 1/16 1/32 1/64 Notes LC oscillator on/off control Valid when the display is off. Blinking period Specified for screen units. 7 LCSOFF 6 BK1 5 BK0 4 SBG1 Display after the main screen Display before the main screen Iterated display (wallpaper) Horizontal 2-character x vertical 2-character display (sprite) Display off Display on Display off Display on Display off Display on Subscreen display specification 3 SBG0 Subscreen display specification 2 DSPBG Screen background color 1 DSPGS Subscreen (wallpaper) 0 DSPGM Main screen *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-18/52 LC74735NW Command 22 (I/O polarity control setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — Content State 1 0 1 0 0 0 1 0 Extended command 2 identification code Command 2 identification code I/O polarity control 1 Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BLD1 0 0 1 1 BLD0 0 1 0 1 Function BLY output delay ±0 +1 +2 +3 Notes 7 BLD1 BLK output delay setting In dot clock units 6 BLD0 5 BLOP BLK output: positive polarity BLK output: negative polarity BLO1 0 0 1 1 BLO0 0 1 0 1 BLK output Text + character background + wallpaper + screen background Text + character background + wallpaper Text + character background Text BLK output polarity selection 4 BLO1 BLK output control 3 BLO0 2 CKP Clock input: positive polarity Clock input: negative polarity VSYNC input: negative polarity VSYNC input: positive polarity HSYNC input: negative polarity HSYNC input: positive polarity Clock input polarity selection 1 VIP VSYNC input polarity selection 0 HIP HSYNC input polarity selection *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-19/52 LC74735NW Command 23 (Screen background color setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — Content State 1 0 1 0 0 0 1 1 Extended command 3 identification code Command 2 identification code Screen background color Function Notes • Second byte DA0 to 7 7 6 5 Register — — BGCT1 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Screen background color 0000 to 1111 0 to F (hexadecimal) Screen background color Selects 1 of 16 values. T1 0 0 1 T0 0 1 X Color table setting Color table No. 2 Invalid setting Color table No. 1 Screen background color Color table setting Function Notes 4 BGCT0 3 BGC3 2 BGC2 1 BGC1 0 BGC0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-20/52 LC74735NW Command 24 (I/O polarity control setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — Content State 1 0 1 0 0 1 0 0 Extended command 4 identification code Command 2 identification code I/O polarity control 2 Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MD1 0 0 1 On Off Disabled Enabled Disabled Enabled Clock output positive polarity Clock output negative polarity VBLK input negative polarity VBLK input positive polarity HBLK input negative polarity HBLK input positive polarity MD0 0 1 0 Function Main screen display area 40 characters × 13 lines 33 characters × 15 lines 40 characters × 16 lines Notes Main screen display area selection Only valid in independent mode. COM20 to COM2 *: In WVGA mode: fixed 33-character × 15-line display D/A converter used/unused selection Only valid in independent mode. COM20 to COM2 VBLK input selection 7 DSPMD1 6 DSPMD0 5 D/ASEL 4 VBLKON 3 HBLKON HBLK input selection 2 CKOP Clock output polarity selection 1 VBP VBLK input polarity selection 0 HBP HBLK input polarity selection *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-21/52 LC74735NW Command 25 (Output control 3 setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — Content State 1 0 1 0 0 1 0 1 Extended command 5 identification code Command 2 identification code Output control Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 6 TOKSL 1 0 1 0 1 0 1 0 2 OTMD0 1 0 1 0 0 QRM0 1 Normal operation CE pin held fixed at the high level Normal mode Transmissive mode The color specified at address 0 in color table No. 1 is displayed in the transmissive state. Falling edge detection Rising edge detection Output off state (always low) Normal output OTMD2 0 0 0 0 OTMD1 0 0 1 1 OTMD0 0 1 0 1 Output Normal RGB No. 1 RGB No. 2 High-impedance state Transmissive mode specification Function CE pin Notes 7 CEHSL 5 VIPSL Selects the detection polarity for the VSYNC signal. CLKOUT pin (pin 18) Output control 4 OTMD2 3 OTMD1 A0 to 17 output selection 1 QRM1 QRM1 0 0 1 1 QRM0 0 1 0 1 ROM selection ROM1 ROM2 ROM3 ROM4 ROM selection when character output is specified in QVGA mode *: This register is set to the all bits zero state when the IC is reset by the RST pin. • When RGB No. 1 or RGB No. 2 is selected: The A17 to 9 output is set to the RD2 to BD0 three-value output. (Supported by connecting external resistors.) * It will not be possible to use external ROM in this case. (Only internal ROM can be used.) No. 1: RGB = 000 = Black only. Here the output will go to the high-impedance state giving the middle level due to the external resistor. For areas other than the display area, the output will be at the low level. No. 2: When any individual color is zero, the output will go to the high-impedance state giving the middle level due to the external resistor. For areas other than the display area, the output will be at the low level. No. 7545-22/52 LC74735NW Command 30 (Main screen: vertical display start position setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 0 1 1 0 0 0 0 Extended command 0 identification code Command 3 identification code Main screen: vertical display start position setting Function Notes • Second byte DA0 to 7 Register VPM7 (MSB) VPM6 Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VSYNC VSM HSYNC Main screen The vertical display start position is specified by the 8 bits VPM7 to 0. The weight of the LSB is 1H in QVGA mode, and the weight of the LSB is 2H in WVGA mode HSM Main screen display area The vertical display start position, VSM, is given by: VSM = 1H × ( ∑ 2 n V P M n ) n=0 7 Function Notes 7 6 5 VPM5 4 VPM4 3 VPM3 2 VPM2 This setting applies in screen units. 1 VPM1 VPM0 (LSB) 0 No. 7545-23/52 LC74735NW Command 31 (Main screen: horizontal display start position setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — HPM8 (MSB) Content State 1 0 1 1 0 0 1 0 1 Extended command 1 identification code Command 3 identification code Main screen: horizontal display start position setting Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 • Setting disable range QVGA : 00 to 07 HEX WVGA : 00 to 07 HEX This setting applies in screen units. Tc: The input clock frequency in operating mode. The horizontal display start position, HSM, is given by: HSM = 1Tc × ( ∑ 2 n H P M n ) + α n=0 8 Function Notes 7 HPM7 6 HPM6 5 HPM5 α = 57 Tc Main screen The horizontal display start position is specified by the 9 bits HPM8:0. The weight of the LSB is 1TC in QVGA mode, and the weight of the LSB is 2TC in WVGA mode 4 HPM4 3 HPM3 2 HPM2 1 HPM1 HPM0 (LSB) 0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-24/52 LC74735NW Command 32 (Subscreen: vertical display start position setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 0 1 1 0 1 0 0 Extended command 2 identification code Command 3 identification code Subscreen: vertical display start position setting Function Notes • Second byte DA0 to 7 Register VPS7 (MSB) VPS6 Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VSYNC VSS HSYNC Subscreen (wallpaper) The vertical display start position is specified by the 8 bits VPS7 to 0. The weight of the LSB is 1H in QVGA mode, and the weight of the LSB is 2H in WVGA mode HSS Subscreen display area This setting applies in screen units. The vertical display start position, VSS, is given by: VSS = 1H × ( ∑ 2 n V P S n ) n=0 7 Function Notes 7 6 5 VPS5 4 VPS4 3 VPS3 2 VPS2 1 VPS1 VPS0 (LSB) 0 No. 7545-25/52 LC74735NW Command 33 (Subscreen: horizontal display start position setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 HPS8 (MSB) Register — — — — — — Content State 1 0 1 1 0 1 1 0 1 Extended command 3 identification code Command 3 identification code Subscreen: horizontal display start position setting Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 • Setting disable range QVGA : 00 to 2F HEX WVGA : 00 to 17 HEX This setting applies in screen units. Tc: The input clock frequency in operating mode. The horizontal display start position, HSS, is given by: HSS = 1Tc × ( ∑ 2 n H P S n ) + α n=0 8 Function Notes 7 HPS7 6 HPS6 5 HPS5 α = 14 Tc Subscreen (wallpaper) The horizontal display start position is specified by the 9 bits HPS8 to 0. The weight of the LSB is 1TC in QVGA mode, and the weight of the LSB is 2TC in WVGA mode 4 HPS4 3 HPS3 2 HPS2 1 HPS1 HPS0 (LSB) 0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-26/52 LC74735NW Command 34 (Screen background color: vertical display start position setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 0 1 1 1 0 0 0 Extended command 4 identification code Command 3 identification code Screen background color: vertical display start position setting Function Notes • Second byte DA0 to 7 Register VPG7 (MSB) VPG6 Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VSYNC VSG HSYNC Screen background color The vertical display start position is specified by the 8 bits VPG7 to 0. The weight of the LSB is 1H in QVGA mode, and the weight of the LSB is 2H in WVGA mode HSG Screen background color display area The vertical display start position, VSG, is given by: VSG = 1H × ( ∑ 2 n V P G n ) n=0 7 Function Notes 7 6 5 VPG5 4 VPG4 3 VPG3 2 VPG2 This setting applies in screen units. 1 VPG1 VPG0 (LSB) 0 No. 7545-27/52 LC74735NW Command 35 (Screen background color: horizontal display start position setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 HPS8 (MSB) Register — — — — — — Content State 1 0 1 1 1 0 1 0 1 Extended command 5 identification code Command 3 identification code Screen background color: horizontal display start position setting Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The horizontal display start position, HSG, is given by: HSG = 1Tc × ( ∑ 2 n H P G n ) n=0 8 Function Notes 7 HPG7 6 HPG6 5 HPG5 Tc: The input clock frequency in operating mode. Screen background color The horizontal display start position is specified by the 9 bits HPG8 to 0. The weight of the LSB is 1TC in QVGA mode, and the weight of the LSB is 2TC in WVGA mode This setting applies in screen units. 4 HPG4 3 HPG3 2 HPG2 1 HPG1 HPG0 (LSB) 0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-28/52 LC74735NW Command 40 (Character size control setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — Content State 1 1 0 0 0 0 0 0 Extended command 0 identification code Command 4 identification code Display character data write settings Function Notes • Second byte DA0 to 7 7 6 5 4 3 Register — — — — SZV1 Content State 0 0 0 0 0 1 0 2 SZV0 1 0 1 0 0 SZH0 1 SZV1 0 0 1 1 SZH1 0 0 1 1 SZV0 0 1 0 1 SZH0 0 1 0 1 Character size 1× 2× 3× 4× Character size 1× 2× 3× 4× Function Notes Specifies the character size in the vertical direction. This setting applies in line units. 1 SZH1 Specifies the character size in the horizontal direction. This setting applies in line units. *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-29/52 LC74735NW Command 41 (Character size line U control setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 0 0 0 1 0 0 Extended command 1 identification code Command 4 identification code Character size line U control Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Character size line setting control Upper lines Function Notes 7 LSZ7 6 LSZ6 5 LSZ5 4 LSZ4 3 LSZ3 2 LSZ2 1 LSZ1 0 LSZ0 No. 7545-30/52 LC74735NW Command 42 (Character size line D control setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 0 0 1 0 0 0 Extended command 2 identification code Command 4 identification code Character size line D control Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Character size line setting control Lower lines Function Notes 7 LSZ15 6 LSZ14 5 LSZ13 4 LSZ12 3 LSZ11 2 LSZ10 1 LSZ9 0 LSZ8 No. 7545-31/52 LC74735NW Command 50 (Box control: U setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 0 1 0 0 0 0 Extended command 0 identification code Command 5 identification code Box control U settings Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 0 4 BXUCT0 1 3 BXUC3 0 1 0 1 0 1 0 1 Box display: upper side color specification 0000 to 1111 0 to F (hexadecimal) Box display: upper side Color specification This setting applies in line units. Color table No. 2 Color table No. 1 Box display: upper side Color table specification This setting applies in line units. Function Box display: upper side is 1 dot. Box display: upper side is 2 dots. Box display: left side is 1 dot. Box display: left side is 2 dots. Notes Box display: upper side Dot width. This setting applies in line units. Box display: left side Dot width. This setting applies in line units. 7 BXUW 6 5 BXLW — 2 BXUC2 1 BXUC1 0 BXUC0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-32/52 LC74735NW Command 51 (Box control: D setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 0 1 0 1 0 0 Extended command 1 identification code Command 5 identification code Box control D settings Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 0 4 BXDCT0 1 3 BXDC3 0 1 0 1 0 1 0 1 Box display: lower side color specification 0000 to 1111 0 to F (hexadecimal) Box display: lower side Color specification This setting applies in line units. Color table No. 2 Color table No. 1 Box display: lower side Color table specification This setting applies in line units. Function Box display: lower side is 1 dot. Box display: lower side is 2 dots. Box display: right side is 1 dot. Box display: right side is 2 dots. Notes Box display: lower side Dot width. This setting applies in line units. Box display: right side Dot width. This setting applies in line units. 7 BXDW 6 5 BXRW — 2 BXDC2 1 BXDC1 0 BXDC0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-33/52 LC74735NW Command 52 (Box control: U line setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 0 1 1 0 0 0 Extended command 2 identification code Command 5 identification code Box control U line setting Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Box control line setting control Upper lines Function Notes 7 LBX7 6 LBX6 5 LBX5 4 LBX4 3 LBX3 2 LBX2 1 LBX1 0 LBX0 No. 7545-34/52 LC74735NW Command 53 (Box control: D line control setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 0 0 1 1 0 0 Extended command 3 identification code Command 4 identification code Box control D line setting Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Box control line setting control Lower lines Function Notes 7 LBX15 6 LBX14 5 LBX13 4 LBX12 3 LBX11 2 LBX10 1 LBX9 0 LBX8 No. 7545-35/52 LC74735NW Command 60 (Border control setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 Register — — — — — — BLK1 Content State 1 1 1 0 0 0 0 1 0 1 Extended command 0 identification code BLK1 0 0 1 1 BLK0 0 1 0 1 Border mode specification Normal display Border Shadow 1 (lower side) Shadow 2 (lower and right sides) Command 6 identification code Border control setting Function Notes Border mode specification This setting applies in line units. 0 BLK0 • Second byte DA0 to 7 7 6 5 Register — — — Content State 0 0 0 0 4 EGCT0 1 3 EGC3 0 1 0 1 0 1 0 1 Border display: color specification 0000 to 1111 0 to F (hexadecimal) Border display color specification This setting applies in line units. Color table No. 2 Color table No. 1 Border display Color table specification This setting applies in line units. Function Notes 2 EGC2 1 EGC1 0 EGC0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. No. 7545-36/52 LC74735NW Command 61 (Border control U line setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 1 0 0 1 0 0 Extended command 1 identification code Command 6 identification code Border control U line setting Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Border control line settings control Upper lines Function Notes 7 LFC7 6 LFC6 5 LFC5 4 LFC4 3 LFC3 2 LFC2 1 LFC1 0 LFC0 No. 7545-37/52 LC74735NW Command 62 (Border control D line setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 1 0 1 0 0 0 Extended command 2 identification code Command 6 identification code Border control D line setting Function Notes • Second byte DA0 to 7 Register Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Border control line settings control Lower lines Function Notes 7 LFC15 6 LFC14 5 LFC13 4 LFC12 3 LFC11 2 LFC10 1 LFC9 0 LFC8 No. 7545-38/52 LC74735NW Command 70 (Color table write address setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — — Content State 1 1 1 1 0 0 0 0 Sub-identifier code 0 Command 7 identification code Color table write address setting Function Notes • Second byte DA0 to 7 7 6 5 4 Register — — — CTN1 CTA3 CTA2 0 1 0 1 0 1 0 1 0 1 Color table address 0 to 15 0 to F (hexadecimal) 16 values Addresses of the color tables Color table No. 1 selected Color table No. 2 selected Color table selection No. 1 or No. 2 Content State Function Notes 3 2 1 CTA1 CTA0 0 No. 7545-39/52 LC74735NW Command 71 (Color table data write setting command) • First byte DA0 to 7 7 6 5 4 3 2 1 Register — — — — — — — Content State 1 1 1 1 0 1 0 0 0 RM3 1 RM3 0 1 Mode End Continuous Continuous write mode selection Sub-identifier code 1 Command 7 identification code Display character data write setting When this command has been issued, the IC remains in display character data write mode until the CS pin is set high. Function Notes [1][2] [1][2] • Second byte (1) DA0 to 7 7 6 5 4 3 Register — — — — TOK Content State 0 0 0 0 0 1 0 1 0 1 0 1 Color table B output 000 to 111 0 to 7 (hexadecimal) Color Transparent (BLK output: low) Function Notes 2 TB2 1 TB1 Color table setting B 0 TB0 • Second byte (2) DA0 to 7 7 6 5 Register — — TG2 Content State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Color table R output 000 to 111 0 to 7 (hexadecimal) Color table G output 000 to 111 0 to 7 (hexadecimal) Function Notes 4 TG1 Color table setting G 3 TG0 2 TR2 1 TR1 Color table setting R 0 TR0 *: This register is set to the all bits zero state when the IC is reset by the RST pin. When transparent is selected, the BLK output is set to the low level. (Transparent state) The RGB outputs are values from the color table. The transparent specification is best for color table 1, address 0000. Since the data is set to all zeros by a RAM clear operation, the RGB output will be 000 (black) and the BLK output will be 1. Transparent is specified by setting the TOK bit to 1. (The BLK output will go to the low level.) No. 7545-40/52 LC74735NW Display Structure The display screen consists of a 40-character × 15-line grid. QVGA mode (12 × 18 dot characters) 40-character × 13-line QVGA panel (480 × 234) WVGA mode (12 × 16 dot characters) 33-character × 15-line WVGA panel (800 × 480) Up to a maximum of 600 characters can be displayed. If the character size is increased, the number of characters that can be displayed will decrease to be fewer than 600 characters. Display memory is addressed by specifying a line address (0 to 14 (decimal) and a character position address (0 to 39 (decimal)). 40 characters 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 00 01 02 03 04 05 06 0 1 2 3 4 5 6 7 8 9 A B C D E HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 HEX 15 rows 07 08 09 10 11 12 13 14 Display Structure (Display memory address) No. 7545-41/52 LC74735NW Sample Application Circuits • QVGA mode (analog output) 3.3VDC + 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 A14 61 A15 VSS3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A12 VDD3 VDD3 VSS3 A13 A11 GND GND 1 60 A16 59 A17 58 CE 57 OE VDD3 VSS3 D0 D1 D2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND GND GND 22 µF VSS1 OSCin OSCout CTRL1 SCLK SIN CS VDD1 VSYNC VBLK HSYNC HBLK TEST1 TEST2 RST VSS1 VDD1 CLKOUT 2 3 GND 4 5 6 7 8 SCLK SIN CS VSYNC HSYNC 9 10 11 12 13 10 kΩ 14 15 16 17 GND 18 19 20 GND LC74735NW D3 D4 D5 D6 D7 VDD1 VSS1 D8 D9 D10 CCOMP CVREF D11 RREF 39 0.1 µF GND_A GND_A GND_A VSS2 40 GOUT 35 1 µF + VSS1 OUTR ROUT VSS1 BOUT 36 VDD2 32 VDD1 GD2 GD1 GD0 RD2 RD1 RD0 BD2 BD1 BD0 29 BLK 30 21 22 23 24 25 26 27 28 31 33 34 37 + GND_A GND GND_A GND_A GND_A + GND_A GND_A 1 µF 68 38 + + GND_A GND_A + GND_A + + GND_A GND_A TR3 A1392 GND_A ROUT GOUT No. 7545-42/52 BOUT BLK LC74735NW • WVGA mode (digital output) 3.3VDC + 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 A14 61 A15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A12 VSS3 VSS3 VDD3 VDD3 A13 A11 GND GND 1 60 VSS1 OSCin OSCout A16 59 A17 58 CE 57 CTRL1 SCLK SIN CS VDD1 VSYNC VBLK HSYNC HBLK TEST1 TEST2 RST VSS1 VDD1 CLKOUT OE VDD3 VSS3 D0 D1 D2 56 55 GND 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND CLK 2 3 4 SCLK SIN CS VSYNC HSYNC 10 kΩ 5 6 7 8 9 10 11 12 13 14 15 1 µF + 16 17 GND 18 LC74735NW D3 D4 D5 D6 D7 VDD1 VSS1 D8 D9 D10 CCOMP CVREF D11 RREF 39 VSS2 40 19 20 VSS1 VDD1 GOUT 35 36 OUTR ROUT BOUT GD2 GD1 GD0 VDD2 32 VSS1 31 RD2 RD1 RD0 BD2 BD1 BD0 29 BLK 30 GND 21 22 23 24 25 26 27 28 33 34 37 GND 38 GND GND_A RD2 RD1 RD0 GD2 GD1 GD0 BD2 BD1 BD0 BLK No. 7545-43/52 LC74735NW Operational Description Command transfer method Overview • Commands are transferred in 8-bit units, LSB first. Always send a first byte and a second byte (16 bits). • Command 10 (Main RAM write) Command 11 (Wallpaper write) Command 71 (Color table write) When these commands specify continuous mode (RM2, 1 RM3), the IC is locked in continuous write mode. (Continuous write mode is cleared by setting the CS pin high.) Writing Data to VRAM • Write start address specification Use command 00 to set the write start address. V3:0: Vertical direction, H5:0: Horizontal direction • Data write Continuous write mode differs depending on the write mode specification. (RM1, RM2) 1 Normal (RM2 = 0, RM1 = 0: initial state) *Continuous mode not used* -- COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 command wait state -2 Write continuous (RM2 = 0, RM1 = 1): Mode 2 COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 3 Write continuous (RM2 = 1, RM1 = 0): Mode 3 COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-3 10-2-4 4 Write continuous (RM2 = 1, RM1 = 1): Mode 4 COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-2 10-2-3 10-2-4 *: In modes 2, 3, and 4, the IC remains locked in continuous write mode until the CS pin is set high. • The write address is automatically incremented. • The write address is retained unless the IC is reset or a new write address is issued. No. 7545-44/52 LC74735NW Color Table write • Write start address specification Use command 70 to set the color table write start address. CTN1: Color table specification (No.1, No.2), CTA3 to 0: Address specification No.1 R 0000 0001 0010 XXX G XXX B XXX 0000 0001 0010 No.2 R XXX G XXX B XXX Address 1110 1111 1110 1111 • Data write Continuous write mode differs depending on the write mode specification. (RM3) 1 Normal (RM3 = 0: initial state) *Continuous mode not used* -- COM71-1 71-2-1 71-2-2 command wait state --2 Write continuous (RM3 = 1) mode COM71-1 71-2-1 71-2-2 *: In mode 2, the IC remains locked in continuous write mode until the CS pin is set high. • The write address is automatically incremented. • The write address is retained unless the IC is reset or a new write address is issued. No. 7545-45/52 LC74735NW Display format Color Specification Related Items • When a character is specified Specify color with the character color (character area) and character background color (outside the character area) Character color: One of 16 colors Character background color: One of 16 colors Color tables: Table No. 1 or No. 2 specified by CT1 to CT0. (COM1-2-3: VRAM) ¡ One of 32 types Character color Specified by CC0 to CC3: One of 16 colors (COM1-2-2: VRAM) Character background color Specified by CB0 to CB3: One of 16 colors (COM1-2-2: VRAM) • When a graphic is specified Specify color is in dot units (12 × 18 or 12 × 16) One of 16 colors (FROM) Color tables: Table No. 1 or No. 2 specified by CT1 to CT0. (COM1-2-3: VRAM) ¡ One of 32 types Specified by FROM: One of 16 types No. 7545-46/52 LC74735NW Display Control Related Items • Blinking: In character units Normal at1 = 0 (COM1-2-1: VRAM) Blinking at1 = 1 Display alternates between normal and transparent with the blinking period. (COM21-2: BK1, 0) • Border display: Only valid for font specified characters Border color: One of 16 colors (COM60-2 EGC3 to 0) Color table specification (COM60-2 EGCT0) ¡ One of 32 types Border mode control (COM60-1 BLK1, 0) Border Shadow 1: lower Shadow 2: lower + right • Character size: Specified in line units The character size is specified as 1x to 4x independently for the vertical and horizontal directions. (COM40-2) No. 7545-47/52 LC74735NW Box Display (raised/recessed) Raised 12 dots Recessed 18 dots or 16 dots • • • • • • Raised/recessed specification: In character units (COM10-2-1 BXS) Left side - displayed/undisplayed specification: in character units (COM10-2-1 BXL) Right side - displayed/undisplayed specification: in character units (COM10-2-1 BXR) Upper side - displayed/undisplayed specification: in character units (COM10-2-1 BXU) Lower side - displayed/undisplayed specification: in character units (COM10-2-1 BXD) Color specification: In line units COM50 (Upper side) COM51 (Lower side) BXUC3:0: One of 16 colors BXDC3:0: One of 16 colors Color table specification BXUCT0 BXDCT0 ’ One of 32 types Dot width specification: 1 or 2 dots Each of left, right, upper, and lower can be specified independently. (BXLW BXRW BXUW BXDW) No. 7545-48/52 LC74735NW Screen Structure Screen background color Wallpaper display screen Main screen • QVGA mode (12 × 18 dot characters) 40-character × 13-line QVGA panel • WVGA mode (12 × 16 dot characters) 33-character × 15-line WVGA panel • For each screen: Display on/off (transparent) can be specified independently. • For each screen: The display start position can be specified independently. The wallpaper display screen and the main screen require xxxx clocks before the horizontal start position is reached. No. 7545-49/52 LC74735NW Display Format • QVGA Character specification 12 dots Graphic 12 dots 18H • WVGA Character specification 24 dots Graphic 24 dots Each dot is 2 × 2 pixels (A 12 × 16 structure magnified 2× in both the horizontal and vertical directions) 32H ROM structure Internal ROM (512 characters) • Character font QVGA: 12 × 18-dot structure WVGA: 24 × 32-dot structure, i.e. 12 × 16 times 4 • Graphics CQVGA: 12 × 18-dot structure WVGA: 12 × 16-dot structure, i.e. displayed magnified 2× in both the horizontal and vertical directions. Note that the contents of ROM differ for QVGA and WVGA. (That is, different ROMs for QVGA and WVGA must be created.) No. 7545-50/52 LC74735NW External ROM (2048 characters) • Conditions Use a 16-bit 4M ROM with an access time less than 3 times the dot clock period Example: DCLK = 50 MHz = 20 ns period × 3 = under 60 ns DCLK = 10 MHz = 100 ns period × 3 = under 300 ns • ROM map • Address A1 to A0 00 12 dots A6 to A2 QVGA mode 18 dots WVGA mode 16 dots 01 10 11 • Data D15 to D12, D11 to D0 Unused Used [1] [2] [3] [4] A17 to A7 (10 bits) = 2048 characters = character codes • Display appearance QVGA: 1 character = 12 × 18 dots Character font: [1] Graphics: [1] + [2] + [3] + [4] WVGA: 1 character = 12 × 16 dots Character font: [1] [2] [3] [4] Graphics: ([1] + [2] + [3] + [4]) displayed magnified 2× in both the horizontal and vertical directions. 12 12 12 [1]+[2] +[3]+[4] ×2 12 16 [1] [2] 16 16 [3] [4] 16 No. 7545-51/52 LC74735NW Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 2003. Specifications and information herein are subject to change without notice. PS No. 7545-52/52