LC74776

Ordering number : EN*6018 CMOS IC LC74776, 74776M On-Screen Display Controller IC Preliminary Overview The LC74776/M is an on-screen display controller CMOS IC that displays characters and patterns on the TV screen under microprocessor control. This IC includes a built-in PDC/VPS/UDT interface circuit. Package Dimensions unit: mm 3196-DIP30SD [LC74776] 30 16 Functions • Display format: 24 characters by 12 rows (Up to 288 characters) • Character format: 12 (horizontal) × 18 (vertical) dots • Character sizes: Three sizes each in the horizontal and vertical directions • Characters in font: 256 (Of the 256 characters, one is a space character (FE hexadecimal) and one is a transparent space character (FF hexadecimal)) • Initial display positions: 64 horizontal positions and 64 vertical positions • Blinking: Specifiable in character units • Blinking types: Two periods supported: 1.0 second and 0.5 second • Blanking: Over the whole font (12 × 18 dots) • Background color: 8 colors (internal synchronization mode): 4fSC and 2fSC Blue background only: NTSC • Line background color: Three lines can be set up. 8 line background colors (in internal synchronization mode): 4fSC and 2fSC • External control input: 8-bit serial input format • On-chip sync separator circuit • Video outputs: PAL and NTSC format composite video outputs • On-chip PDC/VPS/UDT interface circuit supporting I2C • Package: DIP30SD MFP30S 10.16 8.6 1 27.2 15 1.14 1.78 0.48 0.95 SANYO: DIP30SD unit: mm 3216A-MFP30S [LC74776M] 30 16 3.0 3.95max 3.25 2.5max 1 15.3 15 2.15 0.15 0.35 1.0 0.65 0.1 SANYO: MFP30S Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 20399RM(OT) No. 6018-1/35 0.65 10.5 7.9 9.2 0.25 LC74776, 74776M Pin Assignment LC74776 LC74776M No. 6018-2/35 LC74776, 74776M Pin Functions Pin no. 1 2 Pin VSS1 XtalIN XtalOUT (MUTE) Crystal oscillator input switching (CHABLK) I2C clock input LC oscillator connections Crystal oscillator (MUTE input) Ground Function Ground connection (digital system ground) These pins are used either to connect the crystal and capacitors used to form an external crystal oscillator circuit to generate the internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.) Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character . frame) output. This is a 3-value output. Clock input for the PDC/VPS data output. I2C bus. Connection for the external coil and capacitor for the oscillator used to generate the character output dot clock Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs either the crystal oscillator clock if CS and RST are low, or the VCO clock if CS and RST are high. (This signal is not output after a command reset.) Enable input for the OSD serial data input. Serial data input is enabled when this pin is low. A pull-up resistor is built in and the input has hysteresis characteristics. Serial data input enable pin. A pull-up resistor is built in and the input has hysteresis characteristics. Serial data input. A pull-up resistor is built in and the input has hysteresis characteristics. Composite video signal level adjustment power supply (analog system power supply) Charge pump output. Connect a low-pass filter to this pin. VCO oscillator control voltage input. (For data slicing) Ground (VCO ground) VCO oscillator range adjustment resistor connection This pin must either be connected to ground or left open Power supply (+5 V) Video signal output Ground Video signal input Video signal input Power supply (+5 V) Sync separator circuit input Slice level output Composite synchronizing signal output I2C bus data I/O Background color phase adjustment Reset input Power supply (+5 V) Power supply (+5 V: VCO power supply) Composite video signal output Ground (analog system ground) Composite video signal input SECAM chrominance signal input Power supply (+5 V: digital system power supply) Video signal input to the internal sync separator circuit Slice level verification pin Internal sync separator circuit composite synchronizing signal output. The signal actually output can be switched by MOD0 and SEL0. The DAV signal is output in the initial state. PDC/VPS data I/O. The I2C bus write address is [0111 1100]. The I2C bus read address is [0111 1101]. Background color phase adjustment resistor connection System reset input. A pull-up resistor is built in and the input has hysteresis characteristics. Power supply (+5 V: digital system power supply) Notes 3 4 CTRL1 (CHABLK) SCL OSCIN OSCOUT 5 6 7 8 SYNCJDC External synchronizing signal judgment output 9 CS Enable input 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SCLK SIN VDD2 CPOUT VCOIN VSS3 VCOR NC VDD3 CVOUT VSS2 CVIN CVCR VDD1 SYNIN SEPC SEPOUT SDA Clock input Data input Power supply Charge pump output Oscillator control voltage input Ground Oscillator range adjustment 27 28 29 30 CDLR RST VDD1 Note: *Both VDD1 pins must be connected to power. No. 6018-3/35 LC74776, 74776M Absolute Maximum Ratings Paremeter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDDmax VINmax VOUTmax Pd max Topr Tstg Conditions VDD1, VDD2, and VDD3 All input pins SDA, SYNCJDG, and SEPOUT Ta = 25°C Ratings VSS – 0.3 to VSS + 6.5 VSS – 0.3 to VDD1 + 0.3 VSS – 0.3 to VDD1 + 0.3 350 –30 to + 70 –40 to + 125 Unit V V V mW °C °C Allowable Operating Ranges Ratings Paremeter Supply voltage Symbol VDD1 VDD2 VIH1 Input high-level voltage VIH2 VIH3 Input low-level voltage VIL1 VIL2 Pull-up resistance Composite video signal input voltage Input voltage RPU VIN1 VIN2 VIN3 fOSC1 Oscillator frequencies fOSC2 fOSC3 VDD1, VDD3 VDD2 CS, SIN, SCLK, SDA, SCL, RST, MUTE CTRL1 RST, CS, SIN, SCLK, SDA, SCL, MUTE CTRL1 RST, CS, SIN, SCLK, MUTE Applies to pins set up by options. CVIN, CVCR: VDD1 = 5V SYNIN: VDD1 = 5V XtalIN (when used for external clock input) fIN = 2fsc or 4fsc: VDD1= 5V XtalIN and XtalOUT oscillator pins (2fsc: PAL) XtalIN and XtalOUT oscillator pins (4fsc: PAL) OSCIN and OSCOUT oscillator pins (LC oscillator) 5 1.5 0.10 8.867 17.734 10 Conditions min 4.5 4.5 0.8VDD1 0.8VDD1 0.7VDD1 VSS – 0.3 VSS – 0.3 25 50 2.0 2.0 2.5 5.0 typ 5.0 5.0 max 5.5 6.5 5.5 VDD1 + 0.3 VDD1 + 0.3 0.2VDD1 0.3VDD1 90 Unit V V V V V V V kΩ Vp-p Vp-p Vp-p MHz MHz MHz Note: Applications must be especially cautious about noise when using the XtalIN input pin in clock input mode. Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified Ratings Paremeter Input off leakage current Output off leakage current Output high-level voltage Symbol Ileak1 Ileak2 VOH1 VOL1 VOL2 Three-value output voltage VO CVIN, CVCR CVOUT, SDA SEPOUT, CPOUT, SYNCJDG VDD1 = 4.5V, IOH = –1.0 mA SEPOUT, CPOUT, SYNCJDG VDD1 = 4.5 V, IOL = 1.0 mA SDA: VDD1 = 5.0V, IOL = 3.0 mA H CHABLK: VDD1 = 5.0 V M L IIH Input current IIL IDD1 IDD2 SYNC level VSN CTRL1, SDA, SCL, VCOIN VIN = VSS1 VDD1 and VDD3: With all outputs open Xtal: 17.734 MHz, LC: 8 MHz VDD2: VDD2 = 5 V (1) CVOUT: VDD1 = 5.0 V, VDD2 = 5.0 V (2) (3) (1) Pedestal level VPD CVOUT: VDD1 = 5.0 V, VDD2 = 5.0 V (2) (3) 0.80 1.00 1.40 1.37 1.57 1.97 –1 µA RST, CS, SIN, SCLK, SDA, SCL, CTRL1, MUTE, VCOIN: VIN = VDD1 3.3 1.8 0 3.5 Conditions min typ max 1 1 Unit µA µA V Output low-level voltage 1.0 0.4 5.0 2.3 0.8 1 V V V V V µA Operating mode current drain 40 20 mA mA V V V V V V Continued on next page. No. 6018-4/35 LC74776, 74776M Continued from preceding page. Paremeter Symbol Conditions (1) Color burst low level VCBL CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) (1) Color burst high level VCBH CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) (1) Background color (other than blue) low level VRSL0 CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) (1) Background color (other than blue) high level VRSH0 CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) (1) Blue background color 1 low level VRSL1 CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) (1) Blue background color 2 low level VRSL2 CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) (1) Blue background color 1 and 2 high level VRSH CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) (1) Frame level 0 VBK0 CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) (1) Frame level 1 VBK1 CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) (1) Character level VCHA CVOUT: VDD1 = 5.0V, VDD2 = 5.0V (2) (3) Notes: (1): When the sync level = 0.8 V (2): When the sync level = 1.0 V (3): When the sync level = 1.4 V The blue background color (1 or 2) is set as an option. Ratings min typ 1.07 1.27 1.67 1.67 1.87 2.27 1.23 1.43 1.83 2.37 2.57 2.97 1.16 1.36 1.76 1.52 1.72 2.12 2.01 2.21 2.61 1.50 1.70 2.10 2.08 2.28 2.68 2.65 2.85 3.25 max Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V No. 6018-5/35 LC74776, 74776M Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V • OSD Write (See figure 1.) Ratings Paremeter Minimum input pulse width Symbol tW (SCLK) tW (CS) tSU (CS) tSU (SIN) th (CS) th (SIN) tword twt SCLK CS (The period when CS is high) CS SIN CS SIN The 8-bit data write time The RAM data write time Conditions min 200 1 200 200 2 200 4.2 1 typ max Unit ns µs ns ns µs ns µs µs Data setup time Data hold time One word write time • PDC/VPS Write and Read (I2C timing) Ratings Paremeter SCL frequency Bus release time Start/hold SCL low-level period SCL high-level period Data hold Data setup Rise time Fall time Stop/setup Symbol fSCL tBUF tHD: STA tLOW tHIGH tHD: DAT tSU: DAT tR tF tSU: STO 4.0 4.7 4.0 4.7 4.0 0 250 1000 300 Conditions min typ max 100 Unit kHz µs µs µs µs µs ns ns ns µs No. 6018-6/35 LC74776, 74776M Figure 1 OSD Serial Data Input Timing S: Start condition P: Stop condition Figure 2 PDC/VPS Serial Timing (I2C bus) No. 6018-7/35 System Block Diagram Serial to parallel converter 8-bit latch + command decoder Data output buffer Horizontal character size register Vertical character size register Display control register RAM write address counter Output control Horizontal display position register Vertical display position register Blinking and reverse video control register AFC circuit Data slicer circuit Horizontal size counter Vertical size counter Horizontal dot counter Vertical dot counter Blinking and reverse video control circuit Decoder Display RAM LC74776, 74776M Horizontal display position detector Vertical display position detector Decoder Sync discrimination Character control counter Line control counter Font ROM Character output dot clock generator Timing generator Sync signal generator Character output control Background control Video output control Shift register Sync separator data separator circuit Composite sync signal separation control No. 6018-8/35 LC74776, 74776M Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. COMMAND0: Display memory (VRAM) write address setup command COMMAND1: Display character data write command COMMAND2: Vertical display start position and vertical character size setup command COMMAND3: Horizontal display start position and horizontal character size setup command COMMAND4: Display control setup command COMMAND5: Display control setup command COMMAND6: Synchronizing signal detection setup command COMMAND7 to COMMAND12 and COMMAND18: Display control setup commands COMMAND13 to COMMAND17: VPS/PDC control commands. These commands can only be written with the I2C bus (the SCL and SDA pins). Display Control Command Table First byte Command Command identification code 7 COMMAND0 (Write address setup) COMMAND1 (Character write) COMMAND2 (Vertical character size and vertical display start position) COMMAND3 (Horizontal character size and horizontal display start position) COMMAND4 (Display control) COMMAND5 (Display control) COMMAND6 (Synchronizing signal detection) COMMAND7 (Display control) COMMAND8 (Display control) COMMAND9 (Display control) COMMAND10 (Display control) COMMAND11 (Display control) COMMAND12 (Display control) COMMAND18 (Display control) COMMAND13 (VPS/PDC control) COMMAND14 (VPS/PDC control) COMMAND15 (VPS/PDC control) COMMAND16 (VPS/PDC control) COMMAND17 (VPS/PDC control) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 4 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 3 V3 0 VS 21 HS 21 2 V2 0 VS 20 HS 20 Data 1 V1 0 VS 11 HS 11 0 V0 0 VS 10 HS 10 7 0 at 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 c6 FS LC BLK 2 5 0 c5 VP 5 HP 5 BLK 1 Second byte Data 4 H4 c4 VP 4 HP 4 BLK 0 BCL RN 0 VNP SEL LNA 1 LNB 1 LNC 1 VSP SLC OTD S0 SJN 3 CPA 0 3 H3 c3 VP 3 HP 3 BK 1 CB SN 3 2 H2 c2 VP 2 HP 2 BK 0 PH 2 SN 2 1 H1 c1 VP 1 HP 1 RV PH 1 SN 1 0 H0 c0 VP 0 HP 0 DSP ON PH 0 SN 0 TST RAM OSC SYS MOD ERS STP RST NP 1 NP 0 NON DIS LIN 0 0 1 1 0 0 1 0 1 1 0 0 INT MUT 0 1 0 1 0 1 1 1 0 1 0 1 RSH HLF LV2 INT RN 2 CIN SEL LNA 3 LNB 3 RN 1 CIN CTL LNA 2 LNB 2 SEL MOD 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 1 1 1 0 0 VSP MSK MSK EGL SEL ERS SEL LNA LPA 0 2 LNB LPB 0 2 LNC LPC 0 2 LPA 1 LPB 1 LPC 1 LPA 0 LPB 0 LPC 0 LNC LNC 3 2 0 0 0 VSP DCK OTD S1 RNE 0 LNC MOD LNB MOD SEL 3 SEL 2 HLF INT SJN 2 SEL 2 SJN 1 OTH SJC 1 IND SJC 0 CPA CPA 2 1 VPM VPM VPM VPM 3 2 1 0 HBS BMS EMS DCE 1 ECV ECV 13 12 ECP ECP 16 15 ECP ECP 23 22 ECV ECV 11 5 ECP ECP 14 13 ECP ECP 21 20 VMW VMW HBS SE2 SEL 2 0 ECV 15 ECV 14 ECP 17 ECP 24 ECP ECP 19 18 0 ECP 25 Once written, a first byte command identification code is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74776/M locks into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the LC74776/M is set to the COMMAND0 (display memory write address setup mode) state. No. 6018-9/35 LC74776, 74776M COMMAND0 (Display memory write address setup command) • First byte DA 0 to 7 7 6 5 4 3 Register – – – – V3 Contents State 1 0 0 0 0 1 2 V2 0 1 1 V1 0 1 0 V0 0 1 Display memory line address (0 to B hexadecimal) Command 0 identification code. Display memory write address setup. Function Notes • Second byte DA 0 to 7 7 6 5 4 Register – – – H4 Contents State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory column address (0 to 17 hexadecimal) Function Second byte identification bit Notes 3 H3 2 H2 1 H1 0 H0 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. COMMAND1 (Display character data write setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 0 0 1 0 0 0 0 Command 1 identification code. Display character data write mode setup. Function Notes When this command is input, the LC74776/M locks in the display character data write mode until the CS pin goes high. No. 6018-10/35 LC74776, 74776M • Second byte DA 0 to 7 7 Register at Contents State 0 1 6 c6 0 1 5 c5 0 1 4 c4 0 1 3 c3 0 1 2 c2 0 1 1 c1 0 1 0 c0 0 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. (FEHEX: Space character) (FFHEX: Transparent space character) Character code (00 to FF hexadecimal) Function Character attribute off Character attribute on Notes COMMAND2: Vertical display start position and vertical character size setup command • First byte DA 0 to 7 7 6 5 4 3 Register – – – – VS21 Contents State 1 0 1 0 0 1 2 VS20 0 1 1 VS11 0 1 0 VS10 0 1 VS11 0 1 VS21 0 1 VS10 0 1H/dot 3H/dot 1 2H/dot 1H/dot VS20 0 1H/dot 3H/dot 1 2H/dot 1H/dot Function Command 2 identification code. Vertical display start position and the vertical character size setup. Notes Second line vertical character size First line vertical character size • Second byte DA 0 to 7 7 6 Register – FS VP5 (MSB) 4 VP4 Contents State 0 0 1 5 0 1 0 1 3 VP3 0 1 2 VP2 0 1 1 VP1 VP0 (LSB) 0 1 0 0 1 Character display area Function Second byte identification bit Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc If VS is the vertical display start position then: n VS = α +H × 2 ∑ 2 VPn Notes 5 n=0 H: The horizontal synchronization pulse period α = 20H (525H systems) α = 25H (625H systems) The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H. Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-11/35 LC74776, 74776M COMMAND3 (Horizontal display start position and horizontal size setup command) • First byte DA 0 to 7 7 6 5 4 3 Register – – – – HS21 Contents State 1 0 1 1 0 1 2 HS20 0 1 1 HS11 0 1 0 HS10 0 1 VS11 0 1 VS21 0 1 VS10 VS20 0 1Tc/dot 3Tc/dot 1 2Tc/dot 1Tc/dot Function Command 3 identification code. Horizontal display start position and the horizontal character size setup. Notes Second line horizontal character size 0 1Tc/dot 3Tc/dot 1 2Tc/dot 1Tc/dot First line horizontal character size • Second byte DA 0 to 7 7 6 Register – LC HP5 (MSB) 4 HP4 Contents State 0 0 1 5 0 1 0 1 3 HP3 0 1 2 HP2 0 1 1 HP1 HP0 (LSB) 0 1 0 0 1 Function Second byte identification bit Use the LC oscillator as the dot clock Use the crystal oscillator as the dot clock If HS is the horizontal start position then: HS = Tc × 5 2 ∑ 2 n HPn n=0 Notes Selects the dot clock used for character display in the horizontal direction. Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc. Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-12/35 LC74776, 74776M COMMAND4 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 Register – – – – TSTMOD Contents State 1 1 0 0 0 1 2 RAMERS 0 1 1 OSCSTP 0 1 0 0 SYSRST 1 Reset all registers and turn display off Erase display RAM.(The RAM data is set to FF hexadecimal.) Do not stop the crystal and LC oscillators Stop the crystal and LC oscillators Normal operating mode Test mode This bit must be set to 0 Erasing RAM takes about 500 µs. (This operation must be executed in the DSPOFF state.) Valid in external synchronization mode when character display is off The registers are reset when the CS pin is low, and the reset state is cleared when CS is set high. Command 4 identification code. Display character data write setup. Function Notes • Second byte DA 0 to 7 7 6 Register – BLK2 Contents State 0 0 1 5 BLK1 0 1 4 BLK0 0 1 3 BK1 0 1 2 BK0 0 1 1 RV 0 1 0 DSPON 0 1 BLK1 0 1 Function Second byte identification bit Character display area Video display area BLK0 0 Blanking off Frame size 1 Character size Complete fill in size Notes Specifies the size for complete fill in Changes the blanking size Blinking period: About 0.5 s Blinking period: About 1.0 s Blinking off Blinking on Reverse video off Reverse video on Character display off Character display on Switches the blinking period Blinking in character reverse video mode switches the display between normal character display and reverse video display Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-13/35 LC74776, 74776M COMMAND5 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 Register – – – – NP1 Contents State 1 1 0 1 0 1 2 NP0 0 1 1 NON 0 1 0 INT 0 1 NTSC PAL 525 lines 625 lines Interlaced Noninterlaced External synchronization Internal synchronization Switches between NTSC and PAL Command 5 identification code. Display control setup. Function Notes Modified by the external input signal V Switches between interlaced and noninterlaced video Switches between external and internal synchronization • Second byte DA 0 to 7 7 6 Register – RSHLV2 Contents State 0 0 1 5 HLFINT 0 1 4 BCL 0 1 3 CB 0 1 0 2 PH2 1 0 1 PH1 1 0 0 PH0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Function Second byte identification bit Background color level 1. (Level that is different from blue.) Background color level 2. (Level that is identical to the blue level.) Normal mode Partial internal synchronization mode Background color on No background color. (Only the background level is set.) Color burst signal output Color burst signal output stopped PH2 PH1 PH0 (phase) 0 1 0 1 0 1 0 1 Background color Cyan Yellow Red Blue Cyan - blue Green Orange Magenta Notes Switches the background color signal level Only valid in internal synchronization mode Only valid when BCL is high Background color specification Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-14/35 LC74776, 74776M COMMAND6 (Synchronizing signal detection setup command) • First byte DA 0 to 7 7 6 5 4 3 Register – – – – SEL0 Contents State 1 1 1 0 0 1 0 2 MOD0 1 0 1 0 MUT 0 1 SEL0 0 0 1 1 MOD0 0 1 0 1 SEPOUT DAV Sliced data width CSYNC ST pulse signal Function Notes Command 6 identification code. Synchronizing signal control setup. Switches the SEPOUT (pin 19) output 1 DISLIN 12 lines 10 lines Normal output CVIN is cut and CVOUT is held at the pedestal level Switches the number of lines displayed CVOUT switching • Second byte DA 0 to 7 7 6 Register – RN2 Contents State 0 0 1 5 RN1 0 1 4 RN0 0 1 3 SN3 0 1 2 SN2 0 1 1 SN1 0 1 0 SN0 0 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. SN3 0 0 0 0 1 SN2 0 0 0 1 0 SN1 0 0 1 0 0 SN0 0 1 0 0 0 Number of times HSYNC detected Not output 32 64 128 256 RN2 0 0 0 1 RN1 0 0 1 0 RN0 0 1 0 0 Number of times HSYNC detected 0 (32) 4 (64) 8 (128) 16 (256) Function Second byte identification bit Notes External synchronizing signal detection control. Signal absent → signal present transition detection. Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H). Values in parentheses apply when RNE0 (COM18) is 1. External synchronizing signal detection control. Signal present → signal absent transition detection. Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H). No. 6018-15/35 LC74776, 74776M COMMAND7 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 0 0 0 0 Extended command 0 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 6 CINSEL CINCTL Register Contents State 0 0 1 0 1 4 VNPSEL 0 1 3 VSPSEL 0 1 2 MSKERS 0 1 1 MSKSEL 0 1 0 EGL 0 1 Function Second byte identification bit Blank area (The logical OR of the character and frame signals) Video signal display area CVCR: off CVCR: on V falling edge detection V rising edge detection VSEP: about 8.9 µs (NTSC) VSEP: about 17.8 µs (NTSC) Mask valid Mask invalid 3H (NTSC) 20H (NTSC) Frame level 0 only (VBK0) Two-stage frame level (VBK0 and VBK1) CVCR on signal switching CVCR on/off switching Switches the V acquisition polarity in external mode when internal V separation is used. Switches the internal V separation period Notes 5 Clears the HSYNC and VSYNK masks Switches the VSYNC mask Switches the frame level. (Only valid when BLK0 is 0 and BLK1 is 1.) Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-16/35 LC74776, 74776M COMMAND8 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 0 0 0 1 Extended command 1 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 Register – Contents State 0 0 6 LNA3 1 0 5 LNA2 1 0 4 LNA1 1 0 3 LNA0 1 0 2 LPA2 1 0 1 LPA1 1 0 0 LPA0 1 Function Second byte identification bit LNA3 LNA2 LNA1 LNA0 0 0 0 0 0 0 0 0 1 1 1 1 1 LPA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 LPA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 – 0 1 0 1 0 1 0 1 0 1 0 1 – LPA0 0 1 0 1 0 1 0 1 Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Line background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta Notes Specifies the line whose background is to be changed. (When the background color is specified for the same line with LNA*, LNB*, and LNC*, the command specified last becomes valid. The previously specified registers (LN* and LP*) are all cleared to 0.) Specifies the background color Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-17/35 LC74776, 74776M COMMAND9 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 0 0 1 0 Extended command 2 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 Register – Contents State 0 0 6 LNB3 1 0 5 LNB2 1 0 4 LNB1 1 0 3 LNB0 1 0 2 LPB2 1 0 1 LPB1 1 0 0 LPB0 1 Function Second byte identification bit LNB3 LNB2 LNB1 LNB0 0 0 0 0 0 0 0 0 1 1 1 1 1 LPC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 LPC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 – 0 1 0 1 0 1 0 1 0 1 0 1 – LPC0 0 1 0 1 0 1 0 1 Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Line background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta Notes Specifies the line whose background is to be changed. (When the background color is specified for the same line with LNA*, LNB*, and LNC*, the command specified last becomes valid. The previously specified registers (LN* and LP*) are all cleared to 0.) Specifies the background color Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-18/35 LC74776, 74776M COMMAND10 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 0 0 1 1 Extended command 3 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 Register – Contents State 0 0 6 LNC3 1 0 5 LNC2 1 0 4 LNC1 1 0 3 LNC0 1 0 2 LPC2 1 0 1 LPC1 1 0 0 LPC0 1 Function Second byte identification bit LNB3 LNB2 LNB1 LNB0 0 0 0 0 0 0 0 0 1 1 1 1 1 LPB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 LPB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 – 0 1 0 1 0 1 0 1 0 1 0 1 – LPB0 0 1 0 1 0 1 0 1 Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Line background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta Notes Specifies the line whose background is to be changed. (When the background color is specified for the same line with LNA*, LNB*, and LNC*, the command specified last becomes valid. The previously specified registers (LN* and LP*) are all cleared to 0.) Specifies the background color Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-19/35 LC74776, 74776M COMMAND11 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 0 1 0 0 Extended command 4 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 6 5 Register – – VSPDCK Contents State 0 0 0 1 4 VSPSLC 0 1 0 3 LNCSEL 1 LC oscillator: operating LC oscillator: stopped VCO: operating VCO: stopped Normal line background color operation RV characters have the background color specified by PH* and the RV character background color is white The LNCSEL = 1 setting specifications RV characters have the background color specified by PH* and characters are white Normal line background color operation RV characters have the background color specified by PH* and the RV character background color is white The LNBSEL = 1 setting specifications RV characters have the background color specified by PH* and characters are white Valid when LNBSEL is high Switches the RV mode background color for RV specified characters in LNB* specified lines Valid when LNCSEL is high Switches the RV mode background color for RV specified characters in LNC* specified lines LC oscillator control Function Second byte identification bit Notes VCO control 0 2 MOD3 1 0 1 LNBSEL 1 0 0 MOD2 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-20/35 LC74776, 74776M COMMAND12 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 0 1 0 1 Extended command 5 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 6 5 Register – – OTDCS1 Contents State 0 0 0 1 4 OTDCS0 0 1 3 HLFTON 0 1 0 2 SEL2 1 0 1 0 IND3 0 1 OTDS1 0 0 1 SEL2 0 0 1 1 OTDS0 0 1 0 HLFTON 0 1 0 1 Dot clock LC oscillator Crystal oscillator VCO Output SYNCJDG Halftone LOCK SYNCDET Function Second byte identification bit Notes External synchronization mode dot clock setting SYNCJDG pin (pin 8) output switching. The halftone output line specification depends on background color specification (the logical OR of the 3-line specification). 1 OTHS CSYNCB (sync separator) HDB (slicer AFC) LC oscillator Crystal oscillator External synchronization mode H input switching Internal synchronization mode dot clock setup Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-21/35 LC74776, 74776M COMMAND18 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 1 0 1 1 Extended command B identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 6 Register – – Contents State 0 0 0 5 RNE0 1 0 4 SJNS3 1 0 3 SJNS2 1 0 2 SJNS1 1 1 SJCS1 0 1 0 1 Sync discrimination signal absent → present: normal value Sync discrimination signal absent → present: value shown in parentheses SJNS3 0 0 0 0 1 1 1 1 SJCS1 0 0 1 SJNS2 0 0 1 1 0 0 1 1 SJCS0 0 1 0 SJNS1 0 1 0 1 0 1 0 1 PAL 677 ns (1/3) 903 ns (1/4) 450 ns (1/2) Number of times None 4 8 16 32 64 128 256 NTSC 558 ns (1/2) 838 ns (1/3) 1117 ns (1/4) Function Second byte identification bit Notes Changes the discrimination value for the sync discrimination signal absent → present transition Setting for the noise rejection circuit used for sync discrimination signal absent → present transition. The sync signal absent state is recognized when the number of high-level signals shown in the table is input during a 1H period. Sync discrimination. HSYNI signal extraction clock selection. 0 SJCS0 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-22/35 LC74776, 74776M COMMAND13 (VPS/PDC control setup command) I2C bus only • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 0 1 0 1 Extended command 5 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 6 Register – CPA2 Contents State 0 0 1 5 CPA1 0 1 4 CPA0 0 1 0 3 VPM3 1 0 2 VPM2 1 0 1 VPM1 1 0 0 VPM0 1 Function Second byte identification bit CPA2 0 0 0 0 1 1 1 1 M3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 M2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CPA1 0 0 1 1 0 0 1 1 M1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPA0 0 1 0 1 0 1 0 1 Clock No. 1 No. 2 No. 3 No. 4 No. 5 No. 6 No. 7 No. 8 Notes Data acquisition clock selection. Shifts in multiples of 8 clock units with respect to the data. Operating mode VPS 8/30/2 (PDC) Automatic PDC/VPS discrimination 1 8/30/1 (UDT) Header time 1 Header time 2 Header time 3 Header time 4 Status display 1 Status display 2 Status display 3 Status display 4 PAL Pulse Automatic PDC/VPS discrimination 2 Automatic PDC/VPS discrimination 3 Automatic PDC/VPS discrimination 4 Slicer mode selection Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-23/35 LC74776, 74776M COMMAND14 (VPS/PDC control setup command) I2C bus only • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 0 1 1 0 Extended command 6 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 6 Register – VMWSE2 Contents State 0 0 1 5 VMWSEL 0 1 4 HBS2 0 1 3 HBS1 0 1 0 2 BMS 1 0 1 EMS 1 Function Second byte identification bit V mask period start - From the retrace period V mask period start - From 10H before the retrace period The V mask period is the retrace period The V mask period is 9H Clock running discrimination 1 (2 times) Clock running discrimination 2 (4 times) Framing code discrimination 1 Framing code discrimination 2 (Single bad bits are ignored) Error check valid (Error checking can be turned on or off on a per-byte basis.) CPOUT pin (pin 13) V mask period switching 2 Notes CPOUT pin (pin 13) V mask period switching Clock running discrimination count setting Framing code discrimination selection When set to 0, if there are no errors in bytes for which error checking is turned on, those bytes are written to P-S. When set to 1, all Error check invalid (Applications can select whether data for bytes are written to P-S regardless of the error which an error is detected is held or writing on a per-byte basis.) status. Data hold Data write (When the error bit is 0 in VPS mode.) Specifies handling of bytes for which error checking is set to off but in which an error occurred when error checking is turned on 0 Error checking enabled for unused data bytes. VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12, header 1: bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14 to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35 0 DCE 1 Error checking disabled for unused data bytes. VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12, header 1: bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14 to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35 Error checking setting for unused data bytes. Biphase (VPS), Hamming (PDC), and odd parity (header) Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-24/35 LC74776, 74776M COMMAND15 (VPS/PDC control setup command) I2C bus only • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 0 1 1 1 Extended command 7 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 6 5 Register – – ECV15 Contents State 0 0 0 1 4 ECV14 0 1 3 ECV13 0 1 2 ECV12 0 1 1 ECV11 0 1 0 ECV5 0 1 Byte 15 biphase error check on (Data hold) Byte 15 biphase error check off (Data write) Byte 14 biphase error check on (Data hold) Byte 14 biphase error check off (Data write) Byte 13 biphase error check on (Data hold) Byte 13 biphase error check off (Data write) Byte 12 biphase error check on (Data hold) Byte 12 biphase error check off (Data write) Byte 11 biphase error check on (Data hold) Byte 11 biphase error check off (Data write) Byte 5 biphase error check on (Data hold) Byte 5 biphase error check off (Data write) Specification when the VPS data BMS bit is 0. The item in parentheses is the specification when the VPS data BMS bit is 1. Function Second byte identification bit Notes Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-25/35 LC74776, 74776M COMMAND16 (VPS/PDC control setup command) I2C bus only • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 1 0 0 0 Extended command 8 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 Register – Contents State 0 0 6 ECP19 1 Function Second byte identification bit Byte 19 Hamming error check on (Data hold) {Bytes 44, 28, 36, 20, 32, 42, 32, and 42} Byte 19 Hamming error check off (Data write) {Bytes 44, 28, 36, 20, 32, 42, 32, and 42} Byte 18 Hamming error check on (Data hold) {Bytes 43, 27, 35, 19, 31, 41, 31, and 41} Byte 18 Hamming error check off (Data write) {Bytes 43, 27, 35, 19, 31, 41, 31, and 41} Byte 17 Hamming error check on (Data hold) {Bytes 42, 26, 34, 18, 30, 40, 30, and 40} Byte 17 Hamming error check off (Data write) {Bytes 42, 26, 34, 18, 30, 40, 30, and 40} Byte 16 Hamming error check on (Data hold) {Bytes 41, 25, 33, 17, 29, 39, 29, and 39} Byte 16 Hamming error check off (Data write) {Bytes 41, 25, 33, 17, 29, 39, 29, and 39} Byte 15 Hamming error check on (Data hold) {Bytes 40, 24, 32, 16, 28, 38, 28, and 38} Byte 15 Hamming error check off (Data write) {Bytes 40, 24, 32, 16, 28, 38, 28, and 38} Byte 14 Hamming error check on (Data hold) {Bytes 39, 23, 31, 15, 27, 37, 27, and 37} Byte 14 Hamming error check off (Data write) {Bytes 39, 23, 31, 15, 27, 37, 27, and 37} Byte 13 Hamming error check on (Data hold) {Bytes 38, 22, 30, 14, 26, 36, 26, and 36} Byte 13 Hamming error check off (Data write) {Bytes 38, 22, 30, 14, 26, 36, 26, and 36} Specification when the PDC data BMS bit is 0. The item in parentheses is the specification when the BMS bit is 1. The item in curly braces lists the odd parity check on/off bytes for header modes 1, 2, 3, and 4 and status mode 1, 2, 3, and 4. Notes 0 5 ECP18 1 0 4 ECP17 1 0 3 ECP16 1 0 2 ECP15 1 0 1 ECP14 1 0 0 ECP13 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-26/35 LC74776, 74776M COMMAND17 (VPS/PDC control setup command) I2C bus only • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register – – – – – – – – Contents State 1 1 1 1 1 0 0 1 Extended command 9 identification code Command 7 identification code. Display control setup. Function Notes • Second byte DA 0 to 7 7 6 Register – – Contents State 0 0 0 5 ECP25 1 Byte 25 Hamming error check off (Data write) Byte 25 Hamming error check on (Data hold) Specification when the PDC data BMS bit is 0. The item in parentheses is the specification when the BMS bit is 1. The item in curly braces lists the odd parity check on/off bytes for header modes 1, 2, 3, and 4 and status mode 1, 2, 3, and 4. Function Second byte identification bit Notes 0 4 ECP24 1 Byte 24 Hamming error check on (Data hold) Byte 24 Hamming error check off (Data write) 0 3 ECP23 1 Byte 23 Hamming error check on (Data hold) Byte 23 Hamming error check off (Data write) Byte 22 Hamming error check on (Data hold) {Bytes , , , , 35, 45, 35, and 45} Byte 22 Hamming error check off (Data write) {Bytes , , , , 35, 45, 35, and 45} Byte 21 Hamming error check on (Data hold) {Bytes , , , , 34, 44, 34, and 44} Byte 21 Hamming error check off (Data write) {Bytes , , , , 34, 44, 34, and 44} Byte 20 Hamming error check on (Data hold) {Bytes 45, 29, 37, 21, 33, 43, 33, and 43} Byte 20 Hamming error check off (Data write) {Bytes 45, 29, 37, 21, 33, 43, 33, and 43} 0 2 ECP22 1 0 1 ECP21 1 0 0 ECP20 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. No. 6018-27/35 LC74776, 74776M PDC/VPS Output Data Format Data is output in order starting with bit 7 of byte 1. Output data Format 1 Byte 1 Bit 7 6 5 4 3 2 1 0 Byte 2 Bit 7 6 5 4 3 2 1 0 Byte 3 Bit 7 6 5 4 3 2 1 0 Byte 4 Bit 7 6 5 4 3 2 1 0 Byte 5 Bit 7 6 5 4 3 2 1 0 Byte 6 Bit 7 6 5 4 3 2 1 0 byte 20 byte 19 byte 18 byte 17 byte 16 byte 15 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 25 byte 24 byte 15 byte 14 byte 23 byte 22 byte 21 byte 20 byte19 byte 18 byte17 PDC 8/30 mode Format 2 byte 16 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 byte 15 byte 5 byte 14 byte 13 byte 12 byte 11 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 43 (35) byte 42 (34) byte 41 (33) byte 40 (32) byte 39 (31) byte 38 (30) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 27 (19) byte 26 (18) byte 25 (17) byte 24 (16) byte 23 (15) byte 22 (14) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 VPS mode Header time mode 1 (3) Header time mode 2 (4) Continued on next page. No. 6018-28/35 LC74776, 74776M Continued from preceding page. Output data Byte 7 Bit 7 6 5 4 3 2 1 0 Byte 8 Bit 7 6 5 4 3 2 1 0 Byte 9 Bit 7 6 5 4 3 2 1 0 Byte 10 Bit 7 6 5 4 3 2 1 0 Byte 11 Bit 7 6 5 4 3 2 1 0 Byte 12 Bit 7 6 5 4 3 2 1 0 Byte 13 Bit 7 6 5 4 3 2 1 0 byte 25 byte 24 byte 23 byte 22 byte 14 byte 13 byte 21 PDC 8/30 mode Format 1 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 0 0 0 Error information 2 1 1 1 1 Error byte 16 information 1 17 18 19 20 21 22 23 14 15 24 25 13 0 0 Format 2 byte 13 bit 0 1 2 3 1 1 1 1 1 1 1 0 Error byte 11 information 12 13 14 5 15 byte 45 (37) byte 44 (36) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 Error byte 38 (30) information 39 (31) 40 (32) 41 (33) 42 (34) 43 (35) 44 (36) 45 (37) byte 29 (21) byte 28 (20) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 Error byte 22 (14) information 23 (15) 24 (16) 25 (17) 26 (18) 27 (19) 28 (20) 29 (21) VPS mode Header time mode 1 (3) Header time mode 2 (4) Note: A value of 1 is output for section with no output data setting. No. 6018-29/35 LC74776, 74776M Data is output in order starting with bit 7 of byte 1. Status display 1 and 2: 8/30/2 - Status display 1 and 2: 8/30/1 Output data Byte 1 Bit 7 6 5 4 3 2 1 0 Byte 2 Bit 7 6 5 4 3 2 1 0 Byte 3 Bit 7 6 5 4 3 2 1 0 Byte 4 Bit 7 6 5 4 3 2 1 0 Byte 5 Bit 7 6 5 4 3 2 1 0 Byte 6 Bit 7 6 5 4 3 2 1 0 Byte 7 Bit 7 6 5 4 3 2 1 0 byte 32 (32) byte 31 (31) byte 30 (30) byte 29 (29) byte 28 (28) byte 27 (27) Status display mode 1 (3) Status display mode 2 (4) byte 26 (26) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 42 (42) byte 41 (41) byte 39 (40) byte 39 (39) byte 38 (38) byte 37 (37) byte 36 (36) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 PAL Puls bit 0 1 2 3 4 5 6 7 bit 8 9 10 11 12 13 0 0 Continued on next page. No. 6018-30/35 LC74776, 74776M Continued from preceding page. Output data Byte 8 Bit 7 6 5 4 3 2 1 0 Byte 9 Bit 7 6 5 4 3 2 1 0 Byte 10 Bit 7 6 5 4 3 2 1 0 Byte 11 Bit 7 6 5 4 3 2 1 0 Byte 12 Bit 7 6 5 4 3 2 1 0 Byte 13 Bit 7 6 5 4 3 2 1 0 Note: A value of 1 is output for section with no output data setting. byte 35 (35) byte 34 (34) Status display mode 1 (3) byte 33 (33) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 Error byte 26 (26) information 1 27 (27) 28 (28) 29 (29) 30 (30) 31 (31) 32 (32) 33 (33) Error byte 34 (34) information 2 35 (35) 0 0 0 0 0 0 byte 45 (45) byte 44 (44) Status display mode 2 (4) byte 43 (43) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 Error byte 36 (36) information 1 37 (37) 38 (38) 39 (39) 40 (40) 41 (41) 42 (42) 43 (43) Error byte 44 (44) information 1 45 (45) 0 0 0 0 0 0 PAL Puls No. 6018-31/35 LC74776, 74776M Display Screen Structure The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced from the 288 maximum when enlarged characters are displayed. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses) 24 Characters 12 Rows No. 6018-32/35 LC74776, 74776M Composite Video Signal Output Levels (internally generated levels) CVOUT output level waveform (VDD2 = 5.00 V) (1) (2) (3) Output level VCHA VRSH0 VRSH1, 2 VCBH VRSL0 VRSL1 VRSL2 VBK1 VBK0 VPD VCBL VSN : Character : Background colors other than blue: high : Blue background colors 1 and 2: high : Color burst high : Background colors other than blue: low : Blue background color 1: low : Blue background color 2: low : Frame 1 : Frame 2 : Pedestal : Color burst low : Sync Output voltage (1) [V] 2.65 2.37 2.01 1.67 1.23 1.16 1.52 2.08 1.50 1.37 1.07 0.80 Output voltage (2) [V] 2.85 2.57 2.21 1.87 1.43 1.36 1.72 2.28 1.70 1.57 1.27 1.00 Output voltage (3) [V] 3.25 2.97 2.61 2.27 1.83 1.76 2.12 2.68 2.10 1.97 1.67 1.40 No. 6018-33/35 LC74776, 74776M Application Circuit Examples (When used connected to a single-chip Y/C circuit) • External system clock input Microcontroller • Crystal oscillator Microcontroller No. 6018-34/35 LC74776, 74776M • External system clock input (with pins 3 and 4 modified in the mask options) Microcontroller The electrolytic capacitor connected to SYNIN must be connected with the correct polarity when a sync tip level of 1.4 VDC (CVIN input signal: sync tip = 1.4 V) is selected in the options for video signals generated with internal synchronization. When VDD1 is 5.0 V, the SYNIN input video signal pedestal level will be clamped to about 2.5 V. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of Februaly, 1999. Specifications and information herein are subject to change without notice. PS No. 6018-35/35