LC74789JM

Ordering number : EN5732A CMOS IC LC74789, 74789M, 74789JM On-Screen Display Controller Overview The LC74789, LC74789M, and LC74789JM are onscreen display controller CMOS ICs that display characters and patterns on the TV screen under microprocessor control. These ICs support 12 × 18 dot characters and can display 12 lines by 24 characters of text. Package Dimensions unit: mm 3067-DIP24S [LC74789] Features • Display format: 24 characters by 12 rows (Up to 288 characters) • Character format: 12 (horizontal) × 18 (vertical) dots • Character sizes: Three sizes each in the horizontal and vertical directions • Characters in font: 256 (254 characters, one spacing character, and one transparent spacing character) • Initial display positions: 64 horizontal positions and 64 vertical positions • Blinking: Specifiable in character units • Blinking types: Two periods supported: About 1.0 second and about 0.5 second • Blanking: Over the whole font (12 × 18 dots) • Background color: 8 colors (internal synchronization mode): 2fSC and 4fSC • Line background color — Can be set for 3 lines — Line background color: 8 colors (internal synchronization mode): 2fSC and 4fSC • External control input: 8-bit serial input format • On-chip sync separator circuit • Video outputs: NTSC, PAL, PAL-N, PAL-M, NTSC 4.43, and PAL60 format composite video outputs • Package — 24-pin plastic DIP-24S (300 mil) — 24-pin plastic MFP-24 (375 mil) — 24-pin plastic MFP-24S (300 mil) SANYO: DIP24S unit: mm 3045B-MFP24 [LC74789M] SANYO: MFP24 unit: mm 3112-MFP24S [LC74789JM] SANYO: MFP24S SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 30698HA (OT) No. 5732-1/23 LC74789, 74789M, 74789JM Pin Assignment A08696 Pin Functions Pin No. 1 2 Pin Name VSS1 XtalIN XtalOUT (MUTE) Crystal oscillator (MUTE input) Function Ground Ground connection (digital system ground) These pins are used either to connect the crystal and capacitors used to form an external crystal oscillator circuit to generate the internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pullup resistor is built in and the input has hysteresis characteristics.) Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character · frame) output. This is a 3-value output. Outputs the range signal specified by LNA*, LNB*, and LNC*. Outputs the crystal oscillator clock when RST is low. (This signal is not output after a reset command is executed.) Connections for the inductor and capacitor that form the character output dot clock generation oscillator Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs the dot clock (LC oscillator) when RST is low. (This signal is not output on command resets.) Serial data input circuit enable pin. Serial data input is enabled when a low level is input. A pull-up resistor is built in. (This input has hysteresis characteristics.) Serial data input circuit clock input. A pull-up resistor is built in. (This input has hysteresis characteristics.) Serial data input. A pull-up resistor is built in. (This input has hysteresis characteristics.) Composite video signal level adjustment power supply (analog system power supply) Notes 3 4 CTRL1 (CHABLK) Crystal oscillator input switching (CHABLK output) 5 6 7 HFTONOUT OSCIN OSCOUT Background line output LC oscillator 8 SYNCJDG External synchronizing signal judgment output 9 10 11 12 CS SCLK SIN VDD2 Enable input Clock input Data input Power supply Continued on next page. No. 5732-2/23 LC74789, 74789M, 74789JM Continued from preceding page. Pin No. 13 14 15 16 17 18 Pin Name CVOUT VSS2 CVIN CVCR VDD1 SYNIN Function Video signal output Ground Video signal input Video signal input Power supply Sync separator circuit input Sync separator circuit bias voltage Composite synchronizing signal output Composite video signal output Ground connection (analog system ground) Composite video signal input SECAM chrominance signal input Power supply (+5 V: digital system power supply) Video signal input to the internal sync separator circuit (Used as either the horizontal synchronizing signal or the composite synchronizing signal input when the internal sync separator circuit is not used.) Internal sync separator circuit bias voltage monitor Internal sync separator circuit composite synchronizing signal output. Can be switched to function as a signal (high, low, or ST. pulse) output by the SEL0 and MOD0 setting. Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output signal. An integration circuit must be connected to the SEPOUT pin. This pin must be tied to VDD1 if unused. This pin can be switched to function as the frame signal input mode by setting SEL1 high. This is valid when CTL3 is set high. This input has hysteresis characteristics. Background color phase adjustment. Connect a resistor between this pin and ground. System reset input. A pull-up resistor is built in and the input has hysteresis characteristics. Power supply (+5 V: digital system power supply) Notes 19 20 SEPC SEPOUT 21 SEPIN Vertical synchronizing signal input 22 23 24 CDLR RST VDD1 Background color phase adjustment Reset input Power supply (+5 V) Note: Both VDD1 pins must be connected to the power supply. No. 5732-3/23 LC74789, 74789M, 74789JM Specifications Absolute Maximum Ratings Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Topr Tstg VDD1 and VDD2 All input pins HFTONOUT, SYNCJDG, and SEPOUT Ta = 25°C Conditions Ratings VSS–0.3 to VSS+6.5 VSS–0.3 to VDD+0.3 VSS–0.3 to VDD+0.3 350 –30 to +70 –40 to +125 Unit V V V mW °C °C Allowable Operating Ranges Parameter Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 RPU VIN1 Composite video signal input voltage VIN2 VIN3 Input voltage VIN4 VDD1 VDD2 RST, CS, SIN, SCLK, SEPIN, and MUTE CTRL1 RST, CS, SIN, SCLK, SEPIN, and MUTE CTRL1 RST, CS, SIN, SCLK, and MUTE Applies to pins set up by options. CVIN: VDD1 = 5 V SYNIN: VDD1 = 5 V CVCR: VDD1 = 5 V XtalIN (when used for external clock input) fIN = 2fsc or 4fsc ; VDD1 = 5 V XtalIN and XtalOUT oscillator pins (2fsc: NTSC) XtalIN and XtalOUT oscillator pins (4fsc: NTSC) XtalIN and XtalOUT oscillator pins (2fsc: PAL) Oscillator frequencies FOSC1 XtalIN and XtalOUT oscillator pins (4fsc: PAL) XtalIN and XtalOUT oscillator pins (2fsc: PAL-M) XtalIN and XtalOUT oscillator pins (4fsc: PAL-M) XtalIN and XtalOUT oscillator pins (2fsc: PAL-N) XtalIN and XtalOUT oscillator pins (4fsc: PAL-N) FOSC2 OSCIN and OSCOUT oscillator pins (LC oscillator) 5 0.10 7.159 14.318 8.867 17.734 7.151 14.302 7.164 14.328 10 Conditions Ratings min 4.5 4.5 0.8 VDD1 0.7 VDD1 VSS – 0.3 VSS – 0.3 25 50 2.0 2.0 2.0 5.0 2.5 typ 5.0 5.0 max 5.5 1.27 VDD1 VDD1+0.3 VDD+0.3 0.2 VDD1 0.3 VDD1 90 Unit V V V V V V kΩ Vp-p Vp-p Vp-p Vp-p MHz MHz MHz MHz MHz MHz MHz MHz MHz Supply voltage Input high-level voltage Input low-level voltage Pull-up resistance Note: Applications must be especially cautious about noise when using the XtalIN input pin in clock input mode. No. 5732-4/23 LC74789, 74789M, 74789JM Electrical Characteristics at Ta = –30 to +70°C. VDD1 = 5 V unless otherwise specified. Parameter Input off leakage current Output off leakage current Output high-level voltage Output low-level voltage Symbol Ileak1 Ileak2 VOH1 VOL1 CVIN and CVCR CVOUT HFTONOUT, SYNCJDG, and SEPOUT HFTONOUT, SYNCJDG, and SEPOUT VDD1 = 4.5 V, IOH = –1.0 mA VDD1 = 4.5 V, IOL = –1.0 mA H Three-value output voltage VO CHABLK VDD1 = 5.0 V M L IIH IIL IDD1 IDD2 SYNC level VSN RST, CS, SIN, SCLK, CTRL1, SEPIN, and MUTE CTRL1 and OSCIN VDD1 VDD2 VIN = VDD1 VIN = VSS1 All outputs: open Xtal:7.159 MHz LC:8 MHz VDD2 = 5 V (1) (2) (3) (1) Pedestal level VPD (2) (3) (1) Color burst low level VCBL (2) (3) (1) Color burst high level VCBH (2) (3) (1) Background color low level (other than blue) VRSL0 (2) (3) (1) Background color high level (other than blue) VRSH0 CVOUT (1): When the sync level = 0.8 V (2): When the sync level = 1.0 V Blue background 1 low level VRSL1 (3): When the sync level = 1.3 V (2) VDD1 = 5.0 V (3) VDD2 = 5.0 V (1) (2) (3) (1) Blue background 2 low level VRSL2 (2) (3) (1) Blue background 1 and 2 high level VRSH1, 2 (2) (3) (1) Frame level 0 VBK0 (2) (3) (1) Frame level 1 VBK1 (2) (3) (1) Character level VCHA (2) (3) Note: Blue background 1 or 2 are option settings. 0.70 0.89 1.18 1.32 1.52 1.81 0.98 1.17 1.46 1.63 1.83 2.11 1.17 1.36 1.65 2.33 2.52 2.81 1.08 1.27 1.56 1.49 1.68 1.97 1.97 2.17 2.46 1.40 1.60 1.89 1.97 2.17 2.46 2.55 2.75 3.04 0.82 1.01 1.30 1.44 1.64 1.93 1.10 1.29 1.58 1.75 1.95 2.23 1.29 1.48 1.77 2.45 2.64 2.93 1.20 1.39 1.68 1.61 1.80 2.09 2.09 2.29 2.58 1.52 1.72 2.01 2.09 2.29 2.58 2.67 2.87 3.16 –1 15 20 0.94 1.13 1.42 1.56 1.76 2.05 1.22 1.41 1.70 1.87 2.07 2.35 1.41 1.60 1.89 2.57 2.76 3.05 1.32 1.51 1.80 1.83 1.92 2.21 2.21 2.41 2.70 1.64 1.84 2.13 2.21 2.41 2.70 2.79 2.99 3.28 V V V V V V V V V V V V 3.3 1.8 0 3.5 1.0 5.0 2.3 0.8 1 Pin Conditions Ratings min typ max 1 1 Unit µA µA V V V V V µA µA mA mA Input current Operating mode current drain No. 5732-5/23 LC74789, 74789M, 74789JM Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V Parameter Minimum input pulse width Symbol tW(SCLK) tW(CS) Data setup time tSU(CS) tSU(SIN) Data hold time th(CS) th(SIN) One word write time tword twt SCLK CS (The period when CS is high) CS SIN CS SIN The time to write 8 bits of data The RAM data write time Conditions Ratings min 200 1 200 200 2 200 4.2 1 typ max Unit ns µs ns ns µs ns µs µs Serial Data Input Timing First byte Second byte A08697 No. 5732-6/23 System Block Diagram Serial to parallel converter 8-bit latch + command decode Horizontal character size register Vertical character size register Vertical display position register Horizontal display position register Blinking and reverse control register Display control register RAM write address counter Horizontal size counter Vertical size counter Horizontal dot counter Vertical dot counter Blinking and reverse control circuit Decoder Display RAM Horizontal display position detector Vertical display position detector Decoder LC74789, 74789M, 74789JM Synchronization determination Character control counter Line control counter Font ROM Character output dot clock generator Timing generator Sync separator Composite sync signal separation control Sync signal generator Character output control Background control Video output control Shift register A08698 No. 5732-7/23 LC74789, 74789M, 74789JM Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. 1 2 3 4 5 6 7 8 9 10 11 COMMAND0: COMMAND1: COMMAND2: COMMAND3: COMMAND4: COMMAND5: COMMAND6: COMMAND7: COMMAND8: COMMAND9: COMMAND10: Display memory (VRAM) write address setup command Display character data write command Vertical display start position and vertical character size setup command Horizontal display start position and horizontal character size setup command Display control setup command Display control setup command Synchronizing signal detection setup command Display control setup command Display control setup command Display control setup command Display control setup command Display Control Command Table First byte Command Command identification code 7 COMMAND0 Write address setup COMMAND1 Character write COMMAND2 Vertical character size and vertical display start position COMMAND3 Horizontal character size and horizontal display start position COMMAND4 Display control COMMAND5 Display control COMMAND6 Synchronizing signal detection COMMAND7 Display control COMMAND8 Display control COMMAND9 Display control COMMAND10 Display control 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 0 VS 21 HS 21 TST MOD NP 1 SEL 0 0 VS 20 HS 20 RAM ERS NP 0 MOD 0 0 DIS LIN SEL 1 VSY SEL LNB SEL LNC SEL CTL 3 HSY SEL MOD 2 MOD 3 0 0 0 0 MUT 0 VS 11 HS 11 OSC STP NON VS 10 HS 10 SYS RST INT 0 0 FS VP 5 HP 5 BLK 1 HLF INT RN 1 CIN CTL LNA 2 LNB 2 LNC 2 RN 0 VNP SEL LNA 1 LNB 1 LNC 1 SN 3 VSP SEL LNA 0 LNB 0 LNC 0 VP 4 HP 4 BLK 0 BCL VP 3 HP 3 BK 1 CB VP 2 HP 2 BK 0 PH 2 SN 2 MSK ERS LPA 2 LPB 2 LPC 2 PH 1 SN 1 MSK SEL LPA 1 LPB 1 LPC 1 LPA 0 LPB 0 LPC 0 VP 1 HP 1 RV VP 0 HP 0 DSP ON PH 0 SN 0 EGL 1 0 0 1 0 0 0 at c7 c6 c5 c4 c3 c2 c1 c0 1 6 0 5 0 4 0 3 V3 Data 2 V2 1 V1 0 V0 7 0 6 0 5 0 4 H4 Second byte Data 3 H3 2 H2 1 H1 0 H0 1 0 1 1 0 LC 1 1 0 0 0 BLK 2 NP 2 RN 2 CIN SEL LNA 3 LNB 3 LNC 3 Once written, a first byte command identification code is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74789/M/JM locks into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the LC74789/M/JM is set to the COMMAND0 (display memory write address setup mode) state. No. 5732-8/23 LC74789, 74789M, 74789JM COMMAND0 (Display memory write address setup command) • First byte DA 0 to 7 7 6 5 4 3 Register — — — — V3 State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory line address (0 to B hexadecimal) Command 0 identification code. Sets the display memory write address. Contents Function Notes 2 V2 1 V1 0 V0 • Second byte DA 0 to 7 7 6 5 4 Register — — — H4 State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory column address (0 to 17 hexadecimal) Contents Function Second byte identification code Notes 3 H3 2 H2 1 H1 0 H0 Note: All registers are set to 0 when the LC74789/M/JM is reset by the RST pin. No. 5732-9/23 LC74789, 74789M, 74789JM COMMAND1 (Display character data write setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 0 Register — — — — — — — at State 1 0 0 1 0 0 0 0 1 Character attribute off Character attribute on Command 1 identification code. Sets up display character data write mode. When this command is input, the LC74789/M/JM locks in the display character data write mode until the CS pin goes high. Contents Function Notes • Second byte DA 0 to 7 7 Register c7 State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (FE (hex): spacing character) (FF (hex): transparent spacing character) Character code (00 to FF hexadecimal) Contents Function Notes 6 c6 5 c5 4 c4 3 c3 2 c2 1 c1 0 c0 Note: All registers are set to 0 when the LC74789/M/JM is reset by the RST pin. No. 5732-10/23 LC74789, 74789M, 74789JM COMMAND2: Vertical display start position and vertical character size setup command • First byte DA 0 to 7 7 6 5 4 3 Register — — — — VS21 State 1 0 1 0 0 1 0 1 0 1 0 1 VS11 0 1 VS21 0 1 VS10 VS20 0 1H/dot 3H/dot 0 1H/dot 3H/dot 1 2H/dot 1H/dot 1 2H/dot 1H/dot First line vertical character size Second line vertical character size Command 2 identification code. Sets the vertical display start position and the vertical character size. Contents Function Notes 2 VS20 1 VS11 0 VS10 • Second byte DA 0 to 7 7 6 Register — FS VP5 (MSB) VP4 State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character display area Second byte identification bit Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc If VS is the vertical display start position then: VS = α + H × (2Σ 2n VPn) n=0 5 Contents Function Notes 5 4 H: the horizontal synchronization pulse period α = 20 H (in 525-line systems) = 25 H (in 625-line systems) The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H. 3 VP3 2 VP2 1 VP1 VP0 (LSB) 0 Note: All registers are set to 0 when the LC74789/M/JM is reset by the RST pin. No. 5732-11/23 LC74789, 74789M, 74789JM COMMAND3 (Horizontal display start position and horizontal size setup command) • First byte DA 0 to 7 7 6 5 4 3 Register — — — — HS21 State 1 0 1 1 0 1 0 1 0 1 0 1 HS11 0 1 HS21 0 1 HS10 HS20 0 1 Tc/dot 3 Tc/dot 0 1 Tc/dot 3 Tc/dot 1 2 Tc/dot 1 Tc/dot 1 2 Tc/dot 1 Tc/dot First line horizontal character size Second line horizontal character size Command 3 identification code. Sets the horizontal display start position and the horizontal character size. Contents Function Notes 2 HS20 1 HS11 0 HS10 • Second byte DA 0 to 7 7 6 Register — LC HP5 (MSB) HP4 State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc. Second byte identification bit Use the LC oscillator for the dot clock Use the crystal oscillator for the dot clock If HS is the horizontal start position then: HS =Tc × (2Σ 2n HPn) n=0 5 Contents Function Notes Selects the dot clock used for character display in the horizontal direction. 5 4 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. 3 HP3 2 HP2 1 HP1 HP0 (LSB) 0 Note: All registers are set to 0 when the LC74789/M/JM is reset by the RST pin. No. 5732-12/23 LC74789, 74789M, 74789JM COMMAND4 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 Register — — — — TSTMOD State 1 1 0 0 0 1 0 1 0 1 0 1 Reset all registers and turn display off. Erase display RAM. (The RAM data is set to FF hexadecimal.) Do not stop the crystal and LC oscillators. Stop the crystal and LC oscillators. Normal operating mode Test mode This bit must be set to 0. Erasing RAM takes about 500 µs. (This operation must be executed in the DSPOFF state.) Valid in external synchronization mode when character display is off. The registers are reset when the CS pin is low, and the reset state is cleared when CS is set high. Command 4 identification code Display character data write setup Contents Function Notes 2 RAMERS 1 OSCSTP 0 SYSRST • Second byte DA 0 to 7 7 6 Register — BLK2 State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BLK1 0 1 Blinking period: About 0.5 s Blinking period: About 1.0 s Blinking off Blinking on Reverse video off Reverse video on Character display off Character display on Second byte identification bit Character display area Video display area BLK0 0 Blanking off Frame size 1 Character size Complete fill in Switches the blinking period Blinking in reverse video mode switches the display between normal character display and reverse video display. Changes the blanking size Specifies the size for complete fill in Contents Function Notes 5 BLK1 4 BLK0 3 BK1 2 BK0 1 RV 0 DSPON Note: All registers are set to 0 when the LC74789/M/JM is reset by the RST pin. No. 5732-13/23 LC74789, 74789M, 74789JM COMMAND5 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 Register — — — — State 1 1 0 1 0 3 NP1 1 0 2 NP0 1 0 1 0 1 NP2 0 0 0 0 1 1 Interlaced Noninterlaced External synchronization Internal synchronization NP1 0 0 1 1 0 0 NP0 0 1 0 1 0 1 Format NTSC PAL-M PAL PAL-N NTSC4.43 PAL60 Switches between interlaced and noninterlaced video. Switches between external and internal synchronization Switches between the NTSC, PAL, PAL-N, PAL-M, NTSC 4.43, and PAL60 formats. Command 5 identification code. Display control setup. Contents Function Notes 1 NON 0 INT • Second byte DA 0 to 7 7 6 Register — NP2 State 0 0 1 0 1 0 1 0 1 0 2 PH2 1 0 1 PH1 1 0 0 PH0 1 Normal mode Half internal synchronization mode Background color on No background color (Only the background level is set) Color burst signal output. Color burst signal output stopped. Only valid in internal synchronization mode. Second byte identification bit Set with NP0 and NP1. Contents Function Notes 5 HLFINT 4 BCL 3 CB Only valid when BCL is high. PH2 0 0 0 0 1 1 1 1 PH1 0 0 1 1 0 0 1 1 PH0 0 1 0 1 0 1 0 1 Background color (phase) Cyan Yellow Red Blue Cyan blue Green Orange Magenta Background color specification Note: All registers are set to 0 when the LC74786/M/JM is reset by the RST pin. No. 5732-14/23 LC74789, 74789M, 74789JM COMMAND6 (Synchronizing signal detection setup command) • First byte DA 0 to 7 7 6 5 4 Register — — — — State 1 1 1 0 0 3 SEL0 1 0 2 MOD0 1 0 1 0 1 12 lines 10 lines Normal output CVIN is cut and CVOUT is held at the pedestal level. SEL0 0 0 1 1 MOD 0 1 0 1 SEPOUT output Sync separator signal Low-level output High-level output ST pulse signal Switches the SEPOUT (pin 19) output. Command 6 identification code. Sets up synchronizing signal control. Contents Function Notes 1 DISLIN Switches the number of lines displayed. 0 MUT CVOUT switching • Second byte DA 0 to 7 7 6 Register — RN2 State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SN3 0 0 0 0 1 SN2 0 0 0 1 0 SN1 0 0 1 0 0 SN0 0 1 0 0 0 Number of times HSYNC detected Not detected 32 times 64 times 128 times 256 times External synchronizing signal detection control Signal present → signal absent transition detection Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H). RN2 0 0 0 1 RN1 0 0 1 0 RN0 0 1 0 0 Number of times HSYNC detected 0 times 4 times 8 times 16 times External synchronizing signal detection control Signal absent → signal present transition detection Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H). Second byte identification bit Contents Function Notes 5 RN1 4 RN0 3 SN3 2 SN2 1 SN1 0 SN0 Note: All registers are set to 0 when the LC74789/M/JM is reset by the RST pin. No. 5732-15/23 LC74789, 74789M, 74789JM COMMAND7 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 1 Register — — — — — — SEL1 State 1 1 1 1 0 0 0 1 0 1 Extended command 0 identification code Vertical synchronizing signal (external V separation) input Frame signal input Use internal V separation Do not use internal V separation Switches the SEPIN (pin 20) input. Only valid when CTL3 is high. Switches V separation. Command 7 identification code. Display control setup. Contents Function Notes 0 CTL3 • Second byte DA 0 to 7 7 6 Register — CINSEL State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Second byte identification bit Blanking area (The logical OR of the character and frame signals) Video signal display area CVCR: off CVCR: on V falling edge detection V rising edge detection VSEP: about 8.9 µs (for NTSC) VSEP: about 17.8 µs (for NTSC) Mask valid Mask invalid 3H (for NTSC) 20H (for NTSC) Frame level 0 only (VBK0) CVCR on signal switching CVCR on/off setting Switches the V acquisition polarity in external mode when internal V separation is used. Switches the internal V separation period. Contents Function Notes 5 CINCTL 4 VNPSEL 3 VSPSEL 2 MSKERS Clears the HSYNC and VSYNC masks. 1 MSKSEL Switches the VSYNC mask. Switches the frame level. 0 EGL Note: All registers are set to 0 when the LC74786/M/JM is reset by the RST pin. No. 5732-16/23 LC74789, 74789M, 74789JM COMMAND8 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 Register — — — — — — State 1 1 1 1 0 1 0 1 VSYSEL 1 Positive polarity Extended command 1 identification code Command 8 identification code. Display control setup. Contents Function Notes Negative polarity SEPIN input polarity switching. Only valid when CTL3 is high. 0 0 HSYSEL 1 Negative polarity Positive polarity SYNIN (only valid when the sync separator circuit is not used) and SEPOUT input and output polarity switching • Second byte DA 0 to 7 7 Register — State 0 0 6 LNA3 1 0 5 LNA2 1 0 4 LNA1 1 0 3 LNA0 1 0 2 LPA2 1 0 1 LPA1 1 0 0 LPA0 1 Note: All registers are set to 0 when the LC74789/M/JM is reset by the RST pin. LPA2 0 0 0 0 1 1 1 1 LPA1 0 0 1 1 0 0 1 1 LPA0 0 1 0 1 0 1 0 1 Line background color (phase) Cyan Yellow Red Blue Cyan blue Green Orange Magenta Specifies the background color. Second byte identification bit LNA3 0 0 0 0 0 0 0 0 1 1 1 1 1 LNA2 0 0 0 0 1 1 1 1 0 0 0 0 1 LNA1 0 0 1 1 0 0 1 1 0 0 1 1 — LNA0 0 1 0 1 0 1 0 1 0 1 0 1 — Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed. (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specified registers (LN* and LP*) will all be reset to 0.) Contents Function Notes No. 5732-17/23 LC74789, 74789M, 74789JM COMMAND9 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 Register — — — — — — State 1 1 1 1 1 0 0 1 LNBSEL 1 0 0 MOD2 1 Extended command 2 identification code Normal line background color operation RV characters have the background color specified by PH* or the RV character background color is white. The LNBSEL: 1 setting specifications RV characters have the background color specified by PH*, characters are white. Valid when LNBSEL is high Switches the RV mode background color for the line specified by LNB* for characters specified for RV display Command 9 identification code. Display control setup. Contents Function Notes • Second byte DA 0 to 7 7 Register — State 0 0 6 LNB3 1 0 5 LNB2 1 0 4 LNB1 1 0 3 LNB0 1 0 2 LPB2 1 0 1 LPB1 1 0 0 LPB0 1 Note: All registers are set to 0 when the LC74789/M/JM is reset by the RST pin. LPB2 0 0 0 0 1 1 1 1 LPB1 0 0 1 1 0 0 1 1 LPB0 0 1 0 1 0 1 0 1 Line background color (phase) Cyan Yellow Red Blue Cyan blue Green Orange Magenta Specifies the background color Second byte identification bit LNB3 0 0 0 0 0 0 0 0 1 1 1 1 1 LNB2 0 0 0 0 1 1 1 1 0 0 0 0 1 LNB1 0 0 1 1 0 0 1 1 0 0 1 1 — LNB0 0 1 0 1 0 1 0 1 0 1 0 1 — Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 ZSpecifies the line whose background is to be changed. (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specified registers (LN* and LP*) will all be reset to 0.) Contents Function Notes No. 5732-18/23 LC74789, 74789M, 74789JM COMMAND10 (Display control setup command) • First byte DA 0 to 7 7 6 5 4 3 2 Register — — — — — — State 1 1 1 1 1 1 0 1 LNCSEL 1 0 0 MOD3 1 Extended command 3 identification code Normal line background color operation RV characters have the background color specified by PH* or the RV character background color is white The LNCSEL: 1 setting specifications RV characters have the background color specified by PH*, characters are white Valid when LNCSEL is high Switches the RV mode background color for the line specified by LNC* for characters specified for RV display Command 10 identification code. Display control setup. Contents Function Notes • Second byte DA 0 to 7 7 Register — State 0 0 6 LNC3 1 0 5 LNC2 1 0 4 LNC1 1 0 3 LNC0 1 0 2 LPC2 1 0 1 LPC1 1 0 0 LPC0 1 Note: All registers are set to 0 when the LC74789/M/JM is reset by the RST pin. LPC2 0 0 0 0 1 1 1 1 LPC1 0 0 1 1 0 0 1 1 LPC0 0 1 0 1 0 1 0 1 Line background color (phase) Cyan Yellow Red Blue Cyan blue Green Orange Magenta Specifies the background color Second byte identification bit LNC3 0 0 0 0 0 0 0 0 1 1 1 1 1 LNC2 0 0 0 0 1 1 1 1 0 0 0 0 1 LNC1 0 0 1 1 0 0 1 1 0 0 1 1 — LNC0 0 1 0 1 0 1 0 1 0 1 0 1 — Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed. (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specified registers (LN* and LP*) will all be reset to 0.) Contents Function Notes No. 5732-19/23 LC74789, 74789M, 74789JM Display Screen Structure The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced when enlarged characters are displayed. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses) 24 Characters 12 Rows A08699 No. 5732-20/23 LC74789, 74789M, 74789JM Composite Video Signal Output Levels (internally generated levels) CVOUT output level waveform (VDD2 = 5.0 V) Output level VCHA : Character VRH0 : Background color (other than blue) high VRSH1, 2 : Blue background color 1 and 2 high VBk1 : Frame 1 VCBH : Color burst high VRSL2 : Blue background color 2 low VBK0 : Frame 0 VPD : Pedestal VRSL0 : Background color (other than blue) low VRSL1 : Blue background color 1 low VCBL : Color burst low VSN : Sync Output voltage (1) [V] 2.67 2.45 2.09 2.09 1.75 1.61 1.52 1.44 1.29 1.20 1.10 0.82 Output voltage (2) [V] 2.87 2.64 2.29 2.29 1.95 1.80 1.72 1.64 1.48 1.39 1.29 1.01 Output voltage (3) [V] 3.16 2.93 2.58 2.58 2.23 2.09 2.01 1.93 1.77 1.68 1.58 1.30 No. 5732-21/23 LC74789, 74789M, 74789JM Sample Application Circuits (When the LC74789/M/JM is used in conjunction with a single-chip Y/C circuit.) • Circuit Using an External System Clock Input Microcontroller A08701 • Circuit Using a Crystal Oscillator Microcontroller A08702 PS No. 5732-22/23 LC74789, LC74789M, LC74789JM • Circuit Using an External System Clock Input (when the pin 3 and 4 functions are modified by mask options) Microcontroller A08703 Note: When a sync tip level of 1.3 V DC (CVIN input signal: sync tip = 1.3 V) is selected for the internal generated video signals by option settings, the electrolytic capacitor connected to SYNIN must be connected with the correct polarity. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice. PS No. 5732-23/23