LC749402BG

Ordering number : ENA1618 CMOS IC LC749402BG Overview Silicon gate LCD Picture Quality Improvement IC LC749402BG is a picture quality improvement IC that processes the output signals to the LCD panel for high picture quality display. This IC performs various picture quality adjustments to provide the ideal correction for the display panel. It can support up to WVGA/SVGA panels. * Features (1) Digital input/output • Digital YCbCr/YPbPr 24bit (4:4:4) or 16bit (4:2:2) or 8bit(ITU-R BT.656) signal input • Digital RGB 24bit signal input • Digital RGB 18bit/24bit signal output • Digital YCbCr16bit (4:2:2)/24bit (4:4:4) signal output (2) Image quality correction • Y image quality correction: luminance adjustment, contour correction, CDEX (Color Depth Expander), dynamic-γ, black/white stretch • C image quality correction: color exciter, flesh tone correction, hue, color gain • RGB image quality correction: brightness, contrast, white balance, black balance, γ correction (3) Panel interface • Built-in panel driver timing controller • Panel protection timing signal generation • Backlight control PWM (video adaptive low power consumption processing) *: The LC749402BG video input should satisfy the following conditions: 40MHz or less operating frequency, 896 dots or less horizontal size, 768 lines or less vertical size. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 12710HKIM 20091026-S00005 No.A1618-1/11 LC749402BG LSI Specifications • Supply voltage Core: 1.2V I/O: 1.8V/2.85V/3.3V • Maximum operating frequency: 40MHz • Package: FBGA96 Principal Applications • LCD display equipment CDEX (Color Depth Expander) Original CDEX Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS_OSC = 0V Parameter Maximum supply voltage (I/O) Maximum supply voltage (core) Symbol DVDD_IO DVDD_CORE AVDD_OSC Digital input voltage Digital output voltage Operating temperature Storage temperature VI VO Topr Tstg Conditions Ratings -0.3 to +3.96 -0.3 to +1.8 -0.3 to DVDD_IO+0.3 -0.3 to DVDD_IO+0.3 -40 to +85 -55 to +125 Unit V V V V °C °C Allowable Operating Ranges at Ta = -40 to +85°C, DVSS = 0V, AVSS_OSC = 0V Ratings Parameter Supply voltage (I/O) Symbol DVDD_IO Conditions min 2.6 1.7 Supply voltage (I/O) DVDD_CORE AVDD_OSC Input voltage range VIN 1.0 0 typ 2.85 1.8 1.2 max 3.6 1.9 1.3 DVDD_IO V V V V unit No.A1618-2/11 LC749402BG DC Characteristics at Ta = -40 to +85°C, DVSS = 0V, AVSS_OSC = 0V, DVDD_IO = 1.7V to 1.9V or 2.6V to 3.6V, DVDD_CORE = 1.0V to 1.3V Parameter Input high-level voltage Symbol VIH Conditions min CMOS level inputs CMOS level Schmitt inputs Input low-level voltage VIL CMOS level inputs CMOS level Schmitt inputs Input high-level current IIH VI=DVDD_IO VI=DVDD_IO, with pull-down resistance Input low-level current Output high-level voltage IIL VOH VI=DVSS CMOS voltage: 2.6V to 3.6V Pin D: IOH=-2mA Pin F: IOH=-2mA (when set to 2mA) IOH=-4mA (when set to 4mA) Pin G: IOH=-4mA (when set to 4mA) IOH=-8mA (when set to 8mA) Pin H: IOH=-4mA CMOS voltage: 1.7V to 1.9V Pin D: IOH=-1mA Pin F: IOH=-1mA (when set to 2mA) IOH=-2mA (when set to 4mA) Pin G: IOH=-2mA (when set to 4mA) IOH=-4mA (when set to 8mA) Pin H: IOH=-2mA Output low-level voltage Output leak current Pull-down resistor VOL IOZ RDN CMOS At output of high-impedance Typical conditions: Ta=25°C DVDD_IO=2.85V Dynamic supply current IDDOP DVDD_CORE=1.2V Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V tck=10MHz 10 steps Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V tck=40MHz 10 steps Static supply current *1 IDDST Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V Outputs open VI=DVSS or DVDD_IO 20 μA 57 mA 18 mA 98 kΩ -10 0.4 10 V μA DVDD_IO-0.45 V DVDD_IO-0.4 V -10 0.7DVDD_IO 0.7DVDD_IO 0.3DVDD_IO 0.3DVDD_IO 10 100 Ratings typ max V V V V μA μA μA unit *1: There is a input terminal which builds in pull down resistance. Please note that there is no guarantee about static consumption current depending on circuit composition. No.A1618-3/11 LC749402BG Package Dimensions FBGA96 unit:mm (typ) 3387 TOP VIEW 6.0 SIDE VIEW 0.5 BOTTOM VIEW 0.75 1 2 3 4 5 6 7 8 9 10 6.0 0.5 0.75 K J H GF E D C B A SIDE VIEW 0.1 1.05 MAX 0.29 SANYO : ISB96(6.0X6.0) Pin Assignment LC749402BG 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K Top view No.A1618-4/11 DCBIN[7:0] DVSI DCRIN[7:0] DYGIN[7:0] DDEI DCKI DHSI XRST Color Space Convert Timing controller Color Depth Expander Panel protection CTI HUE LTI Horizontal contour FTI Color Gain W/BL stretch Dynamic γ Oscillator Block Diagram OSDBL TEST XTALI SCK_SCL delay SRXD_SDA I²C/SIO STXD SCS_I2SEL SIOSEL PDWN INTO LC749402BG LC749402BG MPU BLCON PWM POL CPV PWM STRB SP DEXR Color Exciter Color Space Convert White/black balance Brightness/contrast RGB γ OSD Mix Dither TCON Bypass OE FLM GRST DVSO DCKO DDEO DHSO DCBOUT[7:0] DYGOUT[7:0] DCROUT[7:0] No.A1618-5/11 LC749402BG Pin Functions Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Pin symbol AVDD_OSC STXD SCK_SCL DBOUT7 DBOUT4 DBOUT1 DGOUT6 DGOUT4 DGOUT3 DVDD_IO RC_BIAS AVDD_OSC SRXD_SDA PWM DBOUT5 DBOUT2 DGOUT7 DGOUT5 DVDD_IO DGOUT2 DCRIN0 DCRIN1 AVSS_OSC INTO DBOUT6 DBOUT3 DBOUT0 DVDD_IO DGOUT1 DGOUT0 DCRIN2 DCRIN3 DCRIN4 TEST XRST DVDD_IO DVDD_IO DROUT7 DROUT6 DROUT5 In/output format I/O P O I O O O O O O P I P I/O O O O O O P O I I P O O O O P O O I I I I I P P O O O Format D C F F F F F F J H D F F F F F C C D F F F F F C C C B A F F F Connecting destination Core voltage CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS IO voltage resistor Core voltage CMOS CMOS CMOS CMOS CMOS CMOS IO voltage CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS IO voltage CMOS CMOS CMOS CMOS CMOS CMOS CMOS IO voltage IO voltage CMOS CMOS CMOS Analog Digital Digital Digital Digital Digital Digital Digital Digital Digital Analog Analog Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Analog Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital R/Cr video (MSB) R/Cr video R/Cr video G/Y video G/Y video (8-bit output mode, LSB) R/Cr video. Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. Test (Normally, connect this pin to GND) System reset (“L” reset) Interrupt B/Cb/C video B/Cb/C video B/Cb/C video (8-bit output mode, LSB) G/Y video (6-bit output mode, LSB) R/Cr video. Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. SIO data input/I2C data I/O Pulse width modulation waveform B/Cb/C video B/Cb/C video (6-bit output mode, LSB) G/Y video (MSB) G/Y video Remarks Connect this pin to B2 without fail. SIO data Bus clock (common to SIO and I2C) B/Cb/C video (MSB) B/Cb/C video B/Cb/C video G/Y video G/Y video G/Y video Connect this pin to B9 without fail Bias resistor connection (Connect this pin to GND with a 20kΩ) Continued on next page. No.A1618-6/11 LC749402BG Continued from preceding page. Pin No. E1 E2 E3 E4 E7 E8 E9 E10 F1 F2 F3 F4 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 Pin symbol DCRIN5 DCRIN6 DCRIN7 DVSS PDWN DROUT4 DROUT3 DROUT2 DYGIN0 DYGIN1 DYGIN2 DVSS DVDD_CORE DROUT1 DROUT0 DCKO DYGIN3 DYGIN4 DYGIN5 DVSS SCS_I2SEL SIOSEL DVDD_CORE DHSO/SP2 DVSO/FLM2 DDEO DYGIN6 DYGIN7 DVSS DCBIN6 DVSI OSDBL FLM DVDD_CORE DEXR POL In/output format I/O I I I P I O O O I I I P P O O O I I I P I I P O O O I I P I I I O P O O Format C C C A F F F C C C F F G C C C A C F F F C C C C C F F F CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS CMOS CMOS GND Core voltage CMOS CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS Core voltage CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS Core voltage CMOS CMOS Digital Digital Digital Digital Digital Digital Digital Reversed video signal output for DTR. Low output when the DTR is OFF. Voltage polarity selection signal for source driver B/Cb/C video. Connect this pin to GND when not to be used. Vertical synchronizing signal Data enable signal for external OSD. Connect this pin to GND when not to be used. Start pulse signal for gate driver Connecting destination Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Horizontal synchronizing signal/start pulse signal for source driver Vertical synchronizing signal/start pulse signal for gate driver Data enable signal G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video (MSB). Connect this pin to GND when not to be used. SIO chip enable/I2C slave address switching “L”: I2C slave, ”H”: 4-wire SIO R/Cr video R/Cr video (8-bit output mode, LSB) Video clock G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. “H” power down. Connect this pin to GND when not to be used. R/Cr video R/Cr video R/Cr video (6-bit output mode, LSB) G/Y/656 video (LSB). Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. Remarks R/Cr video. Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. R/Cr video (MSB). Connect this pin to GND when not to be used. Continued on next page. No.A1618-7/11 LC749402BG Continued from preceding page. Pin No. J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 Pin symbol DCBIN0 DVSS DCBIN3 DCBIN5 DDEI DHSI GRST CPV DVDD_CORE SP DVSS DCBIN1 DCBIN2 DCBIN4 DCBIN7 DCKI XTAL1 OE STRB DVDD_CORE In/output format I/O I P I I I I O O P O P I I I I I I O O P Format C C C C C F F F C C C C C C F F CMOS GND CMOS CMOS CMOS CMOS CMOS CMOS Core voltage CMOS GND CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Core voltage Connecting destination Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Analog Digital Digital Digital Digital Digital Digital Digital Digital Digital Start pulse signal for source driver Connect this pin to J2 without fail B/Cb/C video. Connect this pin to GND when not to be used. B/Cb/C video. Connect this pin to GND when not to be used. B/Cb/C video. Connect this pin to GND when not to be used. B/Cb/C video (MSB). Connect this pin to GND when not to be used. Video clock Panel protection, PWM generation clock. Connect this pin to GND when not to be used. Output enable signal for gate driver Data strobe signal for source driver Connect this pin to J9 without fail B/Cb/C video. Connect this pin to GND when not to be used. B/Cb/C video. Connect this pin to GND when not to be used. Data enable signal, Connect this pin to GND in the internal generation mode Horizontal synchronizing signal Reset signal for gate driver Clock signal for gate driver Remarks B/Cb/C video (LSB). Connect to GND when not to be used. No.A1618-8/11 LC749402BG Pin Type In/Output form Function Schmitt trigger CMOS input A Equivalent circuit Application Terminal XRST, PDWN, SCS_I2SEL CMOS input with built-in pull-down resistor B TEST CMOS input SCK_SCL, SIOSEL, DVSI, DHSI, DDEI, OSDBL, DYGIN7, DYGIN6, DYGIN5, DYGIN4, DYGIN3, DYGIN2, DYGIN1, DYGIN0, DCBIN7, DCBIN6, DCBIN5, DCBIN4, DCBIN3, DCBIN2, DCBIN1, DCBIN0, DCRIN7, DCRIN6, DCRIN5, DCRIN4, DCRIN3, DCRIN2, DCRIN1, DCRIN0 C 2mA 3-STATE drive CMOS output D STXD, PWM, INTO 2mA/4mA switching 3-STATE drive CMOS output F DBOUT7, DBOUT6, DBOUT5, DBOUT4, DBOUT3, DBOUT2, DBOUT1, DBOUT0, DROUT7, DROUT6, DROUT5, DROUT4, DROUT3, DROUT2, DROUT1, DROUT0 DGOUT7, DGOUT6, DGOUT5, DGOUT4, DGOUT3, DGOUT2, DGOUT1, DGOUT0, DHSO/SP2, DVSO/FLM2, DDEO FLM, DEXR, POL, GRST, CPV, SP, OE, STRB 4mA/8mA switching 3-STATE drive CMOS output G DCKO 4mA 3-STATE drive CMOS input/output SRXD_SDA H Analog input/output J RC_BIAS No.A1618-9/11 LC749402BG I/O Timing (1) Input data timing tHI DCKI tSU tHD tLI tCK DVDD_IO/2 Input data DVDD_IO/2 Pin name DCKI Clock cycle Duty Parameter Symbol tCK min 25 typ max unit ns 50 tSU tSU tHD tHD 3 3 2 % ns ns ns Input data setup time (DVDD_IO=2.6 to 3.6V) DCRIN*, DYGIN*, DCBIN*, DVSI, DHSI, DDEI, OSDBL Input data setup time (DVDD_IO=1.7 to 1.9V) Input data hold time (DVDD_IO=2.6 to 3.6V) Input data hold time (DVDD_IO=1.7 to 1.9V) 2 ns *: The recommended duty cycle of input clock is 50% (2) Output data timing tHO tCK DVDD_IO/2 DCKO tAC tLO Output data DVDD_IO/2 Pin name DCKO Clock cycle Duty Parameter Symbol tCK min 25 typ max unit ns 50 % Output data delay time (DVDD_IO=2.6 to 3.6V) Pin F: when set to 4mA Pin G: when set to 8mA Output data delay time (DVDD_IO=2.6 to 3.6V) DROUT*, DGOUT*, DBOUT*, DVSO, DHSO, DDEO, DEXR, POL, SP, STRB, CPV, OE, FLM, GRST Pin F: when set to 2mA Pin G: when set to 4mA Output data delay time (DVDD_IO=1.7 to 1.9V) Pin F: when set to 4mA Pin G: when set to 8mA Output data delay time (DVDD_IO=1.7 to 1.9V) Pin F: when set to 2mA Pin G: when set to 4mA tAC -6 9 ns tAC -5 4 ns tAC -3 6 ns tAC -3 3 ns * When DCKO is set to the forward rotation output. Output load capacity: 5pF No.A1618-10/11 LC749402BG SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2010. Specifications and information herein are subject to change without notice. PS No.A1618-11/11