LC749402PT

Ordering number : ENA1885 CMOS IC LC749402PT Overview Silicon gate LCD Picture Quality Improvement IC LC749402PT is a picture quality improvement IC that processes the output signals to the LCD panel for high picture quality display. This IC performs various picture quality adjustments to provide the ideal correction for the display panel. It can support up to WVGA/SVGA panels. * Features (1) Digital input/output • Digital YCbCr/YPbPr 24bit (4:4:4) or 16bit (4:2:2) or 8bit (ITU-R BT.656) signal input • Digital RGB 24bit signal input • Digital RGB 18bit/24bit signal output • Digital YCbCr 16bit (4:2:2)/24bit (4:4:4) signal output (2) Image quality correction • Y image quality correction: luminance adjustment, contour correction, CDEX (Color Depth Expander), dynamic-γ, black/white stretch • C image quality correction: color exciter, flesh tone correction, hue, color gain • RGB image quality correction: brightness, contrast, white balance, black balance, γ correction (3) Panel interface • Built-in panel driver timing controller • Panel protection timing signal generation • Backlight control PWM (video adaptive low power consumption processing) *: The LC749402PT video input should satisfy the following conditions: 40MHz or less operating frequency, 896 dots or less horizontal size, 768 lines or less vertical size. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. 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D0810HKIM 20101117-S00004 No.A1885-1/10 LC749402PT LSI Specifications • Supply voltage Core: 1.2V I/O: 1.8V/2.85V/3.3V • Maximum operating frequency: 40MHz • Package: TQFP100 Principal Applications • LCD display equipment CDEX (Color Depth Expander) Original CDEX Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS_OSC = 0V Parameter Maximum supply voltage (I/O) Maximum supply voltage (core) Symbol DVDD_IO DVDD_CORE AVDD_OSC VI VO Topr Tstg Conditions Ratings -0.3 to +3.96 -0.3 to +1.8 -0.3 to DVDD_IO+0.3 -0.3 to DVDD_IO+0.3 -40 to +85 -55 to +125 Unit V V V V °C °C Digital input voltage Digital output voltage Operating temperature Storage temperature Allowable Operating Ranges at Ta = -40 to +85°C, DVSS = 0V, AVSS_OSC = 0V Ratings Parameter Supply voltage (I/O) Symbol DVDD_IO Conditions min 2.6 1.7 Supply voltage (core) DVDD_CORE AVDD_OSC Input voltage range VIN 1.1 0 typ 2.85 1.8 1.2 max 3.6 1.9 1.3 DVDD_IO V V V V unit No.A1885-2/10 LC749402PT DC Characteristics at Ta = -40 to +85°C, DVSS = 0V, AVSS_OSC = 0V, DVDD_IO = 1.7V to 1.9V or 2.6V to 3.6V, DVDD_CORE = 1.1V to 1.3V Parameter Input high-level voltage Symbol VIH Conditions min CMOS level inputs CMOS level schmitt inputs Input low-level voltage VIL CMOS level inputs CMOS level schmitt inputs Input high-level current IIH VI=DVDD_IO VI=DVDD_IO, with pull-down resistance Input low-level current Output high-level voltage IIL VOH VI=DVSS CMOS voltage: 2.6V to 3.6V Pin D: IOH=-2mA Pin F: IOH=-2mA (when set to 2mA) IOH=-4mA (when set to 4mA) Pin G: IOH=-4mA (when set to 4mA) IOH=-8mA (when set to 8mA) Pin H: IOH=-4mA CMOS voltage: 1.7V to 1.9V Pin D: IOH=-1mA Pin F: IOH=-1mA (when set to 2mA) IOH=-2mA (when set to 4mA) Pin G: IOH=-2mA (when set to 4mA) IOH=-4mA (when set to 8mA) Pin H: IOH=-2mA Output low-level voltage Output leak current Pull-down resistor VOL IOZ RDN CMOS At output of high-impedance Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V Dynamic supply current IDDOP Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V tck=10MHz 10 steps Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V tck=40MHz 10 steps Static supply current *1 IDDST Typical conditions: Ta=25°C DVDD_IO=2.85V DVDD_CORE=1.2V Outputs open VI=DVSS or DVDD_IO 20 μA 57 mA 18 mA 98 kΩ -10 0.4 10 V μA DVDD_IO-0.45 V DVDD_IO-0.4 V -10 0.7DVDD_IO 0.7DVDD_IO 0.3DVDD_IO 0.3DVDD_IO 10 100 Ratings typ max V V V V μA μA μA unit *1: There is a input terminal which builds in pull down resistance. Please note that there is no guarantee about static consumption current depending on circuit composition. No.A1885-3/10 LC749402PT Package Dimensions unit:mm (typ) 3274 16.0 14.0 75 76 51 50 100 1 (1.0) (1.0) 26 0.5 0.2 25 0.125 1.2max 0.1 SANYO : TQFP100(14X14) Pin Assignment 95 90 85 AVDD_OSC RC_BIAS AVSS_OSC DVSS DCRIN0 DCRIN1 DCRIN2 DCRIN3 DCRIN4 DVDD_CORE DCRIN5 DCRIN6 DCRIN7 DYGIN0 DYGIN1 DVDD_IO DYGIN2 DYGIN3 DYGIN4 DYGIN5 DYGIN6 DVSS DYGIN7 DCBIN0 DCBIN1 100 80 DVDD_IO STXD SRXD_SDA SCK_SCL DVSS TEST INTO XRST DVDD_CORE PWM DBOUT7 DBOUT6 DBOUT5 DVSS DBOUT4 DBOUT3 DBOUT2 DVDD_IO DBOUT1 DBOUT0 DGOUT7 DVSS DGOUT6 DGOUT5 DGOUT4 14.0 16.0 0.5 75 5 70 10 LC749402PT 15 65 60 20 55 25 30 35 40 45 50 DGOUT3 DGOUT2 DGOUT1 DVDD_IO DGOUT0 DROUT7 DROUT6 DVSS DROUT5 DROUT4 DROUT3 DVDD_CORE DROUT2 DROUT1 DROUT0 PDWN DVSS DCKO DVDD_IO DHSO/SP2 DVSO/FLM2 DDEO DVSS DEXR POL DCBIN2 DCBIN3 DCBIN4 DCBIN5 DVDD_CORE DCBIN6 DCBIN7 DDEI DVSI DHSI DVSS OSDBL SCS_I2SEL DCKI SIOSEL XTAL1 DVDD_IO GRST FLM OE DVSS CPV STRB SP DVDD_CORE Top view No.A1885-4/10 DVSI DCBIN[7:0] DCRIN[7:0] DDEI DCKI DHSI XRST Color Space Convert Timing Controller Color Depth Expander Panel Protection CTI HUE LTI Horizontal Contour FTI Color Gain W/BL stretch Dynamic γ Oscillator DYGIN[7:0] Block Diagram OSDBL TEST XTALI SCK_SCL SRXD_SDA I²C/SIO STXD SCS_I2SEL SIOSEL PDWN INTO Delay LC749402PT LC749402PT MPU BL Control PWM POL CPV PWM STRB SP DEXR Color Exciter Color Space Convert White/Black Balance Brightness/Contrast RGB γ OSD Mix Dither TCON Bypass OE FLM GRST DVSO DCKO DDEO DHSO DCBOUT[7:0] DYGOUT[7:0] DCROUT[7:0] No.A1885-5/10 LC749402PT Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Pin symbol AVDD_OSC RC_BIAS AVSS_OSC DVSS DCRIN0 DCRIN1 DCRIN2 DCRIN3 DCRIN4 DVDD_CORE DCRIN5 DCRIN6 DCRIN7 DYGIN0 DYGIN1 DVDD_IO DYGIN2 DYGIN3 DYGIN4 DYGIN5 DYGIN6 DVSS DYGIN7 DCBIN0 DCBIN1 DCBIN2 DCBIN3 DCBIN4 DCBIN5 DVDD_CORE DCBIN6 DCBIN7 DDEI DVSI DHSI DVSS OSDBL SCS_I2SEL DCKI SIOSEL XTAL1 DVDD_IO GRST FLM OE DVSS CPV STRB SP In/output format I/O P I P P I I I I I P I I I I I P I I I I I P I I I I I I I P I I I I I P I I I I I P O O O P O O O Format J C C C C C C C C C C C C C C C C C C C C C C C C C C C C A C C C F F F F F F Connecting destination Core Voltage Resistor GND GND CMOS CMOS CMOS CMOS CMOS Core Voltage CMOS CMOS CMOS CMOS CMOS IO voltage CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS CMOS CMOS Core Voltage CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS IO voltage CMOS CMOS CMOS GND CMOS CMOS CMOS Analog Analog Analog Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Gate driver clock signal. Data strobe signal for source driver. Start pulse signal for sourse driver. Gate driver reset signal. Start pulse signal for gate driver Output enable signal for gate driver. Data enable signal for external OSD. (Connect to GND when not used.) SIO chip enable / I2C slave select Video clock. ”L”: I2C slave, ”H”: 4 wire SIO Extarnal clock input for panel protection. (Connect to GND when not used.) B/Cb/C video input (Connect to GND when not used.) B/Cb/C video input (MSB Connect to GND when not used.) Data enable signal. (Connect to GND when not used.) Vertical sync signal Horizontal sync signal. G/Y/656 video input (MSB Connect to GND when not used.) B/Cb/C video (LSB Connect to GND when not used.) B/Cb/C video input (Connect to GND when not used.) B/Cb/C video input (Connect to GND when not used.) B/Cb/C video input (Connect to GND when not used.) B/Cb/C video input (Connect to GND when not used.) B/Cb/C video input (Connect to GND when not used.) G/Y/656 video input (Connect to GND when not used.) G/Y/656 video input (Connect to GND when not used.) G/Y/656 video input (Connect to GND when not used.) G/Y/656 video input (Connect to GND when not used.) G/Y/656 video input (Connect to GND when not used.) R/Cr video input (Connect to GND when not used.) R/Cr video input (Connect to GND when not used.) R/Cr video input (MSB Connect to GND when not used.) G/Y/656 video input (LSB Connect to GND when not used.) G/Y/656 video input (Connect to GND when not used.) R/Cr video input. (LSB Connect to GND when not used.) R/Cr video input. (Connect to GND when not used.) R/Cr video input (Connect to GND when not used.) R/Cr video input (Connect to GND when not used.) R/Cr video input (Connect to GND when not used.) Bias resistor connection (Connect to ground through 20kΩ resistor) Remarks Continued on next page. No.A1885-6/10 LC749402PT Continued from preceding page. Pin No. 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin symbol DVDD_CORE POL DEXR DVSS DDEO DVSO / FLM2 DHSO / SP2 DVDD_IO DCKO DVSS PDWN DROUT0 DROUT1 DROUT2 DVDD_CORE DROUT3 DROUT4 DROUT5 DVSS DROUT6 DROUT7 DGOUT0 DVDD_IO DGOUT1 DGOUT2 DGOUT3 DGOUT4 DGOUT5 DGOUT6 DVSS DGOUT7 DBOUT0 DBOUT1 DVDD_IO DBOUT2 DBOUT3 DBOUT4 DVSS DBOUT5 DBOUT6 DBOUT7 PWM DVDD_CORE XRST INTO TEST DVSS SCK_SCL SRXD_SDA STXD DVDD_IO In/output format I/O P O O P O O O P O P I O O O P O O O P O O O P O O O O O O P O O O P O O O P O O O O P I O I P I I/O O P Format F F F F F G A F F F F F F F F F F F F F F F F F F F F F F F F D A D B C H D Connecting destination Core Voltage CMOS CMOS GND CMOS CMOS CMOS IO voltage CMOS GND CMOS CMOS CMOS CMOS Core Voltage CMOS CMOS CMOS GND CMOS CMOS CMOS IO voltage CMOS CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS IO voltage CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS Core Voltage CMOS CMOS CMOS GND CMOS CMOS CMOS IO voltage Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Bus clock (shared with SIO/I2C) SIO data input / I2C data input/output SIO data System reset (“L” reset) Interrupt Test setting (Connect to GND normally) B/Cb/C video output B/Cb/C video output B/Cb/C video output (MSB) Pulse width modulation waveform output B/Cb/C video output (LSB when 6-bit output is selected) B/Cb/C video output B/Cb/C video output G/Y video output (MSB) B/Cb/C video output (LSB when 8-bit output is selected) B/Cb/C video output G/Y video output G/Y video output (LSB when 6-bit output is selected) G/Y video output G/Y video output G/Y video output G/Y video output R/Cr video output R/Cr video output (MSB) G/Y video output (LSB when 8-bit output is selected) R/Cr video output R/Cr video output R/Cr video output “H” power down control (Connect to GND when not used.) R/Cr video output (LSB when 8-bit output is selected) R/Cr video output R/Cr video output (LSB when 6-bit output is selected) Video clock output Data enable signal Vertical sync signal / Start pulse signal for gate driver Horizontal sync signal / Start pulse signal for sourse driver Voltage polarity selection signal for the source driver. Reversed video signal output for DTR. Low output when the DTR is OFF. Remarks No.A1885-7/10 LC749402PT Pin Type In/Output form Function Schmitt trigger CMOS input A Equivalent circuit Application Terminal XRST, PDWN, SCS_I2SEL CMOS input with built-in pull-down resistor B TEST CMOS input SCK_SCL, SIOSEL, DVSI, DHSI, DDEI, OSDBL, DYGIN7, DYGIN6, DYGIN5, DYGIN4, DYGIN3, DYGIN2, DYGIN1, DYGIN0, DCBIN7, DCBIN6, DCBIN5, DCBIN4, DCBIN3, DCBIN2, DCBIN1, DCBIN0, DCRIN7, DCRIN6, DCRIN5, DCRIN4, DCRIN3, DCRIN2, DCRIN1, DCRIN0 C 2mA 3-STATE drive CMOS output D STXD, PWM, INTO 2mA/4mA switching 3-STATE drive CMOS output F DBOUT7, DBOUT6, DBOUT5, DBOUT4, DBOUT3, DBOUT2, DBOUT1, DBOUT0, DROUT7, DROUT6, DROUT5, DROUT4, DROUT3, DROUT2, DROUT1, DROUT0 DGOUT7, DGOUT6, DGOUT5, DGOUT4, DGOUT3, DGOUT2, DGOUT1, DGOUT0, DHSO/SP2, DVSO/FLM2, DDEO FLM, DEXR, POL, GRST, CPV, SP, OE, STRB 4mA/8mA switching 3-STATE drive CMOS output G DCKO 4mA 3-STATE drive CMOS input/output SRXD_SDA H Analog input/output J RC_BIAS No.A1885-8/10 LC749402PT I/O Timing (1) Input data timing tHI DCKI tSU tHD tLI tCK DVDD_IO/2 Input data DVDD_IO/2 Pin name DCKI Clock cycle Duty Parameter Symbol tCK min 25 typ max unit ns 50 tSU tSU tHD tHD 3 3 2 % ns ns ns Input data setup time (DVDD_IO=2.6 to 3.6V) DCRIN*, DYGIN*, DCBIN*, DVSI, DHSI, DDEI, OSDBL Input data setup time (DVDD_IO=1.7 to 1.9V) Input data hold time (DVDD_IO=2.6 to 3.6V) Input data hold time (DVDD_IO=1.7 to 1.9V) 2 ns *: The recommended duty cycle of input clock is 50% (2) Output data timing tHO tCK DVDD_IO/2 DCKO tAC tLO Output data DVDD_IO/2 Pin name DCKO Clock cycle Duty Parameter Symbol tCK min 25 typ max unit ns 50 % Output data delay time (DVDD_IO=2.6 to 3.6V) Pin F: when set to 4mA Pin G: when set to 8mA Output data delay time (DVDD_IO=2.6 to 3.6V) Pin F: when set to 2mA Pin G: when set to 4mA Output data delay time (DVDD_IO=1.7 to 1.9V) Pin F: when set to 4mA Pin G: when set to 8mA Output data delay time (DVDD_IO=1.7 to 1.9V) Pin F: when set to 2mA Pin G: when set to 4mA tAC -6 9 ns tAC -5 4 ns tAC -3 6 ns tAC -3 3 ns DROUT*, DGOUT*, DBOUT*, DVSO, DHSO, DDEO, DEXR, POL, SP, STRB, CPV, OE, FLM, GRST * When DCKO is set to the forward rotation output. Output load capacity: 5pF No.A1885-9/10 LC749402PT SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2010. Specifications and information herein are subject to change without notice. PS No.A1885-10/10