LC749403BG

Ordering number : ENA1948 CMOS IC LC749403BG Overview Silicon gate LCD Picture Quality Improvement IC LC749403BG is a IC which enables higher picture quality in LCD products by improving the signals outputed to the LCD panel. In addition to the function to improve the picture quality of the color equation and the brightness correction, smooth picture quality is realized by converting One Seg video from 15fps to 30fps using flame interpolation technique. It supports up to WVGA resolution. * Features (1) Digital Input/Output • Supports digital video input: YCbCr/YPbPr 24bit,16bit (4: 2: 2) signals or ITU-R BT.656 (8bit) input • Digital RGB 24 bit signal input • Digital RGB 18bit/24bit signal output • Digital YCbCr 16bit/24bit signal output (2) Picture Quality Improvement Function • Y signal picture quality improvement: brigntness adjustment, contour correction,CDEX (Color Depth Expander), • C signal picture quality improvement: color exciter,skin color correction,color and hue adjustment • RGB signal picture quality improvement: brightness, contrast, white balance, black balance, gamma correction (3) Panel Interface • Embedded timing controller for panel driver • Automtic timing signal generation for panel protection • PWM for backlight control (video adaptation low power consumtion processing) (4) Frame interpolation (×2) for One-Seg broadcast • Double-speed (×2) mode (15fps ⇒ 30fps) Intermediate image is predicted from the previous and next image. *: Video input of the LC749403BG meets the following conditions: (1) horizontal resolution is under 880 dots, and (2) vertical resolution is under 480 lines. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 41311HKPC 20110318-S00006 No.A1948-1/13 LC749403BG LSI Specifications • Power supply voltage (typ) Core block: 1.2V SDRAM I/F block: 1.8V I/O block: 1.8V/2.85V/3.3V selectable • Maximum operating frequency internal: 36MHz SDRAM I/F block: 80MHz • Package: FBGA144 11mm × 11mm (stacked MCP with SDRAM) Target Application • LCD display devices, One-Seg broadcast receiver (Car-Navigation, One-Seg TV, Portable DVD player, etc) Frame interpolation (×2) example Smooth image quality is realized by converting One Seg video from 15fps to 30fps using flame interpolation technique Jumpy motion Smooth motion Intermediate image is predicted from the previous and next image Interpolation OFF (15frame/s) Interpolation ON (30frame/s) Actual image Interpolated image Actual image No.A1948-2/13 LC749403BG CDEX (Color Depth Expander) Example This specification may be changed without any notices for product improvement. Original CDEX Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS_PLL = 0V, AVSS_OSC = 0V, SDVSS = 0V, SDVSSQ = 0V Parameter Maximum supply voltage (I/O) Maximum supply voltage (SDRAM, SDRAMIF I/O, PLL) Maximum supply voltage (core, osc) Digital input voltage Digital output voltage Operating temperature Storage temperature Symbol DVDD_IO DVDD_SDIO, AVDD_PLL, SDVDD, SDVDDQ DVDD_CORE AVDD_OSC VI VO Topr Tstg Conditions Ratings -0.3 to +3.96 unit V -0.3 to +2.6 V -0.3 to +1.8 -0.3 to DVDD_IO+0.3 -0.3 to DVDD_IO+0.3 -40 to +85 -55 to +125 V V V °C °C Allowable Operation Ranges at Ta = -40 to +85°C, DVSS = 0V, AVSS_PLL = 0V, AVSS_OSC = 0V, SDVSS = 0V, SDVSSQ = 0V Parameter Supply voltage (I/O) Symbol DVDD_IO Conditions min 2.6 1.7 Supply voltage (SDRAMIF I/O) Supply voltage (SDRAM, PLL) Supply voltage (core, osc) Input voltage range DVDD_SDIO SDVDD, SDVDDQ AVDD_PLL DVDD_CORE AVDD_OSC VIN 1.7 1.7 1.14 0 Ratings typ 2.85 1.8 1.8 1.8 1.2 max 3.6 1.95 1.95 1.95 1.26 DVDD_IO V V V V V V unit No.A1948-3/13 LC749403BG DC Characteristics at Ta = -40 to +85°C, DVSS = 0V, AVSS_PLL = 0V, AVSS_OSC = 0V, SDVSS = 0V, SDVSSQ = 0V, DVDD_IO = 1.7 to 3.6V, DVDD_SDIO = 1.7 to 1.95V, DVDD_CORE = 1.14 to 1.26V, SDVDD = 1.7 to 1.95V, SDVDDQ = 1.7 to 1.95V Parameter Input high-level voltage Symbol VIH Conditions min CMOS level inputs CMOS level schmitt inputs Input low-level voltage VIL CMOS level inputs CMOS level schmitt inputs Input high-level current IIH VI=DVDD_IO VI=DVDD_IO, with pull-down resistor Input low-level current Output high-level voltage IIL VOH VI=DVSS CMOS voltage: 2.6V to 3.6V, 1.7V to 1.9V I/O type D: IOH = -1mA I/O type E: IOH = -1mA (2mA mode) IOH = -2mA (4mA mode) I/O type F: IOH = -2mA (4mA mode) IOH = -4mA (8mA mode) I/O type G: IOH = -2mA I/O type H: IOH = -1mA (2mA mode) IOH = -2mA (4mA mode) Output low-level voltage Output leakage current Pull-down resistance VOL IOZ RDN CMOS In high-impedance output mode condition : typ Ta = 25°C DVDD_IO = 2.85V DVDD_CORE = 1.2V condition : typ Ta = 25°C DVDD_IO = 1.8V DVDD_CORE = 1.2V Operating current drain IDDOP condition : typ Ta = 25°C DVDD_IO = 2.85V DVDD_CORE = 1.2V QVGA, tck = 6.6MHz 10step condition : typ Ta = 25°C DVDD_IO = 2.85V DVDD_CORE = 1.2V WVGA, tck = 34.24MHz 10step Static current drain *1 IDDST condition : typ Ta = 25°C DVDD_IO = 2.85V DVDD_CORE = 1.2V Output open, VI = DVSS or DVDD_IO 35 μA 112 mA 25 mA 69 kΩ 98 kΩ 0.4 3 V μA DVDD_IO-0.4 V -10 0.7DVDD_IO 0.7DVDD_IO 0.3DVDD_IO 0.3DVDD_IO 10 100 Ratings typ max V V V V μA μA μA unit *1: Certain input pins have build-in pull-down resistors. Thus there are cases where, due to the circuit sturucture, the static current drain can not beguranteed. No.A1948-4/13 LC749403BG Package Dimensions unit : mm (typ) 3409 TOP VIEW BOTTOM VIEW 1.1 11.0 0.8 1.1 11.0 0.8 0.5 SIDE VIEW ML K J HGFEDCBA 0.4 1.4 MAX SANYO : FBGA144(11.0X11.0) Pin Assignment LC749403BG 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 11 10 12 Top View No.A1948-5/13 XRST DHSI DVSI DDEI DCKI Color Space Convert Timing Controler SDRAM Controler Frame Interpolation (×2) Panel Protection Color Depth Expander SDRAM Block Diagram DCRIN[7:0] DYGIN[7:0] DCBIN[7:0] OSDBL TEST Ocillator XTALI CTI HUE FTI Color Gain delay LTI H/V contour W/BL stretch Dynamic γ I²C/SIO LC749403BG SCK_SCL SRXD_SDA STXD SCS_I2SEL SIOSEL PDWN INTO MPU BLCON PWM PWM Color Exciter Color Space Convert White/black balance Brightness/contrast RGB γ OSD Mix Dither TCON Bypass GRST FLM OE CPV STRB SP DEXR POL DVSO DHSO DDEO DCKO DCBOUT[7:0] DYGOUT[7:0] DCROUT[7:0] LC749403BG No.A1948-6/13 LC749403BG Pin Functions Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Pin symbol AVDD_OSC RC_BIAS AVSS_OSC DHSI DDEI STXD SCK_SCL XTALI TEST AVDD_PLL PDO AVSS_PLL DCRIN2 DVDD_CORE DVSS DVSS DVSI SRXD_SDA XRST DCKI DVDD_SDIO DVSS DVSS DCKO DCRIN1 DCRIN0 SDVSS SDVSS DVDD_CORE INTO PDWN SIOSEL DVSS DVSS DHSO/SP2 DVSO/FLM2 I/O Format I/O P I P I I O I I I P O P I P P P I I/O I I P P P O I I P P P O I I P P O O Format J C C D C C B J C C G A C F C C D A C E E GND CMOS Core voltage GND GND CMOS CMOS CMOS CMOS IO voltage GND GND CMOS CMOS CMOS GND GND Core voltage CMOS CMOS CMOS GND GND CMOS CMOS Core voltage Resistor GND CMOS CMOS CMOS CMOS CMOS CMOS PLL voltage Analog Analog Analog Digital Digital Digital Digital Digital Digital Analog Analog Analog Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Horizontal synchronizing signal/Start pulse signal for source driver Vertical synchronizing signal/Start pulse signal for gate driver Interrupt “L” power down Connect this pin to GND when not to be used. ”L”: I2C slave, ”H”: 3 wire SIO Video clock output R/Cr video. Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. SDRAM ground SDRAM ground Vertical synchronizing signal SIO data input/I2C data input/output System reset (“L” reset) Video clock. R/Cr video. Connect this pin to GND when not to be used. Test (Normally, connect this pin to GND) Horizontal synchronizing signal. Data enable signal. Connect this pin to GND in the internal generation mode. SIO data Bus clock (common to SIO and I2C) Panel protection, PWM generation clock Connect this pin to GND when not to be used. Test (Normally, connect this pin to GND) Bias resistor connection (connect this pin to GND with a 20kΩ) Connecting destination Remarks Continued on next page. No.A1948-7/13 LC749403BG Continued from preceding page. Pin No. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 Pin symbol DCRIN3 DCRIN4 DCRIN5 DVSS SDVSS SDVSS SDVDD SDVDD PWM OSDBL SCS_I2SEL DDEO DCRIN7 DCRIN6 DYGIN1 DYGIN0 DVDD_IO DVDD_IO DVDD_IO DVDD_CORE DBOUT4 DBOUT5 DBOUT6 DBOUT7 DYGIN3 DYGIN2 DYGIN5 DYGIN4 DVDD_CORE DVDD_CORE DVDD_IO DVDD_CORE DBOUT1 DBOUT3 DBOUT0 DBOUT2 Input/output format I/O I I I P P P P P O I I O I I I I P P P P O O O O I I I I P P P P O O O O Format C C C D C A E C C C C E E E E C C C C E E E E CMOS CMOS CMOS GND GND GND IO voltage IO voltage CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS IO voltage IO voltage IO voltage Core voltage CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Core voltage Core voltage IO voltage Core voltage CMOS CMOS CMOS CMOS Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital B/Cb/C video B/Cb/C video B/Cb/C video (LSB) B/Cb/C video B/Cb/C video B/Cb/C video B/Cb/C video B/Cb/C video (MSB) G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. SDRAM ground SDRAM ground SDRAM power SDRAM power Pulse width modulation waveform Data enable signal for external OSD. (Connect to GND when not used.) SIO chip enable/I2C slave select Data enable signal R/Cr video(MSB). Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video (LSB). Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. Connecting destination Remarks Continued on next page. No.A1948-8/13 LC749403BG Continued from preceding page. Pin No. G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 Pin symbol DCBIN0 DYGIN6 DYGIN7 DCBIN1 DVDD_CORE DVDD_CORE DVDD_SDIO DVDD_SDIO DGOUT5 DGOUT6 DGOUT3 DGOUT7 DCBIN4 DCBIN3 DCBIN2 DCBIN5 DVDD_SDIO DVDD_SDIO DVDD_SDIO DVDD_SDIO DGOUT0 DGOUT1 DGOUT2 DGOUT4 CPV STRB DEXR DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DROUT7 Input/output format I/O I I I I P P P P O O O O I I I I P P P P O O O O I/O I/O O P P P P P P P P I/O Format C C C C E E E E C C C C E E E E H H E H CMOS CMOS CMOS CMOS Core Voltage Core Voltage IO voltage IO voltage CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS IO voltage IO voltage IO voltage IO voltage CMOS CMOS CMOS CMOS CMOS CMOS CMOS GND GND GND GND GND GND GND GND CMOS Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital R/Cr video (MSB) G/Y/656 video (LSB) G/Y/656 video G/Y/656 video G/Y/656 video Clock signal for gate driver Data strobe signal for source driver Video inverse signal output for DTR G/Y/656 video G/Y/656 video G/Y/656 video G/Y/656 video (MSB) B/Cb/C video B/Cb/C video B/Cb/C video B/Cb/C video B/Cb/C video G/Y/656 video G/Y/656 video B/Cb/C video. Connect this pin to GND when not to be used. Connecting destination Remarks Continued on next page. No.A1948-9/13 LC749403BG Continued from preceding page. Pin No. K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Pin symbol FLM OE DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DROUT0 DROUT6 DCBIN7 SP SDVDDQ SDVDDQ SDVDDQ SDVDDQ SDVDDQ SDVDDQ SDVDDQ DVSS DROUT2 DROUT5 DCBIN6 POL GRST SDVSSQ SDVSSQ SDVSSQ SDVSSQ SDVSSQ SDVSSQ DROUT1 DROUT3 DROUT4 Input/output format I/O I/O I/O P P P P P P P P I/O I/O I I/O P P P P P P P P I/O I/O I O I/O P P P P P P I/O I/O I/O Format H H H H C H H H C E H H H H CMOS CMOS GND GND GND GND GND GND GND GND CMOS CMOS CMOS CMOS IO voltage IO voltage IO voltage IO voltage IO voltage IO voltage IO voltage GND CMOS CMOS CMOS CMOS CMOS GND GND GND GND GND GND CMOS CMOS CMOS Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital R/Cr video R/Cr video B/Cb/C video. Connect this pin to GND when not to be used. Voltage polarity selection signal for source driver Reset signal for gate driver SDRAM ground *2 SDRAM ground *2 SDRAM ground *2 SDRAM ground *2 SDRAM ground *2 SDRAM ground *2 R/Cr video R/Cr video R/Cr video R/Cr video (LSB) R/Cr video B/Cb/C video (MSB). Connect this pin to GND when not to be used. Start pulse signal for source driver SDRAM power *1 SDRAM power *1 SDRAM power *1 SDRAM power *1 SDRAM power *1 SDRAM power *1 SDRAM power *1 Start pulse signal for gate driver Output enable signal for gate driver Connecting destination Remarks *1: We recommend isolated power to be supplied to SDRAM for improved noise immunity. *2: We recommend isolated ground to be supplied to SDRAM for improved noise immunity. No.A1948-10/13 LC749403BG Pin Circuits In/output form A Function Schmitt trigger CMOS input Equivalent circuit Application Terminal XRST, PDWN, SCS_I2SEL B CMOS input with built-in pull-down resister TEST C CMOS input SCK_SCL, SIOSEL, DVSI, DHSI, DDEI, OSDBL, DYGIN7, DYGIN6, DYGIN5, DYGIN4, DYGIN3, DYGIN2, DYGIN1, DYGIN0, DCBIN7, DCBIN6, DCBIN5, DCBIN4, DCBIN3, DCBIN2, DCBIN1, DCBIN0, DCRIN7, DCRIN6, DCRIN5, DCRIN4, DCRIN3, DCRIN2, DCRIN1, DCRIN0 D 2mA 3-STATE drive CMOS output STXD, PWM, INTO E 2mA/4mA switching 3-STATE drive CMOS output DBOUT7, DBOUT6, DBOUT5, DBOUT4, DBOUT3, DBOUT2, DBOUT1, DBOUT0, DGOUT7, DGOUT6, DGOUT5, DGOUT4, DGOUT3, DGOUT2, DGOUT1, DGOUT0, DHSO/SP2, DVSO/FLM2, DDEO FLM, DEXR, POL F 4mA/8mA switching 3-STATE drive CMOS output DCKO G 4mA 3-STATE drive CMOS input/output SRXD_SDA H 2mA/4mA switching 3-STATE CMOS input/output DROUT7, DROUT6, DROUT5, DROUT4, DROUT3, DROUT2, DROUT1, DROUT0, GRST, CPV, SP, OE, STRB J Analog input/output RC_BIAS No.A1948-11/13 LC749403BG Input/Output Timing (1) Input data timing tHI DCKI tSU tHD tLI DVDD_IO/2 tCK DVDD_IO/2 Input data Pin Name Clock cycle DCKI Duty Parameter tCK Symbol min 25 typ max unit ns 50 tSU tSU tHD tHD 3 3 2 2 % ns ns ns ns Input data set up time (DVDD_IO=2.6 to 3.6V) Input data set up time (DVDD_IO=1.7 to 1.95V) Input data hold time (DVDD_IO=2.6 to 3.6V) Input data hold time (DVDD_IO=1.7 to 1.95V) DCRIN*, DYGIN*, DCBIN*, DVSI, DHSI, DDEI, OSDBL *: We recommend a 50% duty cycle for the input clock. (2) Output data timing tHO tCK DVDD_IO/2 tAC tLO DCKO Output data DVDD_IO/2 Pin Name DCKO Parameter Clock cycle Duty Output data delay time (DVDD_IO=2.6 to 3.6V) I/O typ E: 4mA setting I/O typ F: 8mA setting Output data delay time (DVDD_IO=2.6 to 3.6V) I/O typ E: 2mA setting I/O typ F: 4mA setting Output data hold time (DVDD_IO=1.7 to 1.95V) I/O typ E: 4mA setting I/O typ F: 8mA setting Output data hold time (DVDD_IO=1.7 to 1.95V) I/O typ E: 2mA setting I/O typ F: 4mA setting tAC tAC tAC tAC tCK Symbol min 25 typ max unit ns 50 % -3 3 ns -3 6 ns DROUT*, DGOUT*, DBOUT*, DVSO, DHSO, DDEO, DEXR, POL, SP, STRB, CPV, OE, FLM, GRST -5 4 ns -6 9 ns *: When DCKO is set to the forward rotation output. Output load capacity: 5pF No.A1948-12/13 LC749403BG SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of April, 2011. Specifications and information herein are subject to change without notice. PS No.A1948-13/13