Ordering number : ENA1187A
LC749460W
Overview
CMOS IC
Silicon gate
Digital RGB Processor LSI
The LC749460W is RGB processor LSI which converts the interlace TV signal such as NTSC or PAL into progressive signal, optimizes and adjusts the image quality of these TV signals to the FPD devices such as LCD-TV, and output the signal that converts the resolution according to the connected panel. It optimizes LSI for the pixel display device which deals with image quality and high resolution image. A video signal processing system for flat panel display can be formatted easily by combining with microcomputer and LCD panel.
Features
(1) Analog input • Built-in 4ch A/D converter • CVBS × 2ch, S-Video, YCbCr/YPbPr input (supports 480i/576i, 480p/576p, 1080i, 720p) × 2ch (2) Digital input/output • Support digital video input: YCbCr 24-bit or YCbCr 16-bit (4:2:2) signal or ITU-R BT656 (8-bit) input • Support DTV (480i/576i, 480p/576p, 1080i, 720p) input: YCbCr/YPbPr/RGB digital 24-bit signal input • Digital RGB 30-bit (24-bit)/YCbCr 30-bit (24-bit) signal output (3) YC separation video decoder (NTSC, PAL, SECAM) • Adaptive 3D YC separation (NTSC)/Adaptive 3 or 5 line YC separation (PAL). • Digital AGC. Digital ACC (4) De-interlacing • Motion adaptive Jaggy-less De-interlacing • 2:3 pull-down, 2:2 pull-down
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: SANYO Digital Picture Improvement Core
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment.
62508HKIM / 52808HKIM B8-9279 No.A1187-1/20
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(5) Resolution Conversion • Resolution conversion (to WXGA) • PIP/POP. (6) Picture quality improvement • Noise reduction (3D NR) • Cross color/Cross luminance canceller • Horizontal edge correction (LTI/CTI), Sharpness (horizontal/vertical), Shadow adjuster • White/black stretch. Flesh tone improvement. • Hue/Color gain adjustment/Color exciter (6 phase RGBYMC Independent saturation correction). • Brightness/Contrast adjustment. White balance/Black balance adjustment. • γ correction (RGB independent, LUT system programmable). Dithering (10-bit/8-bit). Clamp control. • Clock generator (PLL)/various of Built-in interface (SDRAM IF, I2C bus, 3 wire-bus) • YUV to RGB conversion/YCbCr to RGB conversion/YPbPr to RGB conversion/RGB to YCbCr conversion
LSI Specifications
• Supply voltage Core: 1.2V, I/O block: 3.3V • Maximum operating frequency: 85MHz • Package: LQFP256
Principal Applications
• LCD TVs, monitors, and projectors, PDP TVs, progressive scan TVs, and projection TVs
1. Input
1-1 Input signal format (Digital input) Digital data port supports the following signal input formats. 24bit (4:4:4) YCbCr/RGB: NTSC/PAL (480i/576i), 480p, 576p, HD (1080i/720p) 16bit (4:2:2) YCbCr: NTSC/PAL (480i/576i), 480p, 576p, HD (1080i/720p) 8bit Based on ITU-R BT656system (H/V sync input is needed): NTSC/PAL (480i/576i) Digital 2 system input such as 16bit (4:2:2) YCbCr + 8bit (ITU-R BT656), 8bit (ITU-R BT656) + 8bit (ITU-R BT656) are possible 1-2 Input signal format (Analog input) Analog port can be connected to all of the following input. CVBS × 2ch: Composite input 2CH S-Video: S video input 1CH YPbPr input (Supports 480i/576i, 480p/576p, 1080i, 720p input): Component input 2 system
2. Digital Video Decoder Block
This LSI carries video decoder which converts the video signal of NTSC, PAL and SECAM or Component video signal into digital picture signal. It decodes Digital picture data by inputting the video signals of NTSC, PAL and SECAM which are converted from Analog to Digital. It supports composite video signal, S video signal and component signal (480i).
3. De-interlacing Block
When inputting NTSC (480i) and PAL (576i), it can implement motion adaptive De-interlacing, cinema mode de-interlace, 3D noise reduction and cross color/cross luminance canceller. At 480p, 576p, 1080i, 720p, this block is set to the through state. 3-1. Motion adaptive De-interlacing At De-interlacing block, it operates the movement detection to every pixel that inputted. As a result, it does interpolation between front and back field to the pixel that judged as static, and does interpolation inside field to the pixel that judged as move. So de-interlacing can be done. In that case, as for interpolation in between field of move part, it is possible to produce less notched (less-jaggy) and smooth image because of interpolation that considers the correlation of oblique direction.
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3-2. Cinema mode De-interlacing (3-2/2-2 pull-down) When NTSC/PAL interlace signal generated from film (cinema) source or 30p source such as cartoon are inputted, it does auto-discriminate cinema/30p source and cinema mode de-interlace that suitable for source. 3-3. 3D Noise reduction This has built-in round type 3D noise reduction function that decreases the noise between frames. In this block luminance signal and color difference signal can be processed independently. 3-4. Cross color/Cross luminance canceller This function can decrease the cross color, noise and cross luminance which are generated when NTSC input signal from composite terminal. By using this function, it can produce vivid image without color blotting and dot interruption.
4. Scaler block
It implement the up/down scaling of the various input signal of analog and digital that fixed to XGA, WXGA of output resolution. Full/panorama/zoom display is possible and maximum resolution is WXGA (1366 × 768 and 85MHz pixel clock). Additionally, this has built-in 2scaler system and enable to display 2screen such as POP/PIP.
5. Image quality adjustment block
This has various image quality blocks and enables to implement the image quality adjustment to fix with flat panel TV. 5-1. Horizontal edge correction (LTI/CTI) LTI/CTI does edge correction of input signal. It improves the sharpness of image by making the transients of input signal steep. In this case, it is possible to make natural image because there is no peak such as overshoot and undershoot attached at the edge part of image. This function operates independently luminance signal and color difference signal. 5-2. Sharpness (Horizontal/Vertical) Sharpness can do edge correction of input signal. In this function, unlike the above function, the moderate peak is added around edge correction. In this case, coring which emphasizes neither an amount of peak nor slight noise can be controlled by register. This function is operated only for luminance signal. 5-3. Shadow adjuster Shadow adjuster add the moderate peak at front and back of detected edge of input signal and with added shadow of image, so it can produce sharpness image. 5-4.White/Black Stretch As far as White-black stretch is concerned, it stretches the level of white side and black side of Y signal of YCbCr signal according to white-black peak inside picture of just before field, APL (Average Picture Level) of luminance, distribution information and microcomputer setting information. White and black peak are the max value and min value of input data in 1 field. When using white/black stretch, each setting value should be set properly. 5-5. Flesh color correction Flesh color correction can extract flesh color and adjust the fresh color without influencing other colors. 5-6. Color phase/Color gain adjustment The phase adjustment can adjust the hue on entire screen. The color gain adjustment can adjust the density of colors by controlling the gain of color phase signal. This function can adjust independently by Cb and Cr. 5-7. Color exciter Color exciter can control the gain of chroma in red, green, blue, magenta, yellow, cyan respectively. 5-8. Brightness/Contrast Brightness can adjust the brightness of entire screen, and contrast can adjust gain of brightness. 5-9. White balance/Black balance adjustment This function can do white adjustment and black adjustment of LCD panel. 5-10. Gamma correction It is possible to make the optional gamma curve that fix to LCD panel characteristic. It is also possible to adjust R, G and B independently by writing the adjustment value in LUT inside LSI 5-11. Dither When the signal processing of internal 10/12bit is output by 8/10bits, the dither rounds the 2/4bits of LSB and output it.
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6. Built-in OSD block
This function can do OSD (On Screen Display) on the image data after adjusting image quality. The amount of the expression per pixel can be selected from 16 indexes (4 bits: CLUT4) and 256 indexes (8 bits: CLUT8). The color pallet of the index can set alfa 4-bit of blending coefficient and 8-bit of green, blue, and the red. Displayed character and icon, etc. need to set the αGBR color to the color pallet and transmit the BMP data in the state of CLUT 4/8. The drawing engine is built-in, besides, it is possible not only to draw the transmitted BMP data to SDRAM but also do the rectangle drawing (including point and line drawing) and copy inside SDRAM.
7. Output/I/F/others
7-1. Matrix conversion The following Matrix conversion is possible for 2 systems after digital and analog input are selected. YCbCr to RGB YPbPr to RGB YPbPr to YCbCr RGB to YCbCr 7-2. Output format Output is possible with the following format. Digital RGB (30-bit/24-bit) Digital YCbCr (30-bit/24-bit) 7-3. Clamp control This can generate clamp signal in external LSI or in the built-in AD converter. In addition, it can generate optional pulse(“H”, “L”, “Hi-Z”) by comparing to the threshold value in the inside the LSI. 7-4. SDRAM interface This built-in SDRAM interface, the system can be made up easily by connecting 64Mbits SDRAM (512word × 32bit × 4bank) 1 piece or 128Mbits SDRAM (1024word × 32bit × 4bank) 1 piece in directly. In this case, more than“-60” speed grade of SDRAM is recommended. 7-5. External OSD interface This allows the interface with external OSD microcomputer using input pin 41 to 45 and output pin 36 to 38. It can display closed caption and teletext data. 7-6. I2C interface/3 wire bus interface It basically controls the internal register using I2C interface. The slave address can be a switch by controlling pin53 (I2C SEL) according to the system. The slave address is as follows. I2CSEL “L” “0111000+(R/W)” I2CSEL “H” “0111001+(R/W)” A part of register can be controlled by 3wire bus interface as well.
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I/O Specifications
1. Input Signals
The Kinds of Signals Video signal The Number of Pins 1 1 1 1 1 1 1 1 1 1 8 8 8 Sync signal 1 1 1 1 1 1 Data enable signal 1 1 Field signal 1 1 OSD signal 1 1 1 1 1 Pixel clock fixled oscillation 1 1 1 1 System reset Total 1 56 Pin Symbol CVBS1 CVBS2 ASYIN ASCIN AYIN1 ACBIN1 ACRIN1 AYIN2 ACBIN2 ACRIN2 YGI CBI CRI HS1I VS1I HS2I VS2I SHSI SVSI HE1I VE1I FLD1I FLD2I OSDG OSDB OSDR OSDEN OSDAL CK1I CK2I XTAL1 XTAL2 XRST Horizontal sync signal Vertical sync signal Horizontal sync signal Vertical sync signal Horizontal sync signal Vertical sync signal Data enable Vertical data enable Field Field External OSD signal G External OSD signal B External OSD signal R External OSD enable External OSD blending enable Pixel clock Pixel clock System clock System clock System reset Pixel clock input for digital input 1 Pixel clock input for digital input 2 Fixed clock input 1 Fixed clock input 2 System reset input negative-logic Digital video signal Explanation Analog video signal Remarks NTSC/PAL input 1 NTSC/PAL input 2 S-Video input Y S-Video input C Component input Y1 Component input Cb1 Component input Cr1 Component input Y2 Component input Cb2 Component input Cr2 Y or G or SY input Cb or B or YC input Cr or R or ITU-R BT656 input Horizontal sync signal for digital input 1 Vertical sync signal for digital input 1 Horizontal sync signal for digital input 2 Vertical sync signal for digital input 2 Horizontal sync signal for analog input Vertical sync signal for analog input Data enable (Horizontal/Composite) for digital input 1 Data enable (Vertical) for digital input 1 Field signal input for digital input 1 Field signal input for digital input 2
2. Output signal
The Kinds of Signals Video signal The Number of Pins 10 10 10 1 Sync signal 1 1 Data enable signal Field signal Pixel clock OSD signal 1 1 1 1 1 1 Pin Symbol YGO CBO CRO SVO HSO VSO DEO FLDO CKO OSDHO OSDVO OSDCKO Analog video signal Horizontal sync signal Vertical sync signal Data enable Field Pixel clock External OSD Horizontal sync signal External OSD Vertical sync signal External OSD pixel clock Field output or vertical data enable output Monitor output Explanation Digital video signal Remarks RGB/YCbCr output Dithered 8bit output is possible.
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The Kinds of Signals Clamp pulse Clamp level The Number of Pins 1 1 1 1 1 1 1 1 1 1 1 PWM output Charge pump output Total 1 1 52 Pin Symbol CLPP CLPCVBS1 CLPCVBS2 CLPSY CLPSC CLPY1 CLPCB1 CLPCR1 CLPY2 CLPCB2 CLPCR2 PWMO CHPMPDO Explanation Clamp pulse for External ADC Clamp level for CVBS1 Clamp level for CVBS2 Clamp level for SY Clamp level for SC Clamp level for Y1 Clamp level for CB1 Clamp level for CR1 Clamp level for Y2 Clamp level for CB2 Clamp level for CR2 PWM Charge pump for built-in PLL Remarks Pulse output to check AD clamp period Clamp level discriminator output (large: L, small: H, Coincident: Hi-Z)
3. Control signal
The Kinds of Signals I2C bus The Number of Pins 1 1 1 Pin Symbol SDA SCL I2CSEL I2C data I2C clock I2C slave address switch Low: “0111000+(R/W)” High: “0111001+(R/W)” Normally “L” 3-wire bus 1 1 1 Total 6 AIDA AICS AICK 3-wire bus data input/output 3-wire bus chip select 3-wire bus clock Explanation Remarks
4. SDRAM control signal
The Kinds of Signals clock The Number of Pins 1 1 Control system signal 1 1 1 Address system 11 4 Data system 4 32 Total 56 Pin Symbol SDCKI SDCKO SDRAS SDCAS SDWE SDAD SDBS SDDQM SDDQ Clock input Clock output Row address strobe signal output Column address strobe signal output Write enable signal output Address signal output Bank select signal output SDRAM data mask signal output Data input/output Explanation Remarks
5. Other signals
The Kinds of Signals SCAN test The Number of Pins 1 1 Test ADC/AFE 2 4 4 4 4 Total 20 Pin Symbol SCANMD SCANEN TEST VRT VRB DACREFP DACREFM Reference output for ADC SCAN test SCAN test Test setting Reference input for ADC Explanation Remarks Generally fixed as “L” Generally fixed as “L” Generally fixed as “L”
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Package Dimensions
unit : mm (typ) 3365
30.0
0.5 28.0
28.0
256 1 0.4 (1.4)
(1.4)
0.16
30.0
0.125
1.6 MAX
0.1
SANYO : LQFP256K(28X28)
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Pin Assignment
192
190
185
180
175
170
165
160
155
150
145
140
135
DVDD33 DVSS33 CK1I VS1I FLD1I YGI7 YGI6 YGI5 YGI4 YGI3 YGI2 YGI1 YGI0 DVDD12 DVSS12 CBI7 CBI6 CBI5 CBI4 CBI3 CBI2 CBI1 CBI0 APVDD0 CHPMPDO APVSS0 AVDD33_0 AYIN2 AVSS33_0 AYIN1 VRB0 DACREFM0 VRT0 DACREFP0 ACBIN2 AVDD33_1 ACBIN1 AVSS33_1 ASCIN VRB1 DACREFM1 VRT1 DACREFP1 SVO ATBI0 GUARD ASYIN AVDD33_2 ACVBS1 AVSS33_2 ACVBS2 VRB2 DACREFM2 VRT2 DACREFP2 ACRIN2 AVDD33_3 ACRIN1 AVSS33_3 VRB3 DACREFM3 NC NC NC
193 195 128 125 200 120 205 115 210 110 215 105 220 SDDQ14 SDDQ15 SDDQ7 SDDQ6 DVSS33 DVDD33 SDDQ5 SDDQ4 SDDQ3 SDDQ2 SDDQ1 SDDQ0 DVSS33 DVDD33 DVSS12 DVDD12 PWMO FLDO/VEO DEO/HEO CKO HSO VSO CRO0 CRO1 CRO2 CRO3 CRO4 DVSS33 DVDD33 CRO5 CRO6 CRO7 CRO8 CRO9 CBO0 CBO1 CBO2 CBO3 CBO4 CBO5 CBO6 CBO7 DVSS33 DVDD33 DVSS12 DVDD12 CBO8 CBO9 YGO0 YGO1 YGO2 YGO3 YGO4 YGO5 YGO6 YGO7 YGO8 YGO9 XRST DVSS33 DVDD33 DPVSS2 DPVDD2 APVSS2
130 129 100 95 90 85 80 75 70 65 60 64
225
230
235
240
245
250
255 256
10
15
20
25
30
35
40
45
50
VRT3 DACREFP3 ATBP ATBM DVDD12 DVSS12 SHSI SVSI CRI7 CRI6 CRI5 CRI4 CRI3 CRI2 CRI1 CRI0 HS2I VS2I CK2I FLD2I DVDD12 DVSS12 DVDD33 DVSS33 CLPP CLPY1 DTBO0 DTBO1 DTBO2 CLPCB2 CLPCB1 DTBO3 CLPCR2 CLPCR1 CLPY2 OSDHO OSDVO OSDCKO DVDD33 DVSS33 OSDG OSDB OSDR OSDEN OSDAL AICK AIDA AICS SDA SCL DVDD12 DVSS12 I2CSEL XTAL1 SCANMD SCANEN XTAL2 TEST0 TEST1 DPVSS1 DPVDD1 APVSS1 APVDD1 APVDD2
55
1
5
HS1I VE1I HE1I SDDQ16 SDDQ17 SDDQ18 SDDQ19 DVSS33 DVDD33 SDDQ20 SDDQ21 SDDQ22 SDDQ23 SDDQ24 SDDQ25 DVSS33 DVDD33 DVSS12 DVDD12 SDDQ26 SDDQ27 SDDQ28 SDDQ29 SDDQ30 SDDQ31 DVSS33 DVDD33 SDDQM3 SDDQM2 SDAD3 SDAD4 SDAD5 SDAD6 SDAD7 SDAD8 SDAD9 DVSS33 DVDD33 SDAD2 SDAD1 SDAD0 SDAD10 SDBS1 SDBS0 SDAD11 SDRAS SDCAS SDWE DVSS12 SDCKI DVDD12 DVSS33 SDCKO DVDD33 SDDQM1 SDDQM0 SDDQ8 SDDQ9 SDDQ10 SDDQ11 DVSS33 DVDD33 SDDQ12 SDDQ13
LC749460W
Top view
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Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin symbol VRT3 DACREFP3 ATBP ATBM DVDD12 DVSS12 SHSI SVSI CRI7 CRI6 CRI5 CRI4 CRI3 CRI2 CRI1 CRI0 HS2I VS2I CK2I FLD2I DVDD12 DVSS12 DVDD33 DVSS33 CLPP CLPY1 DTBO0 DTBO1 DTBO2 CLPCB2 CLPCB1 DTBO3 CLPCR2 CLPCR1 CLPY2 OSDHO OSDVO OSDCKO DVDD33 DVSS33 OSDG OSDB OSDR OSDEN OSDAL AICK AIDA AICS SDA SCL DVDD12 In/output format I/O I O I I P P I I I I I I I I I I I I I I P P P P O O O O O O O O O O O O O O P P I I I I I I B I B I P D H D H D Power supply I2C bus C Power supply GND E External OSD Hsync signal output terminal External OSD Vsync signal output terminal External OSD output pixel clock Digital 3.3V system power supply Digital 3.3V system GND G signal input for OSD B signal input for OSD R signal input for OSD OSD input enable OSD blending enable 3-wire bus clock terminal 3-wire bus data input/output terminal 3-wire bus chip select terminal I2C bus data input/output terminal I2C bus clock terminal Digital 1.2V system power supply Open Digital test output terminal Clamp control terminal E F Open Open Open Clamp control terminal C C A C Power supply GND Power supply GND Horizontal sync signal input terminal for D2 input Vertical sync signal input terminal for D2 input Clock input terminal for D2 input Field signal input terminal for D2 input Digital 1.2V power supply Digital 1.2V GND Digital 3.3V power supply Digital 3.3V GND Clamp pulse output terminal Clamp control terminal Digital test output terminal C D C Format I I I I Open Open Power supply GND Connecting destination Remarks ADC3 reference power supply input ADC3 reference power supply output ADC ATB (Analog Test Bus) Analog input + terminal ADC ATB (Analog Test Bus) Analog input - terminal Digital 1.2V system power supply Digital 1.2V system GND External horizontal sync signal input External vertical sync signal input Cr/R signal input
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Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Pin symbol DVSS12 I2CSEL XTAL1 SCANMD SCANEN XTAL2 TEST0 TEST1 DPVSS1 DPVDD1 APVSS1 APVDD1 APVDD2 APVSS2 DPVDD2 DPVSS2 DVDD33 DVSS33 XRST YGO9 YGO8 YGO7 YGO6 YGO5 YGO4 YGO3 YGO2 YGO1 YGO0 CBO9 CBO8 DVDD12 DVSS12 DVDD33 DVDD33 CBO7 CBO6 CBO5 CBO4 CBO3 CBO2 CBO1 CBO0 CRO9 CRO8 CRO7 CRO6 CRO5 DVDD33 DVSS33 CRO4 CRO3 CRO2 In/output format I/O P I I I I I I I P P P P P P P P P P I O O O O O O O O O O O O P P P P O O O O O O O O O O O O O P P O O O E Power supply GND Digital 3.3V system power supply Digital 3.3V system GND Digital R signal input terminal E Digital R signal output terminal E Power supply GND Power supply GND Digital 1.2V system power supply Digital 1.2V system GND Digital 3.3V system power supply Digital 3.3V system GND Digital B signal output terminal E Digital B signal output terminal B E GND Power supply GND Power supply Power supply GND Power supply GND Power supply GND Initial circuit Digital GND for PLL1 Digital 1.2V system power supply for PLL1 Analog GND for PLL1 Analog 3.3V system power supply for PLL1 Analog 3.3V system power supply for PLL2 Analog GND for PLL2 Digital 1.2V system power supply for PLL2 Digital GND for PLL2 Digital 3.3V system power supply Digital 3.3V system GND System reset terminal (“L” reset) Digital G signal output terminal D A D D A D Open XTAL (for PLL2) input terminal Test terminal Open Format Connecting destination GND Digital 1.2V system GND I2C bus slave address selection input XTAL (for PLL1) input terminal Test terminal Remarks
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Terminal No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 Terminal symbol CRO1 CRO0 VSO HSO CKO DEO/HEO FLDO/VEO PWMO DVDD12 DVSS12 DVDD33 DVSS33 SDDQ0 SDDQ1 SDDQ2 SDDQ3 SDDQ4 SDDQ5 DVDD33 DVSS33 SDDQ6 SDDQ7 SDDQ15 SDDQ14 SDDQ13 SDDQ12 DVDD33 DVSS33 SDDQ11 SDDQ10 SDDQ9 SDDQ8 SDDQM0 SDDQM1 DVDD33 SDCKO DVSS33 DVDD12 SDCKI DVSS12 SDWE SDCAS SDRAS SDAD11 SDBS0 SDBS1 SDAD10 SDAD0 SDAD1 SDAD2 DVDD33 DVSS33 SDAD9 SDAD8 In/output format I/O O O O O O O O O P P P P B B B B B B P P B B B B B B P P B B B B O O P O P P I P O O O O O O O O O O P P O O G Power supply GND SDRAM Digital 3.3V system power supply Digital 3.3V system GND SDRAM address output terminal G SDRAM G G SDRAM SDRAM G A G Power supply SDRAM GND Power supply SDRAM GND SDRAM G SDRAM SDRAM DQM0 output terminal SDRAM DQM1 output terminal Digital 3.3V system power supply SDRAM clock output terminal Digital 3.3V system GND Digital 1.2V system power supply SDRAM clock input terminal Digital 1.2V system GND SDRAM write enable output terminal SDRAM column address strobe output terminal SDRAM low address strobe output terminal SDRAM address output terminal SDRAM bank 0 selection output terminal SDRAM bank 1 selection output terminal SDRAM address output terminal H Power supply GND SDRAM Digital 3.3V system power supply Digital 3.3V system GND SDRAM data input/output terminal H Power supply GND SDRAM Digital 3.3V system power supply Digital 3.3V system GND SDRAM data input/output terminal H E E G E E G Power supply GND Power supply GND SDRAM Vertical sync signal output terminal Horizontal sync signal output terminal Pixel clock output terminal Data enable /horizontal data enable output terminal Field signal/vertical data enable output terminal PWM output terminal Digital 1.2V system power supply Digital 1.2V system GND Digital 3.3V system power supply Digital 3.3V system GND SDRAM data input/output terminal Format E Connection destination Digital R signal input terminal Remarks
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Terminal No. 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Terminal symbol SDAD7 SDAD6 SDAD5 SDAD4 SDAD3 SDDQM2 SDDQM3 DVDD33 DVSS33 SDDQ31 SDDQ30 SDDQ29 SDDQ28 SDDQ27 SDDQ26 DVDD12 DVSS12 DVDD33 DVSS33 SDDQ25 SDDQ24 SDDQ23 SDDQ22 SDDQ21 SDDQ20 DVDD33 DVSS33 SDDQ19 SDDQ18 SDDQ17 SDDQ16 HE1I VE1I HS1I DVDD33 DVSS33 CK1I VS1I FLD1I YGI7 YGI6 YGI5 YGI4 YGI3 YGI2 YGI1 YGI0 DVDD12 DVSS12 CBI7 CBI6 CBI5 In/output format I/O O O O O O O O P P B B B B B B P P P P B B B B B B P P B B B B I I I P P I I I I I I I I I I I P P I I I C Power Supply GND 1.2V system power supply 1.2V system GND C/Cb/B signal input A C C C C C C Power Supply GND Horizontal data enable signal input terminal for digital input 1 Vertical data enable signal input terminal for digital input 1 Horizontal sync signal input terminal for digital input 1 Digital 3.3V system power supply Digital 3.3V system GND Pixel clock input terminal for digital input 1 Vertical sync signal input terminal for digital input 1 Field discrimination signal input terminal for digital input 1 SY/Y/G signal input H Power supply GND SDRAM Digital 3.3V system power supply Digital 3.3V system GND SDRAM data input/output terminal H Power supply GND Power supply GND SDRAM Digital 1.2V system power supply Digital 1.2V system GND Digital 3.3V system power supply Digital 3.3V system GND SDRAM data input/output terminal H Power supply GND SDRAM G SDRAM SDRAM DQM2 output terminal SDRAM DQM3 output terminal Digital 3.3V system power supply Digital 3.3V system GND SDRAM data input/output terminal Format G Connection destination SDRAM Remarks SDRAM address output terminal
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LC749460W
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Terminal No. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Terminal symbol CBI4 CBI3 CBI2 CBI1 CBI0 APVDD0 CHPMPDO APVSS0 AVDD33_0 AYIN2 AVSS33_0 AYIN1 VRB0 DACREFM0 VRT0 DACREFP0 ACBIN2 AVDD33_1 ACBIN1 AVSS33_1 ASCIN VRB1 DACREFM1 VRT1 DACREFP1 SVO ATBI0 GUARD ASYIN AVDD33_2 ACVBS1 AVSS33_2 ACVBS2 VRB2 DACREFM2 VRT2 DACREFP2 ACRIN2 AVDD33_3 ACRIN1 AVSS33_3 VRB3 DACREFM3 NC NC NC In/output format I/O I I I I I P O P P I P I I O I O I P I P I I O I O O I I I P I P I I O I O I P I P I O I I I I I I I I I Analog I/F Power supply Analog I/F GND I I I I I I I I I I Analog I/F Open GND Analog I/F Power supply Analog I/F GND Analog I/F I I I I I I I Analog I/F Power supply Analog I/F GND Analog I/F I I GND Power Supply Analog I/F GND Analog I/F Power Supply Analog power supply for PLL0 Charge pump output Analog GND for PLL0 Analog 3.3V system power supply for ADC0 Analog Y2 signal input Analog 3.3V system GND for ADC0 Analog Y1 signal input ADC0 reference power supply output ADC0 reference power supply output ADC0 reference power supply output ADC0 reference power supply output Analog Cb2 signal input Analog 3.3V system power supply for ADC1 Analog Cb1 signal input Analog 3.3V system GND for ADC1 Analog SC signal input ADC1 reference power supply input ADC1 reference power supply output ADC1 reference power supply input ADC1 reference power supply output Analog signal input Analog test input terminal Analog guard band terminal Analog SY signal input Analog 3.3V system power supply for ADC2 Analog CVBS1 signal input Analog 3.3V system GND for ADC2 Analog CVBS2 signal input ADC2 reference power supply input ADC2 reference power supply output ADC2 reference power supply input ADC2 reference power supply output Analog Cr2 signal input Analog 3.3V system power supply for ADC3 Analog Cr1 signal input Analog 3.3V system GND for ADC3 ADC3 reference power supply input ADC3 reference power supply output Format C Connection destination C/Cb/B signal input Remark
No.A1187-13/20
LC749460W
Pin Type
In/Output form A Function 5V tolerant input Equivalent circuit Application Terminal CK1I, CK2I, XTAL1, XTAL2, SDCKI,
B
5V tolerant schmitt trigger input
XRST
C
5V tolerant with pulldown input
YGI0 to 7, CBI0 to 7, CRI0 to 7, HE1I, VE1I, HS1I, VS1I, FLD1I, HS2I, VS2I, FLD2I, SHSI, OSDG, OSDB, OSDR, OSDEN, OSDAL
D
5V tolerant with pull down schmitt trigger input
SVSI, AICK, AICS, SCL, I2CSEL, SCANMD, SCANEN (*No use OPEN), TEST0, TEST1
E
8mA 3-STATE drive input
YGO0 to 9, CBO0 to 9, CRO0 to 9 VSO, HSO, DEO/HEO, FLDO/VEO, CLPP, OSDHO, OSDVO, OSDCKO
F
8mA 3-STATE drive input
DTBO0 to 3, CLPY1 CLPCB1, CLPCR1, CLPY2 CLPCB2, CLPCR2
G
12mA 3-STATE drive input
CKO, SDCKO, PWMO, SDRAS, SDCAS, SDWE, SDAD0 to 11, SDBS0 to 1, SDDQM0 to 3
H
5V tolerant 12mA 3-STATE drive input/output
AIDA, SDA, SDDQ0 to 31
I
Analog input/output
VRT0 to 3, VRB0 to 3, DACREFP0 to 3, DACREFM0 to 3, ATBP, ATBM, CHPMPDO, SVO, GUARD, ACVBS1, ACVBS2, ASYIN, ASCIN, AYIN1, AYIN2, ACBIN1, ACBIN2, ACRIN1, ACRIN2, ATBI0
No.A1187-14/20
LC749460W
Electrical Characteristics
Absolute Maximum Ratings VSS = 0V
Parameter Max supply voltage (I/O) Max supply voltage (core) Input voltage Output voltage Storage temperature Operating temperature Max supply current Symbol DVDD33 AVDD33 DVDD12 AVDD12 VI VO Tstg Topr Pd max Rating -0.3 to +3.96 -0.3 to +1.44 -0.5 to 6.0 -0.3 to VDD +0.3 -55 to +125 -30 to +70 TDB Unit V V V V °C °C W
Allowable Operation Range at Ta = -30 to +70°C
Parameter Supply voltage (I/O) Supply voltage (core) Supply voltage (Analog) Supply voltage (PLL) Input voltage range Symbol DVDD33 VDD12 AVDD33 APVDD VIN min 3.15 1.08 3.15 3.15 0 typ 3.3 1.2 3.3 3.3 max 3.45 1.32 3.45 3.45 5.5 Unit V V V V V
I/O terminal Capacitance at Ta = 25°C, VDD = VI = 0V
Parameter Input terminal Output terminal I/O terminal Symbol CIN COUT CI/O f=1MHz f=1MHz f=1MHz Conditions min typ max 10 10 10 Unit pF pF pF
DC Characteristics at Ta = -30 to +70°C, VDD33 = 3.15 to 3.45V, VDD12 = 1.08V to 1.32V
Parameter Input high-level voltage VIH Input low-level voltage VIL Input high-level current IIH Input low-level current Output high-level voltage Output low-level voltage Output leak current Pull-down resistor Dynamic supply current Static supply current *1 IIL VOH VOL IOZ RDN IDDOP IDDST tCK=85MHz Output release, VI=VSS or VDD Symbol Conditions Input with 5V tolerant Schmitt input with 5V tolerant Input with 5V tolerant Schmitt input with 5V tolerant VI=VDD VI=VDD, with pull-down resistance VI=VSS CMOS CMOS At output of high-impedance -10 50 97 TBD TBD min 2.0 2.0 -0.3 -0.3 -10 +10 -10 2.4 0.4 +10 272 typ max 5.5 5.5 +0.8 +0.8 +10 +100 +10 Unit V V V V μA μA μA V V μA kΩ mA μA
*1: There is a input terminal which builds in pull down resistance. Please note that there is no guarantee about static consumption current depending on circuit composition.
No.A1187-15/20
LC749460W
A/D Convertor Characteristics at Ta = -30 to +70°C, DVSS = 0V, AVSS = 0V Electric characteristic
Parameter Sampling frequency Clamp pulse width Analog input coupling capacitor Analog input frequency Analog input amplitude SVO amplifier bandwidth SVO amplifier output load capacitor External between DACREFP/DACREFM capacitor Symbol FCLK Tcl Cal Fal Val FSVO CSVO CEXT 0.08 0.1 Conditions min 10 0.45 0.1 30 1.0 5 20 1 typ max 80 unit MHz μs μF MHz Vp-p MHz pF μF
ADC Characteristics
Parameter resolution ENOB ENOB Derivative linearity error DNL Integral linearity error INL Operation power current 3.3V power 1.2V power Standby power current 3.3V power 1.2V power IDD3 IDD ISB3 ISB Symbol NOB *1 *2 *1 *2 *1 *2 *2, *3 *2, *3 *3 *3 -10 -10 Conditions min typ 10 8 7.5 0.5 0.5 2 2 60 1.5 +10 +10 max Unit bits bits bits LSB LSB LSB LSB mA mA μA μA
*1 VDD3=3.3V, Fclk=27MHz, Fin=100KHz *2 VDD3=3.3V, Fclk=80MHz, Fin=100KHz *3 It describes value per 1ch Note: ADC cannot standby. Apply a square wave with a constant frequency when ADC is not to be used. I/O Data Timing (1) Input data timing 1
tHI CLK tSU tHD Input data VDD33/2 tLO tCK VDD33/2
Pin name CK1I, CK2I
Parameter Clock L-level time Clock H-level time Clock cycle
Symbol tLO tHI tCK tSU tHD
min 6.25 6.25 12.5 2 1
max
Unit ns ns ns ns ns
YGI [7:0], CBI [7:0], CRI [7:0], HE1I, VE1I, HS1I, VS1I, FLD1I, HS2I, VS2I, FLD2I
Input data setup time Input data hold time
* The recommended duty cycle of input clock is 50%
No.A1187-16/20
LC749460W
(2) Input data timing 2
tHI SDCKI tSU Input data tHD tLO VDD33/2 tCK VDD33/2
Pin name SDCKI
Parameter Clock L-level time Clock H-level time Clock cycle
Symbol tLO tHI tCK tSU tHD
min 3.00 3.00 6.00 2 1
max
Unit ns ns ns ns ns
SDDQ [31:0]
Input data setup time Input data hold time
(3) Output data timing 1
tHI CKO tAC tHD Output data VDD33/2 tLO tCK VDD33/2
Pin name CKO
Parameter Clock L-level time Clock H-level time Clock cycle
Symbol tLO tHI tCK tAC tHD
min 5.88 5.88 11.76 -1.5 9.00
max
Unit ns ns ns +1.5 ns ns
YGO [9:0], CBO [9:0], CRO [9:0], VSO, HSO, DEO/HEO, FLDO/VEO, OSDHO, OSDVO, OSDCKO
Output data delay time Output data hold time
(4) Output data timing 2
tHI SDCKO tAC tHD tLO
tCK VDD33/2
Output data
VDD33/2
Pin name SDCKO
Parameter Clock L-level time Clock H-level time Clock cycle
Symbol tLO tHI tCK tAC tHD
min 3.00 3.00 6.00 -1.0 4
max
Unit ns ns ns +1.0 ns ns
SDRAS, SDCAS, SDWE, SDAD [11:0], SDBS [1:0], SDDQM [3:0]
Output data delay time Output data hold time
No.A1187-17/20
LC749460W
(5) Output data timing 3
tHI tCK VDD33/2 tHD tLO
OSDCKO
tAC
Output data
VDD33/2
Pin name OSDCKO
Parameter Clock L-level time Clock H-level time Clock cycle
Symbol tLO tHI tCK tAC tHD
min 5.88 5.88 11.76 -1.5 9.00
max
Unit ns ns ns +1.5 ns ns
OSDHO, OSDVO, OSDCKO
Output data delay time Output data hold time
No.A1187-18/20
LC749460W
Block Diagram
ITU-R BT656 (8bits)
Satellite/Terrestrial (Digital 16bits)
CVBS, Y-C, YCbCr, YPbPr 64Mbit SDRAM (512kword×32bit×4banks) or 128Mbit SDRAM (1024kword×32bit×4banks)
LC749460W
Memory I/F
4ch 10bit ADCs & AFE
Video Decoder 3D-NR S W
DeInterlacer MotionDet. Film mode CrossColor Luminance Cancel
Picture Quality Improvement POP PIP Scaler White/Black Stretch FTI
OSD
Gamma Dithering
LVDS Tx
LCD Panel (WXGA)
16 Brightness Contrast 8
CLK PLL I²C 3wire BUS
I²C BUS
3wire BUS
Ext. OSD
No.A1187-19/20
LC749460W
Application Circuit example
LC749460W
Tuner CVBS Y/C CVBS CVBS Y Y C Y/Cb/Cr Y/Cb/Cr Cb Cb Cr Cr Y 8 Sub Video Decoder 16 Hs/Vs LV78200 Sync Sep SW ADC CH1 SW ADC CH2
SDRAM
Video decoder De-Interlacer Scaler POP/PIP Picture Improve LVDS Tx WXGA LCD-Panel
SW ADC CH3 ADC CH0
MPEG2 Decoder
Micro-controller
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T his catalog provides information as of June, 2008. Specifications and information herein are subject to change without notice.
PS No.A1187-20/20
